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ARM: tegra30: Separate out clk ops and clk data
[deliverable/linux.git] / arch / arm / mach-tegra / tegra30_clocks_data.c
1 /*
2 * arch/arm/mach-tegra/tegra30_clocks_data.c
3 *
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/list.h>
24 #include <linux/spinlock.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29 #include <linux/cpufreq.h>
30
31 #include <asm/clkdev.h>
32
33 #include <mach/iomap.h>
34
35 #include "clock.h"
36 #include "fuse.h"
37 #include "tegra30_clocks.h"
38
39 /* Clock definitions */
40 static struct clk tegra_clk_32k = {
41 .name = "clk_32k",
42 .rate = 32768,
43 .ops = NULL,
44 .max_rate = 32768,
45 };
46
47 static struct clk tegra_clk_m = {
48 .name = "clk_m",
49 .flags = ENABLE_ON_INIT,
50 .ops = &tegra30_clk_m_ops,
51 .reg = 0x1fc,
52 .reg_shift = 28,
53 .max_rate = 48000000,
54 };
55
56 static struct clk tegra_clk_m_div2 = {
57 .name = "clk_m_div2",
58 .ops = &tegra_clk_m_div_ops,
59 .parent = &tegra_clk_m,
60 .mul = 1,
61 .div = 2,
62 .state = ON,
63 .max_rate = 24000000,
64 };
65
66 static struct clk tegra_clk_m_div4 = {
67 .name = "clk_m_div4",
68 .ops = &tegra_clk_m_div_ops,
69 .parent = &tegra_clk_m,
70 .mul = 1,
71 .div = 4,
72 .state = ON,
73 .max_rate = 12000000,
74 };
75
76 static struct clk tegra_pll_ref = {
77 .name = "pll_ref",
78 .flags = ENABLE_ON_INIT,
79 .ops = &tegra_pll_ref_ops,
80 .parent = &tegra_clk_m,
81 .max_rate = 26000000,
82 };
83
84 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
85 { 12000000, 1040000000, 520, 6, 1, 8},
86 { 13000000, 1040000000, 480, 6, 1, 8},
87 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
88 { 19200000, 1040000000, 325, 6, 1, 6},
89 { 26000000, 1040000000, 520, 13, 1, 8},
90
91 { 12000000, 832000000, 416, 6, 1, 8},
92 { 13000000, 832000000, 832, 13, 1, 8},
93 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
94 { 19200000, 832000000, 260, 6, 1, 8},
95 { 26000000, 832000000, 416, 13, 1, 8},
96
97 { 12000000, 624000000, 624, 12, 1, 8},
98 { 13000000, 624000000, 624, 13, 1, 8},
99 { 16800000, 600000000, 520, 14, 1, 8},
100 { 19200000, 624000000, 520, 16, 1, 8},
101 { 26000000, 624000000, 624, 26, 1, 8},
102
103 { 12000000, 600000000, 600, 12, 1, 8},
104 { 13000000, 600000000, 600, 13, 1, 8},
105 { 16800000, 600000000, 500, 14, 1, 8},
106 { 19200000, 600000000, 375, 12, 1, 6},
107 { 26000000, 600000000, 600, 26, 1, 8},
108
109 { 12000000, 520000000, 520, 12, 1, 8},
110 { 13000000, 520000000, 520, 13, 1, 8},
111 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
112 { 19200000, 520000000, 325, 12, 1, 6},
113 { 26000000, 520000000, 520, 26, 1, 8},
114
115 { 12000000, 416000000, 416, 12, 1, 8},
116 { 13000000, 416000000, 416, 13, 1, 8},
117 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
118 { 19200000, 416000000, 260, 12, 1, 6},
119 { 26000000, 416000000, 416, 26, 1, 8},
120 { 0, 0, 0, 0, 0, 0 },
121 };
122
123 static struct clk tegra_pll_c = {
124 .name = "pll_c",
125 .flags = PLL_HAS_CPCON,
126 .ops = &tegra30_pll_ops,
127 .reg = 0x80,
128 .parent = &tegra_pll_ref,
129 .max_rate = 1400000000,
130 .u.pll = {
131 .input_min = 2000000,
132 .input_max = 31000000,
133 .cf_min = 1000000,
134 .cf_max = 6000000,
135 .vco_min = 20000000,
136 .vco_max = 1400000000,
137 .freq_table = tegra_pll_c_freq_table,
138 .lock_delay = 300,
139 },
140 };
141
142 static struct clk tegra_pll_c_out1 = {
143 .name = "pll_c_out1",
144 .ops = &tegra30_pll_div_ops,
145 .flags = DIV_U71,
146 .parent = &tegra_pll_c,
147 .reg = 0x84,
148 .reg_shift = 0,
149 .max_rate = 700000000,
150 };
151
152 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
153 { 12000000, 666000000, 666, 12, 1, 8},
154 { 13000000, 666000000, 666, 13, 1, 8},
155 { 16800000, 666000000, 555, 14, 1, 8},
156 { 19200000, 666000000, 555, 16, 1, 8},
157 { 26000000, 666000000, 666, 26, 1, 8},
158 { 12000000, 600000000, 600, 12, 1, 8},
159 { 13000000, 600000000, 600, 13, 1, 8},
160 { 16800000, 600000000, 500, 14, 1, 8},
161 { 19200000, 600000000, 375, 12, 1, 6},
162 { 26000000, 600000000, 600, 26, 1, 8},
163 { 0, 0, 0, 0, 0, 0 },
164 };
165
166 static struct clk tegra_pll_m = {
167 .name = "pll_m",
168 .flags = PLL_HAS_CPCON | PLLM,
169 .ops = &tegra30_pll_ops,
170 .reg = 0x90,
171 .parent = &tegra_pll_ref,
172 .max_rate = 800000000,
173 .u.pll = {
174 .input_min = 2000000,
175 .input_max = 31000000,
176 .cf_min = 1000000,
177 .cf_max = 6000000,
178 .vco_min = 20000000,
179 .vco_max = 1200000000,
180 .freq_table = tegra_pll_m_freq_table,
181 .lock_delay = 300,
182 },
183 };
184
185 static struct clk tegra_pll_m_out1 = {
186 .name = "pll_m_out1",
187 .ops = &tegra30_pll_div_ops,
188 .flags = DIV_U71,
189 .parent = &tegra_pll_m,
190 .reg = 0x94,
191 .reg_shift = 0,
192 .max_rate = 600000000,
193 };
194
195 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
196 { 12000000, 216000000, 432, 12, 2, 8},
197 { 13000000, 216000000, 432, 13, 2, 8},
198 { 16800000, 216000000, 360, 14, 2, 8},
199 { 19200000, 216000000, 360, 16, 2, 8},
200 { 26000000, 216000000, 432, 26, 2, 8},
201 { 0, 0, 0, 0, 0, 0 },
202 };
203
204 static struct clk tegra_pll_p = {
205 .name = "pll_p",
206 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
207 .ops = &tegra30_pll_ops,
208 .reg = 0xa0,
209 .parent = &tegra_pll_ref,
210 .max_rate = 432000000,
211 .u.pll = {
212 .input_min = 2000000,
213 .input_max = 31000000,
214 .cf_min = 1000000,
215 .cf_max = 6000000,
216 .vco_min = 20000000,
217 .vco_max = 1400000000,
218 .freq_table = tegra_pll_p_freq_table,
219 .lock_delay = 300,
220 .fixed_rate = 408000000,
221 },
222 };
223
224 static struct clk tegra_pll_p_out1 = {
225 .name = "pll_p_out1",
226 .ops = &tegra30_pll_div_ops,
227 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
228 .parent = &tegra_pll_p,
229 .reg = 0xa4,
230 .reg_shift = 0,
231 .max_rate = 432000000,
232 };
233
234 static struct clk tegra_pll_p_out2 = {
235 .name = "pll_p_out2",
236 .ops = &tegra30_pll_div_ops,
237 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
238 .parent = &tegra_pll_p,
239 .reg = 0xa4,
240 .reg_shift = 16,
241 .max_rate = 432000000,
242 };
243
244 static struct clk tegra_pll_p_out3 = {
245 .name = "pll_p_out3",
246 .ops = &tegra30_pll_div_ops,
247 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
248 .parent = &tegra_pll_p,
249 .reg = 0xa8,
250 .reg_shift = 0,
251 .max_rate = 432000000,
252 };
253
254 static struct clk tegra_pll_p_out4 = {
255 .name = "pll_p_out4",
256 .ops = &tegra30_pll_div_ops,
257 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
258 .parent = &tegra_pll_p,
259 .reg = 0xa8,
260 .reg_shift = 16,
261 .max_rate = 432000000,
262 };
263
264 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
265 { 9600000, 564480000, 294, 5, 1, 4},
266 { 9600000, 552960000, 288, 5, 1, 4},
267 { 9600000, 24000000, 5, 2, 1, 1},
268
269 { 28800000, 56448000, 49, 25, 1, 1},
270 { 28800000, 73728000, 64, 25, 1, 1},
271 { 28800000, 24000000, 5, 6, 1, 1},
272 { 0, 0, 0, 0, 0, 0 },
273 };
274
275 static struct clk tegra_pll_a = {
276 .name = "pll_a",
277 .flags = PLL_HAS_CPCON,
278 .ops = &tegra30_pll_ops,
279 .reg = 0xb0,
280 .parent = &tegra_pll_p_out1,
281 .max_rate = 700000000,
282 .u.pll = {
283 .input_min = 2000000,
284 .input_max = 31000000,
285 .cf_min = 1000000,
286 .cf_max = 6000000,
287 .vco_min = 20000000,
288 .vco_max = 1400000000,
289 .freq_table = tegra_pll_a_freq_table,
290 .lock_delay = 300,
291 },
292 };
293
294 static struct clk tegra_pll_a_out0 = {
295 .name = "pll_a_out0",
296 .ops = &tegra30_pll_div_ops,
297 .flags = DIV_U71,
298 .parent = &tegra_pll_a,
299 .reg = 0xb4,
300 .reg_shift = 0,
301 .max_rate = 100000000,
302 };
303
304 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
305 { 12000000, 216000000, 216, 12, 1, 4},
306 { 13000000, 216000000, 216, 13, 1, 4},
307 { 16800000, 216000000, 180, 14, 1, 4},
308 { 19200000, 216000000, 180, 16, 1, 4},
309 { 26000000, 216000000, 216, 26, 1, 4},
310
311 { 12000000, 594000000, 594, 12, 1, 8},
312 { 13000000, 594000000, 594, 13, 1, 8},
313 { 16800000, 594000000, 495, 14, 1, 8},
314 { 19200000, 594000000, 495, 16, 1, 8},
315 { 26000000, 594000000, 594, 26, 1, 8},
316
317 { 12000000, 1000000000, 1000, 12, 1, 12},
318 { 13000000, 1000000000, 1000, 13, 1, 12},
319 { 19200000, 1000000000, 625, 12, 1, 8},
320 { 26000000, 1000000000, 1000, 26, 1, 12},
321
322 { 0, 0, 0, 0, 0, 0 },
323 };
324
325 static struct clk tegra_pll_d = {
326 .name = "pll_d",
327 .flags = PLL_HAS_CPCON | PLLD,
328 .ops = &tegra_plld_ops,
329 .reg = 0xd0,
330 .parent = &tegra_pll_ref,
331 .max_rate = 1000000000,
332 .u.pll = {
333 .input_min = 2000000,
334 .input_max = 40000000,
335 .cf_min = 1000000,
336 .cf_max = 6000000,
337 .vco_min = 40000000,
338 .vco_max = 1000000000,
339 .freq_table = tegra_pll_d_freq_table,
340 .lock_delay = 1000,
341 },
342 };
343
344 static struct clk tegra_pll_d_out0 = {
345 .name = "pll_d_out0",
346 .ops = &tegra30_pll_div_ops,
347 .flags = DIV_2 | PLLD,
348 .parent = &tegra_pll_d,
349 .max_rate = 500000000,
350 };
351
352 static struct clk tegra_pll_d2 = {
353 .name = "pll_d2",
354 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
355 .ops = &tegra_plld_ops,
356 .reg = 0x4b8,
357 .parent = &tegra_pll_ref,
358 .max_rate = 1000000000,
359 .u.pll = {
360 .input_min = 2000000,
361 .input_max = 40000000,
362 .cf_min = 1000000,
363 .cf_max = 6000000,
364 .vco_min = 40000000,
365 .vco_max = 1000000000,
366 .freq_table = tegra_pll_d_freq_table,
367 .lock_delay = 1000,
368 },
369 };
370
371 static struct clk tegra_pll_d2_out0 = {
372 .name = "pll_d2_out0",
373 .ops = &tegra30_pll_div_ops,
374 .flags = DIV_2 | PLLD,
375 .parent = &tegra_pll_d2,
376 .max_rate = 500000000,
377 };
378
379 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
380 { 12000000, 480000000, 960, 12, 2, 12},
381 { 13000000, 480000000, 960, 13, 2, 12},
382 { 16800000, 480000000, 400, 7, 2, 5},
383 { 19200000, 480000000, 200, 4, 2, 3},
384 { 26000000, 480000000, 960, 26, 2, 12},
385 { 0, 0, 0, 0, 0, 0 },
386 };
387
388 static struct clk tegra_pll_u = {
389 .name = "pll_u",
390 .flags = PLL_HAS_CPCON | PLLU,
391 .ops = &tegra30_pll_ops,
392 .reg = 0xc0,
393 .parent = &tegra_pll_ref,
394 .max_rate = 480000000,
395 .u.pll = {
396 .input_min = 2000000,
397 .input_max = 40000000,
398 .cf_min = 1000000,
399 .cf_max = 6000000,
400 .vco_min = 480000000,
401 .vco_max = 960000000,
402 .freq_table = tegra_pll_u_freq_table,
403 .lock_delay = 1000,
404 },
405 };
406
407 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
408 /* 1.7 GHz */
409 { 12000000, 1700000000, 850, 6, 1, 8},
410 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
411 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
412 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
413 { 26000000, 1700000000, 850, 13, 1, 8},
414
415 /* 1.6 GHz */
416 { 12000000, 1600000000, 800, 6, 1, 8},
417 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
418 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
419 { 19200000, 1600000000, 500, 6, 1, 8},
420 { 26000000, 1600000000, 800, 13, 1, 8},
421
422 /* 1.5 GHz */
423 { 12000000, 1500000000, 750, 6, 1, 8},
424 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
425 { 16800000, 1500000000, 625, 7, 1, 8},
426 { 19200000, 1500000000, 625, 8, 1, 8},
427 { 26000000, 1500000000, 750, 13, 1, 8},
428
429 /* 1.4 GHz */
430 { 12000000, 1400000000, 700, 6, 1, 8},
431 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
432 { 16800000, 1400000000, 1000, 12, 1, 8},
433 { 19200000, 1400000000, 875, 12, 1, 8},
434 { 26000000, 1400000000, 700, 13, 1, 8},
435
436 /* 1.3 GHz */
437 { 12000000, 1300000000, 975, 9, 1, 8},
438 { 13000000, 1300000000, 1000, 10, 1, 8},
439 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
440 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
441 { 26000000, 1300000000, 650, 13, 1, 8},
442
443 /* 1.2 GHz */
444 { 12000000, 1200000000, 1000, 10, 1, 8},
445 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
446 { 16800000, 1200000000, 1000, 14, 1, 8},
447 { 19200000, 1200000000, 1000, 16, 1, 8},
448 { 26000000, 1200000000, 600, 13, 1, 8},
449
450 /* 1.1 GHz */
451 { 12000000, 1100000000, 825, 9, 1, 8},
452 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
453 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
454 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
455 { 26000000, 1100000000, 550, 13, 1, 8},
456
457 /* 1 GHz */
458 { 12000000, 1000000000, 1000, 12, 1, 8},
459 { 13000000, 1000000000, 1000, 13, 1, 8},
460 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
461 { 19200000, 1000000000, 625, 12, 1, 8},
462 { 26000000, 1000000000, 1000, 26, 1, 8},
463
464 { 0, 0, 0, 0, 0, 0 },
465 };
466
467 static struct clk tegra_pll_x = {
468 .name = "pll_x",
469 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
470 .ops = &tegra30_pll_ops,
471 .reg = 0xe0,
472 .parent = &tegra_pll_ref,
473 .max_rate = 1700000000,
474 .u.pll = {
475 .input_min = 2000000,
476 .input_max = 31000000,
477 .cf_min = 1000000,
478 .cf_max = 6000000,
479 .vco_min = 20000000,
480 .vco_max = 1700000000,
481 .freq_table = tegra_pll_x_freq_table,
482 .lock_delay = 300,
483 },
484 };
485
486 static struct clk tegra_pll_x_out0 = {
487 .name = "pll_x_out0",
488 .ops = &tegra30_pll_div_ops,
489 .flags = DIV_2 | PLLX,
490 .parent = &tegra_pll_x,
491 .max_rate = 850000000,
492 };
493
494
495 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
496 /* PLLE special case: use cpcon field to store cml divider value */
497 { 12000000, 100000000, 150, 1, 18, 11},
498 { 216000000, 100000000, 200, 18, 24, 13},
499 { 0, 0, 0, 0, 0, 0 },
500 };
501
502 static struct clk tegra_pll_e = {
503 .name = "pll_e",
504 .flags = PLL_ALT_MISC_REG,
505 .ops = &tegra30_plle_ops,
506 .reg = 0xe8,
507 .max_rate = 100000000,
508 .u.pll = {
509 .input_min = 12000000,
510 .input_max = 216000000,
511 .cf_min = 12000000,
512 .cf_max = 12000000,
513 .vco_min = 1200000000,
514 .vco_max = 2400000000U,
515 .freq_table = tegra_pll_e_freq_table,
516 .lock_delay = 300,
517 .fixed_rate = 100000000,
518 },
519 };
520
521 static struct clk tegra_cml0_clk = {
522 .name = "cml0",
523 .parent = &tegra_pll_e,
524 .ops = &tegra_cml_clk_ops,
525 .reg = 0x48c,
526 .max_rate = 100000000,
527 .u.periph = {
528 .clk_num = 0,
529 },
530 };
531
532 static struct clk tegra_cml1_clk = {
533 .name = "cml1",
534 .parent = &tegra_pll_e,
535 .ops = &tegra_cml_clk_ops,
536 .reg = 0x48c,
537 .max_rate = 100000000,
538 .u.periph = {
539 .clk_num = 1,
540 },
541 };
542
543 static struct clk tegra_pciex_clk = {
544 .name = "pciex",
545 .parent = &tegra_pll_e,
546 .ops = &tegra_pciex_clk_ops,
547 .max_rate = 100000000,
548 .u.periph = {
549 .clk_num = 74,
550 },
551 };
552
553 /* Audio sync clocks */
554 #define SYNC_SOURCE(_id) \
555 { \
556 .name = #_id "_sync", \
557 .rate = 24000000, \
558 .max_rate = 24000000, \
559 .ops = &tegra_sync_source_ops \
560 }
561 static struct clk tegra_sync_source_list[] = {
562 SYNC_SOURCE(spdif_in),
563 SYNC_SOURCE(i2s0),
564 SYNC_SOURCE(i2s1),
565 SYNC_SOURCE(i2s2),
566 SYNC_SOURCE(i2s3),
567 SYNC_SOURCE(i2s4),
568 SYNC_SOURCE(vimclk),
569 };
570
571 static struct clk_mux_sel mux_audio_sync_clk[] = {
572 { .input = &tegra_sync_source_list[0], .value = 0},
573 { .input = &tegra_sync_source_list[1], .value = 1},
574 { .input = &tegra_sync_source_list[2], .value = 2},
575 { .input = &tegra_sync_source_list[3], .value = 3},
576 { .input = &tegra_sync_source_list[4], .value = 4},
577 { .input = &tegra_sync_source_list[5], .value = 5},
578 { .input = &tegra_pll_a_out0, .value = 6},
579 { .input = &tegra_sync_source_list[6], .value = 7},
580 { 0, 0 }
581 };
582
583 #define AUDIO_SYNC_CLK(_id, _index) \
584 { \
585 .name = #_id, \
586 .inputs = mux_audio_sync_clk, \
587 .reg = 0x4A0 + (_index) * 4, \
588 .max_rate = 24000000, \
589 .ops = &tegra30_audio_sync_clk_ops \
590 }
591 static struct clk tegra_clk_audio_list[] = {
592 AUDIO_SYNC_CLK(audio0, 0),
593 AUDIO_SYNC_CLK(audio1, 1),
594 AUDIO_SYNC_CLK(audio2, 2),
595 AUDIO_SYNC_CLK(audio3, 3),
596 AUDIO_SYNC_CLK(audio4, 4),
597 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
598 };
599
600 #define AUDIO_SYNC_2X_CLK(_id, _index) \
601 { \
602 .name = #_id "_2x", \
603 .flags = PERIPH_NO_RESET, \
604 .max_rate = 48000000, \
605 .ops = &tegra30_clk_double_ops, \
606 .reg = 0x49C, \
607 .reg_shift = 24 + (_index), \
608 .parent = &tegra_clk_audio_list[(_index)], \
609 .u.periph = { \
610 .clk_num = 113 + (_index), \
611 }, \
612 }
613 static struct clk tegra_clk_audio_2x_list[] = {
614 AUDIO_SYNC_2X_CLK(audio0, 0),
615 AUDIO_SYNC_2X_CLK(audio1, 1),
616 AUDIO_SYNC_2X_CLK(audio2, 2),
617 AUDIO_SYNC_2X_CLK(audio3, 3),
618 AUDIO_SYNC_2X_CLK(audio4, 4),
619 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
620 };
621
622 #define MUX_I2S_SPDIF(_id, _index) \
623 static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
624 {.input = &tegra_pll_a_out0, .value = 0}, \
625 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
626 {.input = &tegra_pll_p, .value = 2}, \
627 {.input = &tegra_clk_m, .value = 3}, \
628 { 0, 0}, \
629 }
630 MUX_I2S_SPDIF(audio0, 0);
631 MUX_I2S_SPDIF(audio1, 1);
632 MUX_I2S_SPDIF(audio2, 2);
633 MUX_I2S_SPDIF(audio3, 3);
634 MUX_I2S_SPDIF(audio4, 4);
635 MUX_I2S_SPDIF(audio, 5); /* SPDIF */
636
637 /* External clock outputs (through PMC) */
638 #define MUX_EXTERN_OUT(_id) \
639 static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
640 {.input = &tegra_clk_m, .value = 0}, \
641 {.input = &tegra_clk_m_div2, .value = 1}, \
642 {.input = &tegra_clk_m_div4, .value = 2}, \
643 {.input = NULL, .value = 3}, /* placeholder */ \
644 { 0, 0}, \
645 }
646 MUX_EXTERN_OUT(1);
647 MUX_EXTERN_OUT(2);
648 MUX_EXTERN_OUT(3);
649
650 static struct clk_mux_sel *mux_extern_out_list[] = {
651 mux_clkm_clkm2_clkm4_extern1,
652 mux_clkm_clkm2_clkm4_extern2,
653 mux_clkm_clkm2_clkm4_extern3,
654 };
655
656 #define CLK_OUT_CLK(_id) \
657 { \
658 .name = "clk_out_" #_id, \
659 .lookup = { \
660 .dev_id = "clk_out_" #_id, \
661 .con_id = "extern" #_id, \
662 }, \
663 .ops = &tegra_clk_out_ops, \
664 .reg = 0x1a8, \
665 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
666 .flags = MUX_CLK_OUT, \
667 .max_rate = 216000000, \
668 .u.periph = { \
669 .clk_num = (_id - 1) * 8 + 2, \
670 }, \
671 }
672 static struct clk tegra_clk_out_list[] = {
673 CLK_OUT_CLK(1),
674 CLK_OUT_CLK(2),
675 CLK_OUT_CLK(3),
676 };
677
678 /* called after peripheral external clocks are initialized */
679 static void init_clk_out_mux(void)
680 {
681 int i;
682 struct clk *c;
683
684 /* output clock con_id is the name of peripheral
685 external clock connected to input 3 of the output mux */
686 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
687 c = tegra_get_clock_by_name(
688 tegra_clk_out_list[i].lookup.con_id);
689 if (!c)
690 pr_err("%s: could not find clk %s\n", __func__,
691 tegra_clk_out_list[i].lookup.con_id);
692 mux_extern_out_list[i][3].input = c;
693 }
694 }
695
696 /* Peripheral muxes */
697 static struct clk_mux_sel mux_sclk[] = {
698 { .input = &tegra_clk_m, .value = 0},
699 { .input = &tegra_pll_c_out1, .value = 1},
700 { .input = &tegra_pll_p_out4, .value = 2},
701 { .input = &tegra_pll_p_out3, .value = 3},
702 { .input = &tegra_pll_p_out2, .value = 4},
703 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
704 { .input = &tegra_clk_32k, .value = 6},
705 { .input = &tegra_pll_m_out1, .value = 7},
706 { 0, 0},
707 };
708
709 static struct clk tegra_clk_sclk = {
710 .name = "sclk",
711 .inputs = mux_sclk,
712 .reg = 0x28,
713 .ops = &tegra30_super_ops,
714 .max_rate = 334000000,
715 .min_rate = 40000000,
716 };
717
718 static struct clk tegra_clk_blink = {
719 .name = "blink",
720 .parent = &tegra_clk_32k,
721 .reg = 0x40,
722 .ops = &tegra30_blink_clk_ops,
723 .max_rate = 32768,
724 };
725
726 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
727 { .input = &tegra_pll_m, .value = 0},
728 { .input = &tegra_pll_c, .value = 1},
729 { .input = &tegra_pll_p, .value = 2},
730 { .input = &tegra_pll_a_out0, .value = 3},
731 { 0, 0},
732 };
733
734 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
735 { .input = &tegra_pll_p, .value = 0},
736 { .input = &tegra_pll_c, .value = 1},
737 { .input = &tegra_pll_m, .value = 2},
738 { .input = &tegra_clk_m, .value = 3},
739 { 0, 0},
740 };
741
742 static struct clk_mux_sel mux_pllp_clkm[] = {
743 { .input = &tegra_pll_p, .value = 0},
744 { .input = &tegra_clk_m, .value = 3},
745 { 0, 0},
746 };
747
748 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
749 {.input = &tegra_pll_p, .value = 0},
750 {.input = &tegra_pll_d_out0, .value = 1},
751 {.input = &tegra_pll_c, .value = 2},
752 {.input = &tegra_clk_m, .value = 3},
753 { 0, 0},
754 };
755
756 static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
757 {.input = &tegra_pll_p, .value = 0},
758 {.input = &tegra_pll_m, .value = 1},
759 {.input = &tegra_pll_d_out0, .value = 2},
760 {.input = &tegra_pll_a_out0, .value = 3},
761 {.input = &tegra_pll_c, .value = 4},
762 {.input = &tegra_pll_d2_out0, .value = 5},
763 {.input = &tegra_clk_m, .value = 6},
764 { 0, 0},
765 };
766
767 static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
768 { .input = &tegra_pll_a_out0, .value = 0},
769 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
770 { .input = &tegra_pll_p, .value = 2},
771 { .input = &tegra_clk_m, .value = 3},
772 { 0, 0},
773 };
774
775 static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
776 {.input = &tegra_pll_p, .value = 0},
777 {.input = &tegra_pll_c, .value = 1},
778 {.input = &tegra_clk_32k, .value = 2},
779 {.input = &tegra_clk_m, .value = 3},
780 { 0, 0},
781 };
782
783 static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
784 {.input = &tegra_pll_p, .value = 0},
785 {.input = &tegra_pll_c, .value = 1},
786 {.input = &tegra_clk_m, .value = 2},
787 {.input = &tegra_clk_32k, .value = 3},
788 { 0, 0},
789 };
790
791 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
792 {.input = &tegra_pll_p, .value = 0},
793 {.input = &tegra_pll_c, .value = 1},
794 {.input = &tegra_pll_m, .value = 2},
795 { 0, 0},
796 };
797
798 static struct clk_mux_sel mux_clk_m[] = {
799 { .input = &tegra_clk_m, .value = 0},
800 { 0, 0},
801 };
802
803 static struct clk_mux_sel mux_pllp_out3[] = {
804 { .input = &tegra_pll_p_out3, .value = 0},
805 { 0, 0},
806 };
807
808 static struct clk_mux_sel mux_plld_out0[] = {
809 { .input = &tegra_pll_d_out0, .value = 0},
810 { 0, 0},
811 };
812
813 static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
814 { .input = &tegra_pll_d_out0, .value = 0},
815 { .input = &tegra_pll_d2_out0, .value = 1},
816 { 0, 0},
817 };
818
819 static struct clk_mux_sel mux_clk_32k[] = {
820 { .input = &tegra_clk_32k, .value = 0},
821 { 0, 0},
822 };
823
824 static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
825 { .input = &tegra_pll_a_out0, .value = 0},
826 { .input = &tegra_clk_32k, .value = 1},
827 { .input = &tegra_pll_p, .value = 2},
828 { .input = &tegra_clk_m, .value = 3},
829 { .input = &tegra_pll_e, .value = 4},
830 { 0, 0},
831 };
832
833 static struct clk_mux_sel mux_cclk_g[] = {
834 { .input = &tegra_clk_m, .value = 0},
835 { .input = &tegra_pll_c, .value = 1},
836 { .input = &tegra_clk_32k, .value = 2},
837 { .input = &tegra_pll_m, .value = 3},
838 { .input = &tegra_pll_p, .value = 4},
839 { .input = &tegra_pll_p_out4, .value = 5},
840 { .input = &tegra_pll_p_out3, .value = 6},
841 { .input = &tegra_pll_x, .value = 8},
842 { 0, 0},
843 };
844
845 static struct clk tegra_clk_cclk_g = {
846 .name = "cclk_g",
847 .flags = DIV_U71 | DIV_U71_INT,
848 .inputs = mux_cclk_g,
849 .reg = 0x368,
850 .ops = &tegra30_super_ops,
851 .max_rate = 1700000000,
852 };
853
854 static struct clk tegra30_clk_twd = {
855 .parent = &tegra_clk_cclk_g,
856 .name = "twd",
857 .ops = &tegra30_twd_ops,
858 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
859 .mul = 1,
860 .div = 2,
861 };
862
863 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
864 { \
865 .name = _name, \
866 .lookup = { \
867 .dev_id = _dev, \
868 .con_id = _con, \
869 }, \
870 .ops = &tegra30_periph_clk_ops, \
871 .reg = _reg, \
872 .inputs = _inputs, \
873 .flags = _flags, \
874 .max_rate = _max, \
875 .u.periph = { \
876 .clk_num = _clk_num, \
877 }, \
878 }
879
880 #define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
881 _flags, _ops) \
882 { \
883 .name = _name, \
884 .lookup = { \
885 .dev_id = _dev, \
886 .con_id = _con, \
887 }, \
888 .ops = _ops, \
889 .reg = _reg, \
890 .inputs = _inputs, \
891 .flags = _flags, \
892 .max_rate = _max, \
893 .u.periph = { \
894 .clk_num = _clk_num, \
895 }, \
896 }
897
898 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
899 { \
900 .name = _name, \
901 .lookup = { \
902 .dev_id = _dev, \
903 .con_id = _con, \
904 }, \
905 .ops = &tegra_clk_shared_bus_ops, \
906 .parent = _parent, \
907 .u.shared_bus_user = { \
908 .client_id = _id, \
909 .client_div = _div, \
910 .mode = _mode, \
911 }, \
912 }
913 struct clk tegra_list_clks[] = {
914 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
915 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
916 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
917 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
918 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
919 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
920 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
921 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
922 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
923 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
924 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
925 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
926 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
927 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
928 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
929 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
930 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
931 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
932 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
933 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
934 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
935 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
936 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
937 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
938 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
939 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
940 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
941 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
942 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
943 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
944 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
945 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
946 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
947 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
948 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
949 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
950 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
951 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
952 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
953 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
954 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
955 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
956 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
957 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
958 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
959 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
960 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
961 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
962 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
963 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
964 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
965 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
966 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
967 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
968 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
969 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
970 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
971 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
972 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
973 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
974 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
975 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
976 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
977 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
978 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
979 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
980 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
981 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
982 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
983 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
984 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
985 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
986 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
987 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
988 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
989 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
990 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
991 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
992 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
993 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
994 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
995
996 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
997 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
998 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
999 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1000 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
1001 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
1002 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
1003 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
1004 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
1005 };
1006
1007 #define CLK_DUPLICATE(_name, _dev, _con) \
1008 { \
1009 .name = _name, \
1010 .lookup = { \
1011 .dev_id = _dev, \
1012 .con_id = _con, \
1013 }, \
1014 }
1015
1016 /* Some clocks may be used by different drivers depending on the board
1017 * configuration. List those here to register them twice in the clock lookup
1018 * table under two names.
1019 */
1020 struct clk_duplicate tegra_clk_duplicates[] = {
1021 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1022 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1023 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1024 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1025 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1026 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1027 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1028 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1029 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1030 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1031 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1032 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1033 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1034 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1035 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1036 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1037 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1038 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1039 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1040 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1041 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1042 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1043 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1044 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1045 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1046 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1047 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1048 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1049 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1050 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1051 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1052 CLK_DUPLICATE("twd", "smp_twd", NULL),
1053 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1054 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1055 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1056 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1057 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1058 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1059 CLK_DUPLICATE("dam0", NULL, "dam0"),
1060 CLK_DUPLICATE("dam1", NULL, "dam1"),
1061 CLK_DUPLICATE("dam2", NULL, "dam2"),
1062 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1063 };
1064
1065 struct clk *tegra_ptr_clks[] = {
1066 &tegra_clk_32k,
1067 &tegra_clk_m,
1068 &tegra_clk_m_div2,
1069 &tegra_clk_m_div4,
1070 &tegra_pll_ref,
1071 &tegra_pll_m,
1072 &tegra_pll_m_out1,
1073 &tegra_pll_c,
1074 &tegra_pll_c_out1,
1075 &tegra_pll_p,
1076 &tegra_pll_p_out1,
1077 &tegra_pll_p_out2,
1078 &tegra_pll_p_out3,
1079 &tegra_pll_p_out4,
1080 &tegra_pll_a,
1081 &tegra_pll_a_out0,
1082 &tegra_pll_d,
1083 &tegra_pll_d_out0,
1084 &tegra_pll_d2,
1085 &tegra_pll_d2_out0,
1086 &tegra_pll_u,
1087 &tegra_pll_x,
1088 &tegra_pll_x_out0,
1089 &tegra_pll_e,
1090 &tegra_clk_cclk_g,
1091 &tegra_cml0_clk,
1092 &tegra_cml1_clk,
1093 &tegra_pciex_clk,
1094 &tegra_clk_sclk,
1095 &tegra_clk_blink,
1096 &tegra30_clk_twd,
1097 };
1098
1099
1100 static void tegra30_init_one_clock(struct clk *c)
1101 {
1102 clk_init(c);
1103 INIT_LIST_HEAD(&c->shared_bus_list);
1104 if (!c->lookup.dev_id && !c->lookup.con_id)
1105 c->lookup.con_id = c->name;
1106 c->lookup.clk = c;
1107 clkdev_add(&c->lookup);
1108 }
1109
1110 void __init tegra30_init_clocks(void)
1111 {
1112 int i;
1113 struct clk *c;
1114
1115 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1116 tegra30_init_one_clock(tegra_ptr_clks[i]);
1117
1118 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1119 tegra30_init_one_clock(&tegra_list_clks[i]);
1120
1121 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1122 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1123 if (!c) {
1124 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1125 tegra_clk_duplicates[i].name);
1126 continue;
1127 }
1128
1129 tegra_clk_duplicates[i].lookup.clk = c;
1130 clkdev_add(&tegra_clk_duplicates[i].lookup);
1131 }
1132
1133 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1134 tegra30_init_one_clock(&tegra_sync_source_list[i]);
1135 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1136 tegra30_init_one_clock(&tegra_clk_audio_list[i]);
1137 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1138 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
1139
1140 init_clk_out_mux();
1141 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1142 tegra30_init_one_clock(&tegra_clk_out_list[i]);
1143
1144 }
Linux kernel - Deliverables
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