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Merge branch 'bcm2835/soc' into next/soc
[deliverable/linux.git] / arch / arm / mach-tegra / tegra30_clocks_data.c
1 /*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21 #include <linux/clk-private.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/clk.h>
30 #include <linux/cpufreq.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra30_clocks.h"
35 #include "tegra_cpu_car.h"
36
37 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
38 _parent_names, _parents, _parent) \
39 static struct clk tegra_##_name = { \
40 .hw = &tegra_##_name##_hw.hw, \
41 .name = #_name, \
42 .rate = _rate, \
43 .ops = _ops, \
44 .flags = _flags, \
45 .parent_names = _parent_names, \
46 .parents = _parents, \
47 .num_parents = ARRAY_SIZE(_parent_names), \
48 .parent = _parent, \
49 };
50
51 static struct clk tegra_clk_32k;
52 static struct clk_tegra tegra_clk_32k_hw = {
53 .hw = {
54 .clk = &tegra_clk_32k,
55 },
56 .fixed_rate = 32768,
57 };
58 static struct clk tegra_clk_32k = {
59 .name = "clk_32k",
60 .hw = &tegra_clk_32k_hw.hw,
61 .ops = &tegra30_clk_32k_ops,
62 .flags = CLK_IS_ROOT,
63 };
64
65 static struct clk tegra_clk_m;
66 static struct clk_tegra tegra_clk_m_hw = {
67 .hw = {
68 .clk = &tegra_clk_m,
69 },
70 .flags = ENABLE_ON_INIT,
71 .reg = 0x1fc,
72 .reg_shift = 28,
73 .max_rate = 48000000,
74 };
75 static struct clk tegra_clk_m = {
76 .name = "clk_m",
77 .hw = &tegra_clk_m_hw.hw,
78 .ops = &tegra30_clk_m_ops,
79 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
80 };
81
82 static const char *clk_m_div_parent_names[] = {
83 "clk_m",
84 };
85
86 static struct clk *clk_m_div_parents[] = {
87 &tegra_clk_m,
88 };
89
90 static struct clk tegra_clk_m_div2;
91 static struct clk_tegra tegra_clk_m_div2_hw = {
92 .hw = {
93 .clk = &tegra_clk_m_div2,
94 },
95 .mul = 1,
96 .div = 2,
97 .max_rate = 24000000,
98 };
99 DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
100 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
101
102 static struct clk tegra_clk_m_div4;
103 static struct clk_tegra tegra_clk_m_div4_hw = {
104 .hw = {
105 .clk = &tegra_clk_m_div4,
106 },
107 .mul = 1,
108 .div = 4,
109 .max_rate = 12000000,
110 };
111 DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
112 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
113
114 static struct clk tegra_pll_ref;
115 static struct clk_tegra tegra_pll_ref_hw = {
116 .hw = {
117 .clk = &tegra_pll_ref,
118 },
119 .flags = ENABLE_ON_INIT,
120 .max_rate = 26000000,
121 };
122 DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
123 clk_m_div_parents, &tegra_clk_m);
124
125 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
126 _input_max, _cf_min, _cf_max, _vco_min, \
127 _vco_max, _freq_table, _lock_delay, _ops, \
128 _fixed_rate, _clk_cfg_ex, _parent) \
129 static struct clk tegra_##_name; \
130 static const char *_name##_parent_names[] = { \
131 #_parent, \
132 }; \
133 static struct clk *_name##_parents[] = { \
134 &tegra_##_parent, \
135 }; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .u.pll = { \
144 .input_min = _input_min, \
145 .input_max = _input_max, \
146 .cf_min = _cf_min, \
147 .cf_max = _cf_max, \
148 .vco_min = _vco_min, \
149 .vco_max = _vco_max, \
150 .freq_table = _freq_table, \
151 .lock_delay = _lock_delay, \
152 .fixed_rate = _fixed_rate, \
153 }, \
154 .clk_cfg_ex = _clk_cfg_ex, \
155 }; \
156 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
157 _name##_parent_names, _name##_parents, \
158 &tegra_##_parent);
159
160 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
161 _max_rate, _ops, _parent, _clk_flags) \
162 static const char *_name##_parent_names[] = { \
163 #_parent, \
164 }; \
165 static struct clk *_name##_parents[] = { \
166 &tegra_##_parent, \
167 }; \
168 static struct clk tegra_##_name; \
169 static struct clk_tegra tegra_##_name##_hw = { \
170 .hw = { \
171 .clk = &tegra_##_name, \
172 }, \
173 .flags = _flags, \
174 .reg = _reg, \
175 .max_rate = _max_rate, \
176 .reg_shift = _reg_shift, \
177 }; \
178 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
179 _clk_flags, _name##_parent_names, \
180 _name##_parents, &tegra_##_parent);
181
182 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
183 { 12000000, 1040000000, 520, 6, 1, 8},
184 { 13000000, 1040000000, 480, 6, 1, 8},
185 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
186 { 19200000, 1040000000, 325, 6, 1, 6},
187 { 26000000, 1040000000, 520, 13, 1, 8},
188
189 { 12000000, 832000000, 416, 6, 1, 8},
190 { 13000000, 832000000, 832, 13, 1, 8},
191 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
192 { 19200000, 832000000, 260, 6, 1, 8},
193 { 26000000, 832000000, 416, 13, 1, 8},
194
195 { 12000000, 624000000, 624, 12, 1, 8},
196 { 13000000, 624000000, 624, 13, 1, 8},
197 { 16800000, 600000000, 520, 14, 1, 8},
198 { 19200000, 624000000, 520, 16, 1, 8},
199 { 26000000, 624000000, 624, 26, 1, 8},
200
201 { 12000000, 600000000, 600, 12, 1, 8},
202 { 13000000, 600000000, 600, 13, 1, 8},
203 { 16800000, 600000000, 500, 14, 1, 8},
204 { 19200000, 600000000, 375, 12, 1, 6},
205 { 26000000, 600000000, 600, 26, 1, 8},
206
207 { 12000000, 520000000, 520, 12, 1, 8},
208 { 13000000, 520000000, 520, 13, 1, 8},
209 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
210 { 19200000, 520000000, 325, 12, 1, 6},
211 { 26000000, 520000000, 520, 26, 1, 8},
212
213 { 12000000, 416000000, 416, 12, 1, 8},
214 { 13000000, 416000000, 416, 13, 1, 8},
215 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
216 { 19200000, 416000000, 260, 12, 1, 6},
217 { 26000000, 416000000, 416, 26, 1, 8},
218 { 0, 0, 0, 0, 0, 0 },
219 };
220
221 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
222 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
223 tegra30_pll_ops, 0, NULL, pll_ref);
224
225 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
226 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
227
228 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
229 { 12000000, 666000000, 666, 12, 1, 8},
230 { 13000000, 666000000, 666, 13, 1, 8},
231 { 16800000, 666000000, 555, 14, 1, 8},
232 { 19200000, 666000000, 555, 16, 1, 8},
233 { 26000000, 666000000, 666, 26, 1, 8},
234 { 12000000, 600000000, 600, 12, 1, 8},
235 { 13000000, 600000000, 600, 13, 1, 8},
236 { 16800000, 600000000, 500, 14, 1, 8},
237 { 19200000, 600000000, 375, 12, 1, 6},
238 { 26000000, 600000000, 600, 26, 1, 8},
239 { 0, 0, 0, 0, 0, 0 },
240 };
241
242 DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
243 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
244 300, tegra30_pll_ops, 0, NULL, pll_ref);
245
246 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
247 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
248
249 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
250 { 12000000, 216000000, 432, 12, 2, 8},
251 { 13000000, 216000000, 432, 13, 2, 8},
252 { 16800000, 216000000, 360, 14, 2, 8},
253 { 19200000, 216000000, 360, 16, 2, 8},
254 { 26000000, 216000000, 432, 26, 2, 8},
255 { 0, 0, 0, 0, 0, 0 },
256 };
257
258 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
259 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
260 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
261 pll_ref);
262
263 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
264 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
265 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
266 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
267 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
268 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
269 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
270 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
271
272 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
273 { 9600000, 564480000, 294, 5, 1, 4},
274 { 9600000, 552960000, 288, 5, 1, 4},
275 { 9600000, 24000000, 5, 2, 1, 1},
276
277 { 28800000, 56448000, 49, 25, 1, 1},
278 { 28800000, 73728000, 64, 25, 1, 1},
279 { 28800000, 24000000, 5, 6, 1, 1},
280 { 0, 0, 0, 0, 0, 0 },
281 };
282
283 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
284 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
285 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
286
287 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
288 pll_a, CLK_IGNORE_UNUSED);
289
290 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
291 { 12000000, 216000000, 216, 12, 1, 4},
292 { 13000000, 216000000, 216, 13, 1, 4},
293 { 16800000, 216000000, 180, 14, 1, 4},
294 { 19200000, 216000000, 180, 16, 1, 4},
295 { 26000000, 216000000, 216, 26, 1, 4},
296
297 { 12000000, 594000000, 594, 12, 1, 8},
298 { 13000000, 594000000, 594, 13, 1, 8},
299 { 16800000, 594000000, 495, 14, 1, 8},
300 { 19200000, 594000000, 495, 16, 1, 8},
301 { 26000000, 594000000, 594, 26, 1, 8},
302
303 { 12000000, 1000000000, 1000, 12, 1, 12},
304 { 13000000, 1000000000, 1000, 13, 1, 12},
305 { 19200000, 1000000000, 625, 12, 1, 8},
306 { 26000000, 1000000000, 1000, 26, 1, 12},
307
308 { 0, 0, 0, 0, 0, 0 },
309 };
310
311 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
312 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
313 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
314
315 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
316 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
317
318 DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
319 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
320 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
321 pll_ref);
322
323 DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
324 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
325
326 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
327 { 12000000, 480000000, 960, 12, 2, 12},
328 { 13000000, 480000000, 960, 13, 2, 12},
329 { 16800000, 480000000, 400, 7, 2, 5},
330 { 19200000, 480000000, 200, 4, 2, 3},
331 { 26000000, 480000000, 960, 26, 2, 12},
332 { 0, 0, 0, 0, 0, 0 },
333 };
334
335 DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
336 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
337 1000, tegra30_pll_ops, 0, NULL, pll_ref);
338
339 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
340 /* 1.7 GHz */
341 { 12000000, 1700000000, 850, 6, 1, 8},
342 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
344 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
345 { 26000000, 1700000000, 850, 13, 1, 8},
346
347 /* 1.6 GHz */
348 { 12000000, 1600000000, 800, 6, 1, 8},
349 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
350 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
351 { 19200000, 1600000000, 500, 6, 1, 8},
352 { 26000000, 1600000000, 800, 13, 1, 8},
353
354 /* 1.5 GHz */
355 { 12000000, 1500000000, 750, 6, 1, 8},
356 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
357 { 16800000, 1500000000, 625, 7, 1, 8},
358 { 19200000, 1500000000, 625, 8, 1, 8},
359 { 26000000, 1500000000, 750, 13, 1, 8},
360
361 /* 1.4 GHz */
362 { 12000000, 1400000000, 700, 6, 1, 8},
363 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
364 { 16800000, 1400000000, 1000, 12, 1, 8},
365 { 19200000, 1400000000, 875, 12, 1, 8},
366 { 26000000, 1400000000, 700, 13, 1, 8},
367
368 /* 1.3 GHz */
369 { 12000000, 1300000000, 975, 9, 1, 8},
370 { 13000000, 1300000000, 1000, 10, 1, 8},
371 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
373 { 26000000, 1300000000, 650, 13, 1, 8},
374
375 /* 1.2 GHz */
376 { 12000000, 1200000000, 1000, 10, 1, 8},
377 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
378 { 16800000, 1200000000, 1000, 14, 1, 8},
379 { 19200000, 1200000000, 1000, 16, 1, 8},
380 { 26000000, 1200000000, 600, 13, 1, 8},
381
382 /* 1.1 GHz */
383 { 12000000, 1100000000, 825, 9, 1, 8},
384 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
385 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
386 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
387 { 26000000, 1100000000, 550, 13, 1, 8},
388
389 /* 1 GHz */
390 { 12000000, 1000000000, 1000, 12, 1, 8},
391 { 13000000, 1000000000, 1000, 13, 1, 8},
392 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
393 { 19200000, 1000000000, 625, 12, 1, 8},
394 { 26000000, 1000000000, 1000, 26, 1, 8},
395
396 { 0, 0, 0, 0, 0, 0 },
397 };
398
399 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
400 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
401 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
402
403 DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
404 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
405
406 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
407 /* PLLE special case: use cpcon field to store cml divider value */
408 { 12000000, 100000000, 150, 1, 18, 11},
409 { 216000000, 100000000, 200, 18, 24, 13},
410 { 0, 0, 0, 0, 0, 0 },
411 };
412
413 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
414 12000000, 12000000, 1200000000, 2400000000U,
415 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
416 pll_ref);
417
418 static const char *mux_plle[] = {
419 "pll_e",
420 };
421
422 static struct clk *mux_plle_p[] = {
423 &tegra_pll_e,
424 };
425
426 static struct clk tegra_cml0;
427 static struct clk_tegra tegra_cml0_hw = {
428 .hw = {
429 .clk = &tegra_cml0,
430 },
431 .reg = 0x48c,
432 .fixed_rate = 100000000,
433 .u.periph = {
434 .clk_num = 0,
435 },
436 };
437 DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
438 mux_plle_p, &tegra_pll_e);
439
440 static struct clk tegra_cml1;
441 static struct clk_tegra tegra_cml1_hw = {
442 .hw = {
443 .clk = &tegra_cml1,
444 },
445 .reg = 0x48c,
446 .fixed_rate = 100000000,
447 .u.periph = {
448 .clk_num = 1,
449 },
450 };
451 DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
452 mux_plle_p, &tegra_pll_e);
453
454 static struct clk tegra_pciex;
455 static struct clk_tegra tegra_pciex_hw = {
456 .hw = {
457 .clk = &tegra_pciex,
458 },
459 .reg = 0x48c,
460 .fixed_rate = 100000000,
461 .reset = tegra30_periph_clk_reset,
462 .u.periph = {
463 .clk_num = 74,
464 },
465 };
466 DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
467 mux_plle_p, &tegra_pll_e);
468
469 #define SYNC_SOURCE(_name) \
470 static struct clk tegra_##_name##_sync; \
471 static struct clk_tegra tegra_##_name##_sync_hw = { \
472 .hw = { \
473 .clk = &tegra_##_name##_sync, \
474 }, \
475 .max_rate = 24000000, \
476 .fixed_rate = 24000000, \
477 }; \
478 static struct clk tegra_##_name##_sync = { \
479 .name = #_name "_sync", \
480 .hw = &tegra_##_name##_sync_hw.hw, \
481 .ops = &tegra_sync_source_ops, \
482 .flags = CLK_IS_ROOT, \
483 };
484
485 SYNC_SOURCE(spdif_in);
486 SYNC_SOURCE(i2s0);
487 SYNC_SOURCE(i2s1);
488 SYNC_SOURCE(i2s2);
489 SYNC_SOURCE(i2s3);
490 SYNC_SOURCE(i2s4);
491 SYNC_SOURCE(vimclk);
492
493 static struct clk *tegra_sync_source_list[] = {
494 &tegra_spdif_in_sync,
495 &tegra_i2s0_sync,
496 &tegra_i2s1_sync,
497 &tegra_i2s2_sync,
498 &tegra_i2s3_sync,
499 &tegra_i2s4_sync,
500 &tegra_vimclk_sync,
501 };
502
503 static const char *mux_audio_sync_clk[] = {
504 "spdif_in_sync",
505 "i2s0_sync",
506 "i2s1_sync",
507 "i2s2_sync",
508 "i2s3_sync",
509 "i2s4_sync",
510 "vimclk_sync",
511 };
512
513 #define AUDIO_SYNC_CLK(_name, _index) \
514 static struct clk tegra_##_name; \
515 static struct clk_tegra tegra_##_name##_hw = { \
516 .hw = { \
517 .clk = &tegra_##_name, \
518 }, \
519 .max_rate = 24000000, \
520 .reg = 0x4A0 + (_index) * 4, \
521 }; \
522 static struct clk tegra_##_name = { \
523 .name = #_name, \
524 .ops = &tegra30_audio_sync_clk_ops, \
525 .hw = &tegra_##_name##_hw.hw, \
526 .parent_names = mux_audio_sync_clk, \
527 .parents = tegra_sync_source_list, \
528 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
529 };
530
531 AUDIO_SYNC_CLK(audio0, 0);
532 AUDIO_SYNC_CLK(audio1, 1);
533 AUDIO_SYNC_CLK(audio2, 2);
534 AUDIO_SYNC_CLK(audio3, 3);
535 AUDIO_SYNC_CLK(audio4, 4);
536 AUDIO_SYNC_CLK(audio5, 5);
537
538 static struct clk *tegra_clk_audio_list[] = {
539 &tegra_audio0,
540 &tegra_audio1,
541 &tegra_audio2,
542 &tegra_audio3,
543 &tegra_audio4,
544 &tegra_audio5, /* SPDIF */
545 };
546
547 #define AUDIO_SYNC_2X_CLK(_name, _index) \
548 static const char *_name##_parent_names[] = { \
549 "tegra_" #_name, \
550 }; \
551 static struct clk *_name##_parents[] = { \
552 &tegra_##_name, \
553 }; \
554 static struct clk tegra_##_name##_2x; \
555 static struct clk_tegra tegra_##_name##_2x_hw = { \
556 .hw = { \
557 .clk = &tegra_##_name##_2x, \
558 }, \
559 .flags = PERIPH_NO_RESET, \
560 .max_rate = 48000000, \
561 .reg = 0x49C, \
562 .reg_shift = 24 + (_index), \
563 .u.periph = { \
564 .clk_num = 113 + (_index), \
565 }, \
566 }; \
567 static struct clk tegra_##_name##_2x = { \
568 .name = #_name "_2x", \
569 .ops = &tegra30_clk_double_ops, \
570 .hw = &tegra_##_name##_2x_hw.hw, \
571 .parent_names = _name##_parent_names, \
572 .parents = _name##_parents, \
573 .parent = &tegra_##_name, \
574 .num_parents = 1, \
575 };
576
577 AUDIO_SYNC_2X_CLK(audio0, 0);
578 AUDIO_SYNC_2X_CLK(audio1, 1);
579 AUDIO_SYNC_2X_CLK(audio2, 2);
580 AUDIO_SYNC_2X_CLK(audio3, 3);
581 AUDIO_SYNC_2X_CLK(audio4, 4);
582 AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
583
584 static struct clk *tegra_clk_audio_2x_list[] = {
585 &tegra_audio0_2x,
586 &tegra_audio1_2x,
587 &tegra_audio2_2x,
588 &tegra_audio3_2x,
589 &tegra_audio4_2x,
590 &tegra_audio5_2x, /* SPDIF */
591 };
592
593 #define MUX_I2S_SPDIF(_id) \
594 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
595 "pll_a_out0", \
596 #_id "_2x", \
597 "pll_p", \
598 "clk_m", \
599 }; \
600 static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
601 &tegra_pll_a_out0, \
602 &tegra_##_id##_2x, \
603 &tegra_pll_p, \
604 &tegra_clk_m, \
605 };
606
607 MUX_I2S_SPDIF(audio0);
608 MUX_I2S_SPDIF(audio1);
609 MUX_I2S_SPDIF(audio2);
610 MUX_I2S_SPDIF(audio3);
611 MUX_I2S_SPDIF(audio4);
612 MUX_I2S_SPDIF(audio5); /* SPDIF */
613
614 static struct clk tegra_extern1;
615 static struct clk tegra_extern2;
616 static struct clk tegra_extern3;
617
618 /* External clock outputs (through PMC) */
619 #define MUX_EXTERN_OUT(_id) \
620 static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
621 "clk_m", \
622 "clk_m_div2", \
623 "clk_m_div4", \
624 "extern" #_id, \
625 }; \
626 static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
627 &tegra_clk_m, \
628 &tegra_clk_m_div2, \
629 &tegra_clk_m_div4, \
630 &tegra_extern##_id, \
631 };
632
633 MUX_EXTERN_OUT(1);
634 MUX_EXTERN_OUT(2);
635 MUX_EXTERN_OUT(3);
636
637 #define CLK_OUT_CLK(_name, _index) \
638 static struct clk tegra_##_name; \
639 static struct clk_tegra tegra_##_name##_hw = { \
640 .hw = { \
641 .clk = &tegra_##_name, \
642 }, \
643 .lookup = { \
644 .dev_id = #_name, \
645 .con_id = "extern" #_index, \
646 }, \
647 .flags = MUX_CLK_OUT, \
648 .fixed_rate = 216000000, \
649 .reg = 0x1a8, \
650 .u.periph = { \
651 .clk_num = (_index - 1) * 8 + 2, \
652 }, \
653 }; \
654 static struct clk tegra_##_name = { \
655 .name = #_name, \
656 .ops = &tegra_clk_out_ops, \
657 .hw = &tegra_##_name##_hw.hw, \
658 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
659 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
660 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
661 };
662
663 CLK_OUT_CLK(clk_out_1, 1);
664 CLK_OUT_CLK(clk_out_2, 2);
665 CLK_OUT_CLK(clk_out_3, 3);
666
667 static struct clk *tegra_clk_out_list[] = {
668 &tegra_clk_out_1,
669 &tegra_clk_out_2,
670 &tegra_clk_out_3,
671 };
672
673 static const char *mux_sclk[] = {
674 "clk_m",
675 "pll_c_out1",
676 "pll_p_out4",
677 "pll_p_out3",
678 "pll_p_out2",
679 "dummy",
680 "clk_32k",
681 "pll_m_out1",
682 };
683
684 static struct clk *mux_sclk_p[] = {
685 &tegra_clk_m,
686 &tegra_pll_c_out1,
687 &tegra_pll_p_out4,
688 &tegra_pll_p_out3,
689 &tegra_pll_p_out2,
690 NULL,
691 &tegra_clk_32k,
692 &tegra_pll_m_out1,
693 };
694
695 static struct clk tegra_clk_sclk;
696 static struct clk_tegra tegra_clk_sclk_hw = {
697 .hw = {
698 .clk = &tegra_clk_sclk,
699 },
700 .reg = 0x28,
701 .max_rate = 334000000,
702 .min_rate = 40000000,
703 };
704
705 static struct clk tegra_clk_sclk = {
706 .name = "sclk",
707 .ops = &tegra30_super_ops,
708 .hw = &tegra_clk_sclk_hw.hw,
709 .parent_names = mux_sclk,
710 .parents = mux_sclk_p,
711 .num_parents = ARRAY_SIZE(mux_sclk),
712 };
713
714 static const char *mux_blink[] = {
715 "clk_32k",
716 };
717
718 static struct clk *mux_blink_p[] = {
719 &tegra_clk_32k,
720 };
721
722 static struct clk tegra_clk_blink;
723 static struct clk_tegra tegra_clk_blink_hw = {
724 .hw = {
725 .clk = &tegra_clk_blink,
726 },
727 .reg = 0x40,
728 .max_rate = 32768,
729 };
730 static struct clk tegra_clk_blink = {
731 .name = "blink",
732 .ops = &tegra30_blink_clk_ops,
733 .hw = &tegra_clk_blink_hw.hw,
734 .parent = &tegra_clk_32k,
735 .parent_names = mux_blink,
736 .parents = mux_blink_p,
737 .num_parents = ARRAY_SIZE(mux_blink),
738 };
739
740 static const char *mux_pllm_pllc_pllp_plla[] = {
741 "pll_m",
742 "pll_c",
743 "pll_p",
744 "pll_a_out0",
745 };
746
747 static const char *mux_pllp_pllc_pllm_clkm[] = {
748 "pll_p",
749 "pll_c",
750 "pll_m",
751 "clk_m",
752 };
753
754 static const char *mux_pllp_clkm[] = {
755 "pll_p",
756 "dummy",
757 "dummy",
758 "clk_m",
759 };
760
761 static const char *mux_pllp_plld_pllc_clkm[] = {
762 "pll_p",
763 "pll_d_out0",
764 "pll_c",
765 "clk_m",
766 };
767
768 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
769 "pll_p",
770 "pll_m",
771 "pll_d_out0",
772 "pll_a_out0",
773 "pll_c",
774 "pll_d2_out0",
775 "clk_m",
776 };
777
778 static const char *mux_plla_pllc_pllp_clkm[] = {
779 "pll_a_out0",
780 "dummy",
781 "pll_p",
782 "clk_m"
783 };
784
785 static const char *mux_pllp_pllc_clk32_clkm[] = {
786 "pll_p",
787 "pll_c",
788 "clk_32k",
789 "clk_m",
790 };
791
792 static const char *mux_pllp_pllc_clkm_clk32[] = {
793 "pll_p",
794 "pll_c",
795 "clk_m",
796 "clk_32k",
797 };
798
799 static const char *mux_pllp_pllc_pllm[] = {
800 "pll_p",
801 "pll_c",
802 "pll_m",
803 };
804
805 static const char *mux_clk_m[] = {
806 "clk_m",
807 };
808
809 static const char *mux_pllp_out3[] = {
810 "pll_p_out3",
811 };
812
813 static const char *mux_plld_out0[] = {
814 "pll_d_out0",
815 };
816
817 static const char *mux_plld_out0_plld2_out0[] = {
818 "pll_d_out0",
819 "pll_d2_out0",
820 };
821
822 static const char *mux_clk_32k[] = {
823 "clk_32k",
824 };
825
826 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
827 "pll_a_out0",
828 "clk_32k",
829 "pll_p",
830 "clk_m",
831 "pll_e",
832 };
833
834 static const char *mux_cclk_g[] = {
835 "clk_m",
836 "pll_c",
837 "clk_32k",
838 "pll_m",
839 "pll_p",
840 "pll_p_out4",
841 "pll_p_out3",
842 "dummy",
843 "pll_x",
844 };
845
846 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
847 &tegra_pll_m,
848 &tegra_pll_c,
849 &tegra_pll_p,
850 &tegra_pll_a_out0,
851 };
852
853 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
854 &tegra_pll_p,
855 &tegra_pll_c,
856 &tegra_pll_m,
857 &tegra_clk_m,
858 };
859
860 static struct clk *mux_pllp_clkm_p[] = {
861 &tegra_pll_p,
862 NULL,
863 NULL,
864 &tegra_clk_m,
865 };
866
867 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
868 &tegra_pll_p,
869 &tegra_pll_d_out0,
870 &tegra_pll_c,
871 &tegra_clk_m,
872 };
873
874 static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
875 &tegra_pll_p,
876 &tegra_pll_m,
877 &tegra_pll_d_out0,
878 &tegra_pll_a_out0,
879 &tegra_pll_c,
880 &tegra_pll_d2_out0,
881 &tegra_clk_m,
882 };
883
884 static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
885 &tegra_pll_a_out0,
886 NULL,
887 &tegra_pll_p,
888 &tegra_clk_m,
889 };
890
891 static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
892 &tegra_pll_p,
893 &tegra_pll_c,
894 &tegra_clk_32k,
895 &tegra_clk_m,
896 };
897
898 static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
899 &tegra_pll_p,
900 &tegra_pll_c,
901 &tegra_clk_m,
902 &tegra_clk_32k,
903 };
904
905 static struct clk *mux_pllp_pllc_pllm_p[] = {
906 &tegra_pll_p,
907 &tegra_pll_c,
908 &tegra_pll_m,
909 };
910
911 static struct clk *mux_clk_m_p[] = {
912 &tegra_clk_m,
913 };
914
915 static struct clk *mux_pllp_out3_p[] = {
916 &tegra_pll_p_out3,
917 };
918
919 static struct clk *mux_plld_out0_p[] = {
920 &tegra_pll_d_out0,
921 };
922
923 static struct clk *mux_plld_out0_plld2_out0_p[] = {
924 &tegra_pll_d_out0,
925 &tegra_pll_d2_out0,
926 };
927
928 static struct clk *mux_clk_32k_p[] = {
929 &tegra_clk_32k,
930 };
931
932 static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
933 &tegra_pll_a_out0,
934 &tegra_clk_32k,
935 &tegra_pll_p,
936 &tegra_clk_m,
937 &tegra_pll_e,
938 };
939
940 static struct clk *mux_cclk_g_p[] = {
941 &tegra_clk_m,
942 &tegra_pll_c,
943 &tegra_clk_32k,
944 &tegra_pll_m,
945 &tegra_pll_p,
946 &tegra_pll_p_out4,
947 &tegra_pll_p_out3,
948 NULL,
949 &tegra_pll_x,
950 };
951
952 static struct clk tegra_clk_cclk_g;
953 static struct clk_tegra tegra_clk_cclk_g_hw = {
954 .hw = {
955 .clk = &tegra_clk_cclk_g,
956 },
957 .flags = DIV_U71 | DIV_U71_INT,
958 .reg = 0x368,
959 .max_rate = 1700000000,
960 };
961 static struct clk tegra_clk_cclk_g = {
962 .name = "cclk_g",
963 .ops = &tegra30_super_ops,
964 .hw = &tegra_clk_cclk_g_hw.hw,
965 .parent_names = mux_cclk_g,
966 .parents = mux_cclk_g_p,
967 .num_parents = ARRAY_SIZE(mux_cclk_g),
968 };
969
970 static const char *mux_twd[] = {
971 "cclk_g",
972 };
973
974 static struct clk *mux_twd_p[] = {
975 &tegra_clk_cclk_g,
976 };
977
978 static struct clk tegra30_clk_twd;
979 static struct clk_tegra tegra30_clk_twd_hw = {
980 .hw = {
981 .clk = &tegra30_clk_twd,
982 },
983 .max_rate = 1400000000,
984 .mul = 1,
985 .div = 2,
986 };
987
988 static struct clk tegra30_clk_twd = {
989 .name = "twd",
990 .ops = &tegra30_twd_ops,
991 .hw = &tegra30_clk_twd_hw.hw,
992 .parent = &tegra_clk_cclk_g,
993 .parent_names = mux_twd,
994 .parents = mux_twd_p,
995 .num_parents = ARRAY_SIZE(mux_twd),
996 };
997
998 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
999 _max, _inputs, _flags) \
1000 static struct clk tegra_##_name; \
1001 static struct clk_tegra tegra_##_name##_hw = { \
1002 .hw = { \
1003 .clk = &tegra_##_name, \
1004 }, \
1005 .lookup = { \
1006 .dev_id = _dev, \
1007 .con_id = _con, \
1008 }, \
1009 .reg = _reg, \
1010 .flags = _flags, \
1011 .max_rate = _max, \
1012 .u.periph = { \
1013 .clk_num = _clk_num, \
1014 }, \
1015 .reset = &tegra30_periph_clk_reset, \
1016 }; \
1017 static struct clk tegra_##_name = { \
1018 .name = #_name, \
1019 .ops = &tegra30_periph_clk_ops, \
1020 .hw = &tegra_##_name##_hw.hw, \
1021 .parent_names = _inputs, \
1022 .parents = _inputs##_p, \
1023 .num_parents = ARRAY_SIZE(_inputs), \
1024 };
1025
1026 PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1027 PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1028 PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1029 PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1030 PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1031 PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1032 PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1033 PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1034 PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1035 PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1036 PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1037 PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1038 PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1039 PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1040 PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1041 PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1042 PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1043 PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1044 PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1045 PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1046 PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1047 PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1048 PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1049 PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1050 PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1051 PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1052 PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1053 PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1054 PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1055 PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1056 PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1057 PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1058 PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1059 PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1060 PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1061 PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1062 PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1063 PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1064 PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1065 PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1066 PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1067 PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1068 PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1069 PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1070 PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1071 PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1072 PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1073 PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1074 PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075 PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076 PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077 PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078 PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1079 PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080 PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081 PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1082 PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1083 PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1084 PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1085 PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1086 PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1087 PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1088 PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1089 PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1090 PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1091 PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1092 PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1093 PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1094 PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1095 PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1096 PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1097 PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1098 PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1099 PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1100 PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1101 PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1102 PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1103 PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1104 PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1105 PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1106 PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1107 PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1108 PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1109 PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1110 PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1111 PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1112 PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1113 PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1114 PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1115
1116 static struct clk tegra_dsib;
1117 static struct clk_tegra tegra_dsib_hw = {
1118 .hw = {
1119 .clk = &tegra_dsib,
1120 },
1121 .lookup = {
1122 .dev_id = "tegradc.1",
1123 .con_id = "dsib",
1124 },
1125 .reg = 0xd0,
1126 .flags = MUX | PLLD,
1127 .max_rate = 500000000,
1128 .u.periph = {
1129 .clk_num = 82,
1130 },
1131 .reset = &tegra30_periph_clk_reset,
1132 };
1133 static struct clk tegra_dsib = {
1134 .name = "dsib",
1135 .ops = &tegra30_dsib_clk_ops,
1136 .hw = &tegra_dsib_hw.hw,
1137 .parent_names = mux_plld_out0_plld2_out0,
1138 .parents = mux_plld_out0_plld2_out0_p,
1139 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1140 };
1141
1142 struct clk *tegra_list_clks[] = {
1143 &tegra_apbdma,
1144 &tegra_rtc,
1145 &tegra_kbc,
1146 &tegra_kfuse,
1147 &tegra_fuse,
1148 &tegra_fuse_burn,
1149 &tegra_apbif,
1150 &tegra_i2s0,
1151 &tegra_i2s1,
1152 &tegra_i2s2,
1153 &tegra_i2s3,
1154 &tegra_i2s4,
1155 &tegra_spdif_out,
1156 &tegra_spdif_in,
1157 &tegra_pwm,
1158 &tegra_d_audio,
1159 &tegra_dam0,
1160 &tegra_dam1,
1161 &tegra_dam2,
1162 &tegra_hda,
1163 &tegra_hda2codec_2x,
1164 &tegra_hda2hdmi,
1165 &tegra_sbc1,
1166 &tegra_sbc2,
1167 &tegra_sbc3,
1168 &tegra_sbc4,
1169 &tegra_sbc5,
1170 &tegra_sbc6,
1171 &tegra_sata_oob,
1172 &tegra_sata,
1173 &tegra_sata_cold,
1174 &tegra_ndflash,
1175 &tegra_ndspeed,
1176 &tegra_vfir,
1177 &tegra_sdmmc1,
1178 &tegra_sdmmc2,
1179 &tegra_sdmmc3,
1180 &tegra_sdmmc4,
1181 &tegra_vcp,
1182 &tegra_bsea,
1183 &tegra_bsev,
1184 &tegra_vde,
1185 &tegra_csite,
1186 &tegra_la,
1187 &tegra_owr,
1188 &tegra_nor,
1189 &tegra_mipi,
1190 &tegra_i2c1,
1191 &tegra_i2c2,
1192 &tegra_i2c3,
1193 &tegra_i2c4,
1194 &tegra_i2c5,
1195 &tegra_uarta,
1196 &tegra_uartb,
1197 &tegra_uartc,
1198 &tegra_uartd,
1199 &tegra_uarte,
1200 &tegra_vi,
1201 &tegra_3d,
1202 &tegra_3d2,
1203 &tegra_2d,
1204 &tegra_vi_sensor,
1205 &tegra_epp,
1206 &tegra_mpe,
1207 &tegra_host1x,
1208 &tegra_cve,
1209 &tegra_tvo,
1210 &tegra_dtv,
1211 &tegra_hdmi,
1212 &tegra_tvdac,
1213 &tegra_disp1,
1214 &tegra_disp2,
1215 &tegra_usbd,
1216 &tegra_usb2,
1217 &tegra_usb3,
1218 &tegra_dsia,
1219 &tegra_dsib,
1220 &tegra_csi,
1221 &tegra_isp,
1222 &tegra_csus,
1223 &tegra_tsensor,
1224 &tegra_actmon,
1225 &tegra_extern1,
1226 &tegra_extern2,
1227 &tegra_extern3,
1228 &tegra_i2cslow,
1229 &tegra_pcie,
1230 &tegra_afi,
1231 &tegra_se,
1232 };
1233
1234 #define CLK_DUPLICATE(_name, _dev, _con) \
1235 { \
1236 .name = _name, \
1237 .lookup = { \
1238 .dev_id = _dev, \
1239 .con_id = _con, \
1240 }, \
1241 }
1242
1243 /* Some clocks may be used by different drivers depending on the board
1244 * configuration. List those here to register them twice in the clock lookup
1245 * table under two names.
1246 */
1247 struct clk_duplicate tegra_clk_duplicates[] = {
1248 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1249 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1250 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1251 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1252 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1253 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1254 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1255 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1256 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1257 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1258 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1259 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1260 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1261 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1262 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1263 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1264 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1265 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1266 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1267 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1268 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1269 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1270 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1271 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1272 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1273 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1274 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1275 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1276 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1277 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1278 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1279 CLK_DUPLICATE("twd", "smp_twd", NULL),
1280 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1281 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1282 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1283 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1284 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1285 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1286 CLK_DUPLICATE("dam0", NULL, "dam0"),
1287 CLK_DUPLICATE("dam1", NULL, "dam1"),
1288 CLK_DUPLICATE("dam2", NULL, "dam2"),
1289 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1290 };
1291
1292 struct clk *tegra_ptr_clks[] = {
1293 &tegra_clk_32k,
1294 &tegra_clk_m,
1295 &tegra_clk_m_div2,
1296 &tegra_clk_m_div4,
1297 &tegra_pll_ref,
1298 &tegra_pll_m,
1299 &tegra_pll_m_out1,
1300 &tegra_pll_c,
1301 &tegra_pll_c_out1,
1302 &tegra_pll_p,
1303 &tegra_pll_p_out1,
1304 &tegra_pll_p_out2,
1305 &tegra_pll_p_out3,
1306 &tegra_pll_p_out4,
1307 &tegra_pll_a,
1308 &tegra_pll_a_out0,
1309 &tegra_pll_d,
1310 &tegra_pll_d_out0,
1311 &tegra_pll_d2,
1312 &tegra_pll_d2_out0,
1313 &tegra_pll_u,
1314 &tegra_pll_x,
1315 &tegra_pll_x_out0,
1316 &tegra_pll_e,
1317 &tegra_clk_cclk_g,
1318 &tegra_cml0,
1319 &tegra_cml1,
1320 &tegra_pciex,
1321 &tegra_clk_sclk,
1322 &tegra_clk_blink,
1323 &tegra30_clk_twd,
1324 };
1325
1326 static void tegra30_init_one_clock(struct clk *c)
1327 {
1328 struct clk_tegra *clk = to_clk_tegra(c->hw);
1329 __clk_init(NULL, c);
1330 INIT_LIST_HEAD(&clk->shared_bus_list);
1331 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1332 clk->lookup.con_id = c->name;
1333 clk->lookup.clk = c;
1334 clkdev_add(&clk->lookup);
1335 tegra_clk_add(c);
1336 }
1337
1338 void __init tegra30_init_clocks(void)
1339 {
1340 int i;
1341 struct clk *c;
1342
1343 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1344 tegra30_init_one_clock(tegra_ptr_clks[i]);
1345
1346 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1347 tegra30_init_one_clock(tegra_list_clks[i]);
1348
1349 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1350 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1351 if (!c) {
1352 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1353 tegra_clk_duplicates[i].name);
1354 continue;
1355 }
1356
1357 tegra_clk_duplicates[i].lookup.clk = c;
1358 clkdev_add(&tegra_clk_duplicates[i].lookup);
1359 }
1360
1361 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1362 tegra30_init_one_clock(tegra_sync_source_list[i]);
1363 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1364 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1365 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1366 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1367
1368 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1369 tegra30_init_one_clock(tegra_clk_out_list[i]);
1370
1371 tegra30_cpu_car_ops_init();
1372 }
Linux kernel - Deliverables
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