arch/arm/mach-tegra/tegra_cpu_car.h

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __MACH_TEGRA_CPU_CAR_H
  18 #define __MACH_TEGRA_CPU_CAR_H
  19
  20 /*
  21  * Tegra CPU clock and reset control ops
  22  *
  23  * wait_for_reset:
  24  *      keep waiting until the CPU in reset state
  25  * put_in_reset:
  26  *      put the CPU in reset state
  27  * out_of_reset:
  28  *      release the CPU from reset state
  29  * enable_clock:
  30  *      CPU clock un-gate
  31  * disable_clock:
  32  *      CPU clock gate
  33  * rail_off_ready:
  34  *      CPU is ready for rail off
  35  * suspend:
  36  *      save the clock settings when CPU go into low-power state
  37  * resume:
  38  *      restore the clock settings when CPU exit low-power state
  39  */
  40 struct tegra_cpu_car_ops {
  41         void (*wait_for_reset)(u32 cpu);
  42         void (*put_in_reset)(u32 cpu);
  43         void (*out_of_reset)(u32 cpu);
  44         void (*enable_clock)(u32 cpu);
  45         void (*disable_clock)(u32 cpu);
  46 #ifdef CONFIG_PM_SLEEP
  47         bool (*rail_off_ready)(void);
  48         void (*suspend)(void);
  49         void (*resume)(void);
  50 #endif
  51 };
  52
  53 extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
  54
  55 static inline void tegra_wait_cpu_in_reset(u32 cpu)
  56 {
  57         if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
  58                 return;
  59
  60         tegra_cpu_car_ops->wait_for_reset(cpu);
  61 }
  62
  63 static inline void tegra_put_cpu_in_reset(u32 cpu)
  64 {
  65         if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
  66                 return;
  67
  68         tegra_cpu_car_ops->put_in_reset(cpu);
  69 }
  70
  71 static inline void tegra_cpu_out_of_reset(u32 cpu)
  72 {
  73         if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
  74                 return;
  75
  76         tegra_cpu_car_ops->out_of_reset(cpu);
  77 }
  78
  79 static inline void tegra_enable_cpu_clock(u32 cpu)
  80 {
  81         if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
  82                 return;
  83
  84         tegra_cpu_car_ops->enable_clock(cpu);
  85 }
  86
  87 static inline void tegra_disable_cpu_clock(u32 cpu)
  88 {
  89         if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
  90                 return;
  91
  92         tegra_cpu_car_ops->disable_clock(cpu);
  93 }
  94
  95 #ifdef CONFIG_PM_SLEEP
  96 static inline bool tegra_cpu_rail_off_ready(void)
  97 {
  98         if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
  99                 return false;
 100
 101         return tegra_cpu_car_ops->rail_off_ready();
 102 }
 103
 104 static inline void tegra_cpu_clock_suspend(void)
 105 {
 106         if (WARN_ON(!tegra_cpu_car_ops->suspend))
 107                 return;
 108
 109         tegra_cpu_car_ops->suspend();
 110 }
 111
 112 static inline void tegra_cpu_clock_resume(void)
 113 {
 114         if (WARN_ON(!tegra_cpu_car_ops->resume))
 115                 return;
 116
 117         tegra_cpu_car_ops->resume();
 118 }
 119 #endif
 120
 121 void tegra20_cpu_car_ops_init(void);
 122 void tegra30_cpu_car_ops_init(void);
 123
 124 #endif /* __MACH_TEGRA_CPU_CAR_H */