arch/arm/mach-tegra/timer.c

   1 /*
   2  * arch/arch/mach-tegra/timer.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/err.h>
  22 #include <linux/time.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/clk.h>
  28 #include <linux/io.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31
  32 #include <asm/mach/time.h>
  33 #include <asm/smp_twd.h>
  34 #include <asm/sched_clock.h>
  35
  36 #include "board.h"
  37
  38 #define RTC_SECONDS            0x08
  39 #define RTC_SHADOW_SECONDS     0x0c
  40 #define RTC_MILLISECONDS       0x10
  41
  42 #define TIMERUS_CNTR_1US 0x10
  43 #define TIMERUS_USEC_CFG 0x14
  44 #define TIMERUS_CNTR_FREEZE 0x4c
  45
  46 #define TIMER1_BASE 0x0
  47 #define TIMER2_BASE 0x8
  48 #define TIMER3_BASE 0x50
  49 #define TIMER4_BASE 0x58
  50
  51 #define TIMER_PTV 0x0
  52 #define TIMER_PCR 0x4
  53
  54 static void __iomem *timer_reg_base;
  55 static void __iomem *rtc_base;
  56
  57 static struct timespec persistent_ts;
  58 static u64 persistent_ms, last_persistent_ms;
  59
  60 #define timer_writel(value, reg) \
  61         __raw_writel(value, timer_reg_base + (reg))
  62 #define timer_readl(reg) \
  63         __raw_readl(timer_reg_base + (reg))
  64
  65 static int tegra_timer_set_next_event(unsigned long cycles,
  66                                          struct clock_event_device *evt)
  67 {
  68         u32 reg;
  69
  70         reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
  71         timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  72
  73         return 0;
  74 }
  75
  76 static void tegra_timer_set_mode(enum clock_event_mode mode,
  77                                     struct clock_event_device *evt)
  78 {
  79         u32 reg;
  80
  81         timer_writel(0, TIMER3_BASE + TIMER_PTV);
  82
  83         switch (mode) {
  84         case CLOCK_EVT_MODE_PERIODIC:
  85                 reg = 0xC0000000 | ((1000000/HZ)-1);
  86                 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  87                 break;
  88         case CLOCK_EVT_MODE_ONESHOT:
  89                 break;
  90         case CLOCK_EVT_MODE_UNUSED:
  91         case CLOCK_EVT_MODE_SHUTDOWN:
  92         case CLOCK_EVT_MODE_RESUME:
  93                 break;
  94         }
  95 }
  96
  97 static struct clock_event_device tegra_clockevent = {
  98         .name           = "timer0",
  99         .rating         = 300,
 100         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 101         .set_next_event = tegra_timer_set_next_event,
 102         .set_mode       = tegra_timer_set_mode,
 103 };
 104
 105 static u32 notrace tegra_read_sched_clock(void)
 106 {
 107         return timer_readl(TIMERUS_CNTR_1US);
 108 }
 109
 110 /*
 111  * tegra_rtc_read - Reads the Tegra RTC registers
 112  * Care must be taken that this funciton is not called while the
 113  * tegra_rtc driver could be executing to avoid race conditions
 114  * on the RTC shadow register
 115  */
 116 static u64 tegra_rtc_read_ms(void)
 117 {
 118         u32 ms = readl(rtc_base + RTC_MILLISECONDS);
 119         u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
 120         return (u64)s * MSEC_PER_SEC + ms;
 121 }
 122
 123 /*
 124  * tegra_read_persistent_clock -  Return time from a persistent clock.
 125  *
 126  * Reads the time from a source which isn't disabled during PM, the
 127  * 32k sync timer.  Convert the cycles elapsed since last read into
 128  * nsecs and adds to a monotonically increasing timespec.
 129  * Care must be taken that this funciton is not called while the
 130  * tegra_rtc driver could be executing to avoid race conditions
 131  * on the RTC shadow register
 132  */
 133 static void tegra_read_persistent_clock(struct timespec *ts)
 134 {
 135         u64 delta;
 136         struct timespec *tsp = &persistent_ts;
 137
 138         last_persistent_ms = persistent_ms;
 139         persistent_ms = tegra_rtc_read_ms();
 140         delta = persistent_ms - last_persistent_ms;
 141
 142         timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
 143         *ts = *tsp;
 144 }
 145
 146 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 147 {
 148         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 149         timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
 150         evt->event_handler(evt);
 151         return IRQ_HANDLED;
 152 }
 153
 154 static struct irqaction tegra_timer_irq = {
 155         .name           = "timer0",
 156         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
 157         .handler        = tegra_timer_interrupt,
 158         .dev_id         = &tegra_clockevent,
 159 };
 160
 161 static const struct of_device_id timer_match[] __initconst = {
 162         { .compatible = "nvidia,tegra20-timer" },
 163         {}
 164 };
 165
 166 static const struct of_device_id rtc_match[] __initconst = {
 167         { .compatible = "nvidia,tegra20-rtc" },
 168         {}
 169 };
 170
 171 static void __init tegra_init_timer(void)
 172 {
 173         struct device_node *np;
 174         struct clk *clk;
 175         unsigned long rate;
 176         int ret;
 177
 178         np = of_find_matching_node(NULL, timer_match);
 179         if (!np) {
 180                 pr_err("Failed to find timer DT node\n");
 181                 BUG();
 182         }
 183
 184         timer_reg_base = of_iomap(np, 0);
 185         if (!timer_reg_base) {
 186                 pr_err("Can't map timer registers");
 187                 BUG();
 188         }
 189
 190         tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
 191         if (tegra_timer_irq.irq <= 0) {
 192                 pr_err("Failed to map timer IRQ\n");
 193                 BUG();
 194         }
 195
 196         clk = clk_get_sys("timer", NULL);
 197         if (IS_ERR(clk)) {
 198                 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
 199                 rate = 12000000;
 200         } else {
 201                 clk_prepare_enable(clk);
 202                 rate = clk_get_rate(clk);
 203         }
 204
 205         of_node_put(np);
 206
 207         np = of_find_matching_node(NULL, rtc_match);
 208         if (!np) {
 209                 pr_err("Failed to find RTC DT node\n");
 210                 BUG();
 211         }
 212
 213         rtc_base = of_iomap(np, 0);
 214         if (!rtc_base) {
 215                 pr_err("Can't map RTC registers");
 216                 BUG();
 217         }
 218
 219         /*
 220          * rtc registers are used by read_persistent_clock, keep the rtc clock
 221          * enabled
 222          */
 223         clk = clk_get_sys("rtc-tegra", NULL);
 224         if (IS_ERR(clk))
 225                 pr_warn("Unable to get rtc-tegra clock\n");
 226         else
 227                 clk_prepare_enable(clk);
 228
 229         of_node_put(np);
 230
 231         switch (rate) {
 232         case 12000000:
 233                 timer_writel(0x000b, TIMERUS_USEC_CFG);
 234                 break;
 235         case 13000000:
 236                 timer_writel(0x000c, TIMERUS_USEC_CFG);
 237                 break;
 238         case 19200000:
 239                 timer_writel(0x045f, TIMERUS_USEC_CFG);
 240                 break;
 241         case 26000000:
 242                 timer_writel(0x0019, TIMERUS_USEC_CFG);
 243                 break;
 244         default:
 245                 WARN(1, "Unknown clock rate");
 246         }
 247
 248         setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
 249
 250         if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
 251                 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
 252                 pr_err("Failed to register clocksource\n");
 253                 BUG();
 254         }
 255
 256         ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
 257         if (ret) {
 258                 pr_err("Failed to register timer IRQ: %d\n", ret);
 259                 BUG();
 260         }
 261
 262         clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
 263         tegra_clockevent.max_delta_ns =
 264                 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
 265         tegra_clockevent.min_delta_ns =
 266                 clockevent_delta2ns(0x1, &tegra_clockevent);
 267         tegra_clockevent.cpumask = cpu_all_mask;
 268         tegra_clockevent.irq = tegra_timer_irq.irq;
 269         clockevents_register_device(&tegra_clockevent);
 270 #ifdef CONFIG_HAVE_ARM_TWD
 271         twd_local_timer_of_register();
 272 #endif
 273         register_persistent_clock(NULL, tegra_read_persistent_clock);
 274 }
 275
 276 struct sys_timer tegra_sys_timer = {
 277         .init = tegra_init_timer,
 278 };
 279
 280 #ifdef CONFIG_PM
 281 static u32 usec_config;
 282
 283 void tegra_timer_suspend(void)
 284 {
 285         usec_config = timer_readl(TIMERUS_USEC_CFG);
 286 }
 287
 288 void tegra_timer_resume(void)
 289 {
 290         timer_writel(usec_config, TIMERUS_USEC_CFG);
 291 }
 292 #endif