arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/io.h>
  10 #include <linux/clk.h>
  11 #include <linux/mfd/db8500-prcmu.h>
  12
  13 #include <asm/cacheflush.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16 #include <asm/mach/map.h>
  17 #include <asm/localtimer.h>
  18
  19 #include <plat/mtu.h>
  20 #include <mach/hardware.h>
  21 #include <mach/setup.h>
  22 #include <mach/devices.h>
  23
  24 #include "clock.h"
  25
  26 void __iomem *_PRCMU_BASE;
  27
  28 #ifdef CONFIG_CACHE_L2X0
  29 static void __iomem *l2x0_base;
  30 #endif
  31
  32 void __init ux500_init_irq(void)
  33 {
  34         void __iomem *dist_base;
  35         void __iomem *cpu_base;
  36
  37         if (cpu_is_u5500()) {
  38                 dist_base = __io_address(U5500_GIC_DIST_BASE);
  39                 cpu_base = __io_address(U5500_GIC_CPU_BASE);
  40         } else if (cpu_is_u8500()) {
  41                 dist_base = __io_address(U8500_GIC_DIST_BASE);
  42                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
  43         } else
  44                 ux500_unknown_soc();
  45
  46         gic_init(0, 29, dist_base, cpu_base);
  47
  48         /*
  49          * Init clocks here so that they are available for system timer
  50          * initialization.
  51          */
  52         if (cpu_is_u8500())
  53                 prcmu_early_init();
  54         clk_init();
  55 }
  56
  57 #ifdef CONFIG_CACHE_L2X0
  58 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  59 {
  60         /* wait for the operation to complete */
  61         while (readl_relaxed(reg) & mask)
  62                 ;
  63 }
  64
  65 static inline void ux500_cache_sync(void)
  66 {
  67         void __iomem *base = l2x0_base;
  68
  69         writel_relaxed(0, base + L2X0_CACHE_SYNC);
  70         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  71 }
  72
  73 /*
  74  * The L2 cache cannot be turned off in the non-secure world.
  75  * Dummy until a secure service is in place.
  76  */
  77 static void ux500_l2x0_disable(void)
  78 {
  79 }
  80
  81 /*
  82  * This is only called when doing a kexec, just after turning off the L2
  83  * and L1 cache, and it is surrounded by a spinlock in the generic version.
  84  * However, we're not really turning off the L2 cache right now and the
  85  * PL310 does not support exclusive accesses (used to implement the spinlock).
  86  * So, the invalidation needs to be done without the spinlock.
  87  */
  88 static void ux500_l2x0_inv_all(void)
  89 {
  90         void __iomem *base = l2x0_base;
  91         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
  92
  93         /* invalidate all ways */
  94         writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
  95         ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
  96         ux500_cache_sync();
  97 }
  98
  99 static int ux500_l2x0_init(void)
 100 {
 101         if (cpu_is_u5500())
 102                 l2x0_base = __io_address(U5500_L2CC_BASE);
 103         else if (cpu_is_u8500())
 104                 l2x0_base = __io_address(U8500_L2CC_BASE);
 105         else
 106                 ux500_unknown_soc();
 107
 108         /* 64KB way size, 8 way associativity, force WA */
 109         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 110
 111         /* Override invalidate function */
 112         outer_cache.disable = ux500_l2x0_disable;
 113         outer_cache.inv_all = ux500_l2x0_inv_all;
 114
 115         return 0;
 116 }
 117 early_initcall(ux500_l2x0_init);
 118 #endif
 119
 120 static void __init ux500_timer_init(void)
 121 {
 122 #ifdef CONFIG_LOCAL_TIMERS
 123         /* Setup the local timer base */
 124         if (cpu_is_u5500())
 125                 twd_base = __io_address(U5500_TWD_BASE);
 126         else if (cpu_is_u8500())
 127                 twd_base = __io_address(U8500_TWD_BASE);
 128         else
 129                 ux500_unknown_soc();
 130 #endif
 131         if (cpu_is_u5500())
 132                 mtu_base = __io_address(U5500_MTU0_BASE);
 133         else if (cpu_is_u8500ed())
 134                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 135         else if (cpu_is_u8500())
 136                 mtu_base = __io_address(U8500_MTU0_BASE);
 137         else
 138                 ux500_unknown_soc();
 139
 140         nmdk_timer_init();
 141 }
 142
 143 struct sys_timer ux500_timer = {
 144         .init   = ux500_timer_init,
 145 };