2 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/platform_device.h>
10 #include <linux/clk.h>
12 #include <asm/cacheflush.h>
13 #include <asm/hardware/cache-l2x0.h>
14 #include <asm/hardware/gic.h>
15 #include <asm/mach/map.h>
16 #include <asm/localtimer.h>
19 #include <mach/hardware.h>
20 #include <mach/setup.h>
21 #include <mach/devices.h>
22 #include <mach/prcmu.h>
26 #ifdef CONFIG_CACHE_L2X0
27 static void __iomem
*l2x0_base
;
30 void __init
ux500_map_io(void)
34 void __init
ux500_init_irq(void)
36 void __iomem
*dist_base
;
37 void __iomem
*cpu_base
;
40 dist_base
= __io_address(U5500_GIC_DIST_BASE
);
41 cpu_base
= __io_address(U5500_GIC_CPU_BASE
);
42 } else if (cpu_is_u8500()) {
43 dist_base
= __io_address(U8500_GIC_DIST_BASE
);
44 cpu_base
= __io_address(U8500_GIC_CPU_BASE
);
48 gic_init(0, 29, dist_base
, cpu_base
);
51 * Init clocks here so that they are available for system timer
59 #ifdef CONFIG_CACHE_L2X0
60 static inline void ux500_cache_wait(void __iomem
*reg
, unsigned long mask
)
62 /* wait for the operation to complete */
63 while (readl_relaxed(reg
) & mask
)
67 static inline void ux500_cache_sync(void)
69 void __iomem
*base
= l2x0_base
;
71 writel_relaxed(0, base
+ L2X0_CACHE_SYNC
);
72 ux500_cache_wait(base
+ L2X0_CACHE_SYNC
, 1);
76 * The L2 cache cannot be turned off in the non-secure world.
77 * Dummy until a secure service is in place.
79 static void ux500_l2x0_disable(void)
84 * This is only called when doing a kexec, just after turning off the L2
85 * and L1 cache, and it is surrounded by a spinlock in the generic version.
86 * However, we're not really turning off the L2 cache right now and the
87 * PL310 does not support exclusive accesses (used to implement the spinlock).
88 * So, the invalidation needs to be done without the spinlock.
90 static void ux500_l2x0_inv_all(void)
92 void __iomem
*base
= l2x0_base
;
93 uint32_t l2x0_way_mask
= (1<<16) - 1; /* Bitmask of active ways */
95 /* invalidate all ways */
96 writel_relaxed(l2x0_way_mask
, base
+ L2X0_INV_WAY
);
97 ux500_cache_wait(base
+ L2X0_INV_WAY
, l2x0_way_mask
);
101 static int ux500_l2x0_init(void)
104 l2x0_base
= __io_address(U5500_L2CC_BASE
);
105 else if (cpu_is_u8500())
106 l2x0_base
= __io_address(U8500_L2CC_BASE
);
110 /* 64KB way size, 8 way associativity, force WA */
111 l2x0_init(l2x0_base
, 0x3e060000, 0xc0000fff);
113 /* Override invalidate function */
114 outer_cache
.disable
= ux500_l2x0_disable
;
115 outer_cache
.inv_all
= ux500_l2x0_inv_all
;
119 early_initcall(ux500_l2x0_init
);
122 static void __init
ux500_timer_init(void)
124 #ifdef CONFIG_LOCAL_TIMERS
125 /* Setup the local timer base */
127 twd_base
= __io_address(U5500_TWD_BASE
);
128 else if (cpu_is_u8500())
129 twd_base
= __io_address(U8500_TWD_BASE
);
134 mtu_base
= __io_address(U5500_MTU0_BASE
);
135 else if (cpu_is_u8500ed())
136 mtu_base
= __io_address(U8500_MTU0_BASE_ED
);
137 else if (cpu_is_u8500())
138 mtu_base
= __io_address(U8500_MTU0_BASE
);
145 struct sys_timer ux500_timer
= {
146 .init
= ux500_timer_init
,
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