arch/arm/mach-ux500/cpu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/io.h>
  10 #include <linux/clk.h>
  11
  12 #include <asm/cacheflush.h>
  13 #include <asm/hardware/cache-l2x0.h>
  14 #include <asm/hardware/gic.h>
  15 #include <asm/mach/map.h>
  16 #include <asm/localtimer.h>
  17
  18 #include <plat/mtu.h>
  19 #include <mach/hardware.h>
  20 #include <mach/setup.h>
  21 #include <mach/devices.h>
  22 #include <mach/prcmu.h>
  23
  24 #include "clock.h"
  25
  26 #ifdef CONFIG_CACHE_L2X0
  27 static void __iomem *l2x0_base;
  28 #endif
  29
  30 void __init ux500_map_io(void)
  31 {
  32 }
  33
  34 void __init ux500_init_irq(void)
  35 {
  36         void __iomem *dist_base;
  37         void __iomem *cpu_base;
  38
  39         if (cpu_is_u5500()) {
  40                 dist_base = __io_address(U5500_GIC_DIST_BASE);
  41                 cpu_base = __io_address(U5500_GIC_CPU_BASE);
  42         } else if (cpu_is_u8500()) {
  43                 dist_base = __io_address(U8500_GIC_DIST_BASE);
  44                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
  45         } else
  46                 ux500_unknown_soc();
  47
  48         gic_init(0, 29, dist_base, cpu_base);
  49
  50         /*
  51          * Init clocks here so that they are available for system timer
  52          * initialization.
  53          */
  54         if (cpu_is_u8500())
  55                 prcmu_early_init();
  56         clk_init();
  57 }
  58
  59 #ifdef CONFIG_CACHE_L2X0
  60 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
  61 {
  62         /* wait for the operation to complete */
  63         while (readl_relaxed(reg) & mask)
  64                 ;
  65 }
  66
  67 static inline void ux500_cache_sync(void)
  68 {
  69         void __iomem *base = l2x0_base;
  70
  71         writel_relaxed(0, base + L2X0_CACHE_SYNC);
  72         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
  73 }
  74
  75 /*
  76  * The L2 cache cannot be turned off in the non-secure world.
  77  * Dummy until a secure service is in place.
  78  */
  79 static void ux500_l2x0_disable(void)
  80 {
  81 }
  82
  83 /*
  84  * This is only called when doing a kexec, just after turning off the L2
  85  * and L1 cache, and it is surrounded by a spinlock in the generic version.
  86  * However, we're not really turning off the L2 cache right now and the
  87  * PL310 does not support exclusive accesses (used to implement the spinlock).
  88  * So, the invalidation needs to be done without the spinlock.
  89  */
  90 static void ux500_l2x0_inv_all(void)
  91 {
  92         void __iomem *base = l2x0_base;
  93         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
  94
  95         /* invalidate all ways */
  96         writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
  97         ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
  98         ux500_cache_sync();
  99 }
 100
 101 static int ux500_l2x0_init(void)
 102 {
 103         if (cpu_is_u5500())
 104                 l2x0_base = __io_address(U5500_L2CC_BASE);
 105         else if (cpu_is_u8500())
 106                 l2x0_base = __io_address(U8500_L2CC_BASE);
 107         else
 108                 ux500_unknown_soc();
 109
 110         /* 64KB way size, 8 way associativity, force WA */
 111         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 112
 113         /* Override invalidate function */
 114         outer_cache.disable = ux500_l2x0_disable;
 115         outer_cache.inv_all = ux500_l2x0_inv_all;
 116
 117         return 0;
 118 }
 119 early_initcall(ux500_l2x0_init);
 120 #endif
 121
 122 static void __init ux500_timer_init(void)
 123 {
 124 #ifdef CONFIG_LOCAL_TIMERS
 125         /* Setup the local timer base */
 126         if (cpu_is_u5500())
 127                 twd_base = __io_address(U5500_TWD_BASE);
 128         else if (cpu_is_u8500())
 129                 twd_base = __io_address(U8500_TWD_BASE);
 130         else
 131                 ux500_unknown_soc();
 132 #endif
 133         if (cpu_is_u5500())
 134                 mtu_base = __io_address(U5500_MTU0_BASE);
 135         else if (cpu_is_u8500ed())
 136                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
 137         else if (cpu_is_u8500())
 138                 mtu_base = __io_address(U8500_MTU0_BASE);
 139         else
 140                 ux500_unknown_soc();
 141
 142         nmdk_timer_init();
 143 }
 144
 145 struct sys_timer ux500_timer = {
 146         .init   = ux500_timer_init,
 147 };