arch/arm/mach-ux500/timer.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2011
   3  *
   4  * License Terms: GNU General Public License v2
   5  * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
   6  */
   7 #include <linux/io.h>
   8 #include <linux/errno.h>
   9 #include <linux/clksrc-dbx500-prcmu.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12
  13 #include <asm/smp_twd.h>
  14
  15 #include <plat/mtu.h>
  16
  17 #include <mach/setup.h>
  18 #include <mach/hardware.h>
  19 #include <mach/irqs.h>
  20
  21 #ifdef CONFIG_HAVE_ARM_TWD
  22 static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
  23                               U8500_TWD_BASE, IRQ_LOCALTIMER);
  24
  25 static void __init ux500_twd_init(void)
  26 {
  27         struct twd_local_timer *twd_local_timer;
  28         int err;
  29
  30         /* Use this to switch local timer base if changed in new ASICs */
  31         twd_local_timer = &u8500_twd_local_timer;
  32
  33         if (of_have_populated_dt())
  34                 twd_local_timer_of_register();
  35         else {
  36                 err = twd_local_timer_register(twd_local_timer);
  37                 if (err)
  38                         pr_err("twd_local_timer_register failed %d\n", err);
  39         }
  40 }
  41 #else
  42 #define ux500_twd_init()        do { } while(0)
  43 #endif
  44
  45 const static struct of_device_id prcmu_timer_of_match[] __initconst = {
  46         { .compatible = "stericsson,db8500-prcmu-timer-4", },
  47         { },
  48 };
  49
  50 static void __init ux500_timer_init(void)
  51 {
  52         void __iomem *mtu_timer_base;
  53         void __iomem *prcmu_timer_base;
  54         void __iomem *tmp_base;
  55         struct device_node *np;
  56
  57         if (cpu_is_u8500_family()) {
  58                 mtu_timer_base = __io_address(U8500_MTU0_BASE);
  59                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
  60         } else {
  61                 ux500_unknown_soc();
  62         }
  63
  64         /* TODO: Once MTU has been DT:ed place code above into else. */
  65         if (of_have_populated_dt()) {
  66 #ifdef CONFIG_OF
  67                 np = of_find_matching_node(NULL, prcmu_timer_of_match);
  68                 if (!np)
  69 #endif
  70                         goto dt_fail;
  71
  72                 tmp_base = of_iomap(np, 0);
  73                 if (!tmp_base)
  74                         goto dt_fail;
  75
  76                 prcmu_timer_base = tmp_base;
  77         }
  78
  79 dt_fail:
  80         /* Doing it the old fashioned way. */
  81
  82         /*
  83          * Here we register the timerblocks active in the system.
  84          * Localtimers (twd) is started when both cpu is up and running.
  85          * MTU register a clocksource, clockevent and sched_clock.
  86          * Since the MTU is located in the VAPE power domain
  87          * it will be cleared in sleep which makes it unsuitable.
  88          * We however need it as a timer tick (clockevent)
  89          * during boot to calibrate delay until twd is started.
  90          * RTC-RTT have problems as timer tick during boot since it is
  91          * depending on delay which is not yet calibrated. RTC-RTT is in the
  92          * always-on powerdomain and is used as clockevent instead of twd when
  93          * sleeping.
  94          * The PRCMU timer 4 register a clocksource and
  95          * sched_clock with higher rating then MTU since is always-on.
  96          *
  97          */
  98
  99         nmdk_timer_init(mtu_timer_base);
 100         clksrc_dbx500_prcmu_init(prcmu_timer_base);
 101         ux500_twd_init();
 102 }
 103
 104 static void ux500_timer_reset(void)
 105 {
 106         nmdk_clkevt_reset();
 107         nmdk_clksrc_reset();
 108 }
 109
 110 struct sys_timer ux500_timer = {
 111         .init           = ux500_timer_init,
 112         .resume         = ux500_timer_reset,
 113 };