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clocksource: pass clocksource to read() callback
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/cnt32_to_63.h>
32 #include <linux/io.h>
33
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst307.h>
41 #include <asm/hardware/vic.h>
42 #include <asm/mach-types.h>
43
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/mmc.h>
50
51 #include "core.h"
52 #include "clock.h"
53
54 /*
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
56 * is the (PA >> 12).
57 *
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
59 */
60 #define __io_address(n) __io(IO_ADDRESS(n))
61 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
62 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
63
64 static void sic_mask_irq(unsigned int irq)
65 {
66 irq -= IRQ_SIC_START;
67 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
68 }
69
70 static void sic_unmask_irq(unsigned int irq)
71 {
72 irq -= IRQ_SIC_START;
73 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
74 }
75
76 static struct irq_chip sic_chip = {
77 .name = "SIC",
78 .ack = sic_mask_irq,
79 .mask = sic_mask_irq,
80 .unmask = sic_unmask_irq,
81 };
82
83 static void
84 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
85 {
86 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
87
88 if (status == 0) {
89 do_bad_IRQ(irq, desc);
90 return;
91 }
92
93 do {
94 irq = ffs(status) - 1;
95 status &= ~(1 << irq);
96
97 irq += IRQ_SIC_START;
98
99 generic_handle_irq(irq);
100 } while (status);
101 }
102
103 #if 1
104 #define IRQ_MMCI0A IRQ_VICSOURCE22
105 #define IRQ_AACI IRQ_VICSOURCE24
106 #define IRQ_ETH IRQ_VICSOURCE25
107 #define PIC_MASK 0xFFD00000
108 #else
109 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
110 #define IRQ_AACI IRQ_SIC_AACI
111 #define IRQ_ETH IRQ_SIC_ETH
112 #define PIC_MASK 0
113 #endif
114
115 void __init versatile_init_irq(void)
116 {
117 unsigned int i;
118
119 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
120
121 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
122
123 /* Do second interrupt controller */
124 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
125
126 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
127 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
128 set_irq_chip(i, &sic_chip);
129 set_irq_handler(i, handle_level_irq);
130 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
131 }
132 }
133
134 /*
135 * Interrupts on secondary controller from 0 to 8 are routed to
136 * source 31 on PIC.
137 * Interrupts from 21 to 31 are routed directly to the VIC on
138 * the corresponding number on primary controller. This is controlled
139 * by setting PIC_ENABLEx.
140 */
141 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
142 }
143
144 static struct map_desc versatile_io_desc[] __initdata = {
145 {
146 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
147 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
148 .length = SZ_4K,
149 .type = MT_DEVICE
150 }, {
151 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
152 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
153 .length = SZ_4K,
154 .type = MT_DEVICE
155 }, {
156 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
157 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
158 .length = SZ_4K,
159 .type = MT_DEVICE
160 }, {
161 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
162 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
163 .length = SZ_4K * 9,
164 .type = MT_DEVICE
165 },
166 #ifdef CONFIG_MACH_VERSATILE_AB
167 {
168 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
169 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
170 .length = SZ_4K,
171 .type = MT_DEVICE
172 }, {
173 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
174 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
175 .length = SZ_64M,
176 .type = MT_DEVICE
177 },
178 #endif
179 #ifdef CONFIG_DEBUG_LL
180 {
181 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
182 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
183 .length = SZ_4K,
184 .type = MT_DEVICE
185 },
186 #endif
187 #ifdef CONFIG_PCI
188 {
189 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
190 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
191 .length = SZ_4K,
192 .type = MT_DEVICE
193 }, {
194 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
195 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
196 .length = VERSATILE_PCI_BASE_SIZE,
197 .type = MT_DEVICE
198 }, {
199 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
200 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
201 .length = VERSATILE_PCI_CFG_BASE_SIZE,
202 .type = MT_DEVICE
203 },
204 #if 0
205 {
206 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
207 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
208 .length = SZ_16M,
209 .type = MT_DEVICE
210 }, {
211 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
212 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
213 .length = SZ_16M,
214 .type = MT_DEVICE
215 }, {
216 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
217 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
218 .length = SZ_16M,
219 .type = MT_DEVICE
220 },
221 #endif
222 #endif
223 };
224
225 void __init versatile_map_io(void)
226 {
227 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
228 }
229
230 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
231
232 /*
233 * This is the Versatile sched_clock implementation. This has
234 * a resolution of 41.7ns, and a maximum value of about 35583 days.
235 *
236 * The return value is guaranteed to be monotonic in that range as
237 * long as there is always less than 89 seconds between successive
238 * calls to this function.
239 */
240 unsigned long long sched_clock(void)
241 {
242 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
243
244 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
245 v *= 125<<1;
246 do_div(v, 3<<1);
247
248 return v;
249 }
250
251
252 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
253
254 static int versatile_flash_init(void)
255 {
256 u32 val;
257
258 val = __raw_readl(VERSATILE_FLASHCTRL);
259 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
260 __raw_writel(val, VERSATILE_FLASHCTRL);
261
262 return 0;
263 }
264
265 static void versatile_flash_exit(void)
266 {
267 u32 val;
268
269 val = __raw_readl(VERSATILE_FLASHCTRL);
270 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
271 __raw_writel(val, VERSATILE_FLASHCTRL);
272 }
273
274 static void versatile_flash_set_vpp(int on)
275 {
276 u32 val;
277
278 val = __raw_readl(VERSATILE_FLASHCTRL);
279 if (on)
280 val |= VERSATILE_FLASHPROG_FLVPPEN;
281 else
282 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
283 __raw_writel(val, VERSATILE_FLASHCTRL);
284 }
285
286 static struct flash_platform_data versatile_flash_data = {
287 .map_name = "cfi_probe",
288 .width = 4,
289 .init = versatile_flash_init,
290 .exit = versatile_flash_exit,
291 .set_vpp = versatile_flash_set_vpp,
292 };
293
294 static struct resource versatile_flash_resource = {
295 .start = VERSATILE_FLASH_BASE,
296 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
297 .flags = IORESOURCE_MEM,
298 };
299
300 static struct platform_device versatile_flash_device = {
301 .name = "armflash",
302 .id = 0,
303 .dev = {
304 .platform_data = &versatile_flash_data,
305 },
306 .num_resources = 1,
307 .resource = &versatile_flash_resource,
308 };
309
310 static struct resource smc91x_resources[] = {
311 [0] = {
312 .start = VERSATILE_ETH_BASE,
313 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = IRQ_ETH,
318 .end = IRQ_ETH,
319 .flags = IORESOURCE_IRQ,
320 },
321 };
322
323 static struct platform_device smc91x_device = {
324 .name = "smc91x",
325 .id = 0,
326 .num_resources = ARRAY_SIZE(smc91x_resources),
327 .resource = smc91x_resources,
328 };
329
330 static struct resource versatile_i2c_resource = {
331 .start = VERSATILE_I2C_BASE,
332 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
333 .flags = IORESOURCE_MEM,
334 };
335
336 static struct platform_device versatile_i2c_device = {
337 .name = "versatile-i2c",
338 .id = 0,
339 .num_resources = 1,
340 .resource = &versatile_i2c_resource,
341 };
342
343 static struct i2c_board_info versatile_i2c_board_info[] = {
344 {
345 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
346 .type = "ds1338",
347 },
348 };
349
350 static int __init versatile_i2c_init(void)
351 {
352 return i2c_register_board_info(0, versatile_i2c_board_info,
353 ARRAY_SIZE(versatile_i2c_board_info));
354 }
355 arch_initcall(versatile_i2c_init);
356
357 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
358
359 unsigned int mmc_status(struct device *dev)
360 {
361 struct amba_device *adev = container_of(dev, struct amba_device, dev);
362 u32 mask;
363
364 if (adev->res.start == VERSATILE_MMCI0_BASE)
365 mask = 1;
366 else
367 mask = 2;
368
369 return readl(VERSATILE_SYSMCI) & mask;
370 }
371
372 static struct mmc_platform_data mmc0_plat_data = {
373 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
374 .status = mmc_status,
375 };
376
377 /*
378 * Clock handling
379 */
380 static const struct icst307_params versatile_oscvco_params = {
381 .ref = 24000,
382 .vco_max = 200000,
383 .vd_min = 4 + 8,
384 .vd_max = 511 + 8,
385 .rd_min = 1 + 2,
386 .rd_max = 127 + 2,
387 };
388
389 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
390 {
391 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
392 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
393 u32 val;
394
395 val = readl(sys + clk->oscoff) & ~0x7ffff;
396 val |= vco.v | (vco.r << 9) | (vco.s << 16);
397
398 writel(0xa05f, sys_lock);
399 writel(val, sys + clk->oscoff);
400 writel(0, sys_lock);
401 }
402
403 static struct clk osc4_clk = {
404 .params = &versatile_oscvco_params,
405 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
406 .setvco = versatile_oscvco_set,
407 };
408
409 /*
410 * These are fixed clocks.
411 */
412 static struct clk ref24_clk = {
413 .rate = 24000000,
414 };
415
416 static struct clk_lookup lookups[] __initdata = {
417 { /* UART0 */
418 .dev_id = "dev:f1",
419 .clk = &ref24_clk,
420 }, { /* UART1 */
421 .dev_id = "dev:f2",
422 .clk = &ref24_clk,
423 }, { /* UART2 */
424 .dev_id = "dev:f3",
425 .clk = &ref24_clk,
426 }, { /* UART3 */
427 .dev_id = "fpga:09",
428 .clk = &ref24_clk,
429 }, { /* KMI0 */
430 .dev_id = "fpga:06",
431 .clk = &ref24_clk,
432 }, { /* KMI1 */
433 .dev_id = "fpga:07",
434 .clk = &ref24_clk,
435 }, { /* MMC0 */
436 .dev_id = "fpga:05",
437 .clk = &ref24_clk,
438 }, { /* MMC1 */
439 .dev_id = "fpga:0b",
440 .clk = &ref24_clk,
441 }, { /* CLCD */
442 .dev_id = "dev:20",
443 .clk = &osc4_clk,
444 }
445 };
446
447 /*
448 * CLCD support.
449 */
450 #define SYS_CLCD_MODE_MASK (3 << 0)
451 #define SYS_CLCD_MODE_888 (0 << 0)
452 #define SYS_CLCD_MODE_5551 (1 << 0)
453 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
454 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
455 #define SYS_CLCD_NLCDIOON (1 << 2)
456 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
457 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
458 #define SYS_CLCD_ID_MASK (0x1f << 8)
459 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
460 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
461 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
462 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
463 #define SYS_CLCD_ID_VGA (0x1f << 8)
464
465 static struct clcd_panel vga = {
466 .mode = {
467 .name = "VGA",
468 .refresh = 60,
469 .xres = 640,
470 .yres = 480,
471 .pixclock = 39721,
472 .left_margin = 40,
473 .right_margin = 24,
474 .upper_margin = 32,
475 .lower_margin = 11,
476 .hsync_len = 96,
477 .vsync_len = 2,
478 .sync = 0,
479 .vmode = FB_VMODE_NONINTERLACED,
480 },
481 .width = -1,
482 .height = -1,
483 .tim2 = TIM2_BCD | TIM2_IPC,
484 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
485 .bpp = 16,
486 };
487
488 static struct clcd_panel sanyo_3_8_in = {
489 .mode = {
490 .name = "Sanyo QVGA",
491 .refresh = 116,
492 .xres = 320,
493 .yres = 240,
494 .pixclock = 100000,
495 .left_margin = 6,
496 .right_margin = 6,
497 .upper_margin = 5,
498 .lower_margin = 5,
499 .hsync_len = 6,
500 .vsync_len = 6,
501 .sync = 0,
502 .vmode = FB_VMODE_NONINTERLACED,
503 },
504 .width = -1,
505 .height = -1,
506 .tim2 = TIM2_BCD,
507 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
508 .bpp = 16,
509 };
510
511 static struct clcd_panel sanyo_2_5_in = {
512 .mode = {
513 .name = "Sanyo QVGA Portrait",
514 .refresh = 116,
515 .xres = 240,
516 .yres = 320,
517 .pixclock = 100000,
518 .left_margin = 20,
519 .right_margin = 10,
520 .upper_margin = 2,
521 .lower_margin = 2,
522 .hsync_len = 10,
523 .vsync_len = 2,
524 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
525 .vmode = FB_VMODE_NONINTERLACED,
526 },
527 .width = -1,
528 .height = -1,
529 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
530 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
531 .bpp = 16,
532 };
533
534 static struct clcd_panel epson_2_2_in = {
535 .mode = {
536 .name = "Epson QCIF",
537 .refresh = 390,
538 .xres = 176,
539 .yres = 220,
540 .pixclock = 62500,
541 .left_margin = 3,
542 .right_margin = 2,
543 .upper_margin = 1,
544 .lower_margin = 0,
545 .hsync_len = 3,
546 .vsync_len = 2,
547 .sync = 0,
548 .vmode = FB_VMODE_NONINTERLACED,
549 },
550 .width = -1,
551 .height = -1,
552 .tim2 = TIM2_BCD | TIM2_IPC,
553 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
554 .bpp = 16,
555 };
556
557 /*
558 * Detect which LCD panel is connected, and return the appropriate
559 * clcd_panel structure. Note: we do not have any information on
560 * the required timings for the 8.4in panel, so we presently assume
561 * VGA timings.
562 */
563 static struct clcd_panel *versatile_clcd_panel(void)
564 {
565 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
566 struct clcd_panel *panel = &vga;
567 u32 val;
568
569 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
570 if (val == SYS_CLCD_ID_SANYO_3_8)
571 panel = &sanyo_3_8_in;
572 else if (val == SYS_CLCD_ID_SANYO_2_5)
573 panel = &sanyo_2_5_in;
574 else if (val == SYS_CLCD_ID_EPSON_2_2)
575 panel = &epson_2_2_in;
576 else if (val == SYS_CLCD_ID_VGA)
577 panel = &vga;
578 else {
579 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
580 val);
581 panel = &vga;
582 }
583
584 return panel;
585 }
586
587 /*
588 * Disable all display connectors on the interface module.
589 */
590 static void versatile_clcd_disable(struct clcd_fb *fb)
591 {
592 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
593 u32 val;
594
595 val = readl(sys_clcd);
596 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
597 writel(val, sys_clcd);
598
599 #ifdef CONFIG_MACH_VERSATILE_AB
600 /*
601 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
602 */
603 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
604 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
605 unsigned long ctrl;
606
607 ctrl = readl(versatile_ib2_ctrl);
608 ctrl &= ~0x01;
609 writel(ctrl, versatile_ib2_ctrl);
610 }
611 #endif
612 }
613
614 /*
615 * Enable the relevant connector on the interface module.
616 */
617 static void versatile_clcd_enable(struct clcd_fb *fb)
618 {
619 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
620 u32 val;
621
622 val = readl(sys_clcd);
623 val &= ~SYS_CLCD_MODE_MASK;
624
625 switch (fb->fb.var.green.length) {
626 case 5:
627 val |= SYS_CLCD_MODE_5551;
628 break;
629 case 6:
630 val |= SYS_CLCD_MODE_565_RLSB;
631 break;
632 case 8:
633 val |= SYS_CLCD_MODE_888;
634 break;
635 }
636
637 /*
638 * Set the MUX
639 */
640 writel(val, sys_clcd);
641
642 /*
643 * And now enable the PSUs
644 */
645 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
646 writel(val, sys_clcd);
647
648 #ifdef CONFIG_MACH_VERSATILE_AB
649 /*
650 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
651 */
652 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
653 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
654 unsigned long ctrl;
655
656 ctrl = readl(versatile_ib2_ctrl);
657 ctrl |= 0x01;
658 writel(ctrl, versatile_ib2_ctrl);
659 }
660 #endif
661 }
662
663 static unsigned long framesize = SZ_1M;
664
665 static int versatile_clcd_setup(struct clcd_fb *fb)
666 {
667 dma_addr_t dma;
668
669 fb->panel = versatile_clcd_panel();
670
671 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
672 &dma, GFP_KERNEL);
673 if (!fb->fb.screen_base) {
674 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
675 return -ENOMEM;
676 }
677
678 fb->fb.fix.smem_start = dma;
679 fb->fb.fix.smem_len = framesize;
680
681 return 0;
682 }
683
684 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
685 {
686 return dma_mmap_writecombine(&fb->dev->dev, vma,
687 fb->fb.screen_base,
688 fb->fb.fix.smem_start,
689 fb->fb.fix.smem_len);
690 }
691
692 static void versatile_clcd_remove(struct clcd_fb *fb)
693 {
694 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
695 fb->fb.screen_base, fb->fb.fix.smem_start);
696 }
697
698 static struct clcd_board clcd_plat_data = {
699 .name = "Versatile",
700 .check = clcdfb_check,
701 .decode = clcdfb_decode,
702 .disable = versatile_clcd_disable,
703 .enable = versatile_clcd_enable,
704 .setup = versatile_clcd_setup,
705 .mmap = versatile_clcd_mmap,
706 .remove = versatile_clcd_remove,
707 };
708
709 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
710 #define AACI_DMA { 0x80, 0x81 }
711 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
712 #define MMCI0_DMA { 0x84, 0 }
713 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
714 #define KMI0_DMA { 0, 0 }
715 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
716 #define KMI1_DMA { 0, 0 }
717
718 /*
719 * These devices are connected directly to the multi-layer AHB switch
720 */
721 #define SMC_IRQ { NO_IRQ, NO_IRQ }
722 #define SMC_DMA { 0, 0 }
723 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
724 #define MPMC_DMA { 0, 0 }
725 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
726 #define CLCD_DMA { 0, 0 }
727 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
728 #define DMAC_DMA { 0, 0 }
729
730 /*
731 * These devices are connected via the core APB bridge
732 */
733 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
734 #define SCTL_DMA { 0, 0 }
735 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
736 #define WATCHDOG_DMA { 0, 0 }
737 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
738 #define GPIO0_DMA { 0, 0 }
739 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
740 #define GPIO1_DMA { 0, 0 }
741 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
742 #define RTC_DMA { 0, 0 }
743
744 /*
745 * These devices are connected via the DMA APB bridge
746 */
747 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
748 #define SCI_DMA { 7, 6 }
749 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
750 #define UART0_DMA { 15, 14 }
751 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
752 #define UART1_DMA { 13, 12 }
753 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
754 #define UART2_DMA { 11, 10 }
755 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
756 #define SSP_DMA { 9, 8 }
757
758 /* FPGA Primecells */
759 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
760 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
761 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
762 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
763
764 /* DevChip Primecells */
765 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
766 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
767 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
768 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
769 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
770 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
771 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
772 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
773 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
774 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
775 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
776 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
777 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
778 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
779
780 static struct amba_device *amba_devs[] __initdata = {
781 &dmac_device,
782 &uart0_device,
783 &uart1_device,
784 &uart2_device,
785 &smc_device,
786 &mpmc_device,
787 &clcd_device,
788 &sctl_device,
789 &wdog_device,
790 &gpio0_device,
791 &gpio1_device,
792 &rtc_device,
793 &sci0_device,
794 &ssp0_device,
795 &aaci_device,
796 &mmc0_device,
797 &kmi0_device,
798 &kmi1_device,
799 };
800
801 #ifdef CONFIG_LEDS
802 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
803
804 static void versatile_leds_event(led_event_t ledevt)
805 {
806 unsigned long flags;
807 u32 val;
808
809 local_irq_save(flags);
810 val = readl(VA_LEDS_BASE);
811
812 switch (ledevt) {
813 case led_idle_start:
814 val = val & ~VERSATILE_SYS_LED0;
815 break;
816
817 case led_idle_end:
818 val = val | VERSATILE_SYS_LED0;
819 break;
820
821 case led_timer:
822 val = val ^ VERSATILE_SYS_LED1;
823 break;
824
825 case led_halted:
826 val = 0;
827 break;
828
829 default:
830 break;
831 }
832
833 writel(val, VA_LEDS_BASE);
834 local_irq_restore(flags);
835 }
836 #endif /* CONFIG_LEDS */
837
838 void __init versatile_init(void)
839 {
840 int i;
841
842 for (i = 0; i < ARRAY_SIZE(lookups); i++)
843 clkdev_add(&lookups[i]);
844
845 platform_device_register(&versatile_flash_device);
846 platform_device_register(&versatile_i2c_device);
847 platform_device_register(&smc91x_device);
848
849 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
850 struct amba_device *d = amba_devs[i];
851 amba_device_register(d, &iomem_resource);
852 }
853
854 #ifdef CONFIG_LEDS
855 leds_event = versatile_leds_event;
856 #endif
857 }
858
859 /*
860 * Where is the timer (VA)?
861 */
862 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
863 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
864 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
865 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
866 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
867
868 /*
869 * How long is the timer interval?
870 */
871 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
872 #if TIMER_INTERVAL >= 0x100000
873 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
874 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
875 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
876 #elif TIMER_INTERVAL >= 0x10000
877 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
878 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
879 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
880 #else
881 #define TIMER_RELOAD (TIMER_INTERVAL)
882 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
883 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
884 #endif
885
886 static void timer_set_mode(enum clock_event_mode mode,
887 struct clock_event_device *clk)
888 {
889 unsigned long ctrl;
890
891 switch(mode) {
892 case CLOCK_EVT_MODE_PERIODIC:
893 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
894
895 ctrl = TIMER_CTRL_PERIODIC;
896 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
897 break;
898 case CLOCK_EVT_MODE_ONESHOT:
899 /* period set, and timer enabled in 'next_event' hook */
900 ctrl = TIMER_CTRL_ONESHOT;
901 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
902 break;
903 case CLOCK_EVT_MODE_UNUSED:
904 case CLOCK_EVT_MODE_SHUTDOWN:
905 default:
906 ctrl = 0;
907 }
908
909 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
910 }
911
912 static int timer_set_next_event(unsigned long evt,
913 struct clock_event_device *unused)
914 {
915 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
916
917 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
918 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
919
920 return 0;
921 }
922
923 static struct clock_event_device timer0_clockevent = {
924 .name = "timer0",
925 .shift = 32,
926 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
927 .set_mode = timer_set_mode,
928 .set_next_event = timer_set_next_event,
929 };
930
931 /*
932 * IRQ handler for the timer
933 */
934 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
935 {
936 struct clock_event_device *evt = &timer0_clockevent;
937
938 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
939
940 evt->event_handler(evt);
941
942 return IRQ_HANDLED;
943 }
944
945 static struct irqaction versatile_timer_irq = {
946 .name = "Versatile Timer Tick",
947 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
948 .handler = versatile_timer_interrupt,
949 };
950
951 static cycle_t versatile_get_cycles(struct clocksource *cs)
952 {
953 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
954 }
955
956 static struct clocksource clocksource_versatile = {
957 .name = "timer3",
958 .rating = 200,
959 .read = versatile_get_cycles,
960 .mask = CLOCKSOURCE_MASK(32),
961 .shift = 20,
962 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
963 };
964
965 static int __init versatile_clocksource_init(void)
966 {
967 /* setup timer3 as free-running clocksource */
968 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
969 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
970 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
971 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
972 TIMER3_VA_BASE + TIMER_CTRL);
973
974 clocksource_versatile.mult =
975 clocksource_khz2mult(1000, clocksource_versatile.shift);
976 clocksource_register(&clocksource_versatile);
977
978 return 0;
979 }
980
981 /*
982 * Set up timer interrupt, and return the current time in seconds.
983 */
984 static void __init versatile_timer_init(void)
985 {
986 u32 val;
987
988 /*
989 * set clock frequency:
990 * VERSATILE_REFCLK is 32KHz
991 * VERSATILE_TIMCLK is 1MHz
992 */
993 val = readl(__io_address(VERSATILE_SCTL_BASE));
994 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
995 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
996 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
997 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
998 __io_address(VERSATILE_SCTL_BASE));
999
1000 /*
1001 * Initialise to a known state (all timers off)
1002 */
1003 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1004 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1005 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1006 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1007
1008 /*
1009 * Make irqs happen for the system timer
1010 */
1011 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
1012
1013 versatile_clocksource_init();
1014
1015 timer0_clockevent.mult =
1016 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1017 timer0_clockevent.max_delta_ns =
1018 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1019 timer0_clockevent.min_delta_ns =
1020 clockevent_delta2ns(0xf, &timer0_clockevent);
1021
1022 timer0_clockevent.cpumask = cpumask_of(0);
1023 clockevents_register_device(&timer0_clockevent);
1024 }
1025
1026 struct sys_timer versatile_timer = {
1027 .init = versatile_timer_init,
1028 };
1029
Linux kernel - Deliverables
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