2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/cnt32_to_63.h>
34 #include <asm/system.h>
35 #include <mach/hardware.h>
38 #include <asm/hardware/arm_timer.h>
39 #include <asm/hardware/icst307.h>
40 #include <asm/hardware/vic.h>
41 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/time.h>
47 #include <asm/mach/map.h>
48 #include <asm/mach/mmc.h>
54 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
57 * Setup a VA for the Versatile Vectored Interrupt Controller.
59 #define __io_address(n) __io(IO_ADDRESS(n))
60 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
61 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
63 static void sic_mask_irq(unsigned int irq
)
66 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
69 static void sic_unmask_irq(unsigned int irq
)
72 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_SET
);
75 static struct irq_chip sic_chip
= {
79 .unmask
= sic_unmask_irq
,
83 sic_handle_irq(unsigned int irq
, struct irq_desc
*desc
)
85 unsigned long status
= readl(VA_SIC_BASE
+ SIC_IRQ_STATUS
);
88 do_bad_IRQ(irq
, desc
);
93 irq
= ffs(status
) - 1;
94 status
&= ~(1 << irq
);
98 generic_handle_irq(irq
);
103 #define IRQ_MMCI0A IRQ_VICSOURCE22
104 #define IRQ_AACI IRQ_VICSOURCE24
105 #define IRQ_ETH IRQ_VICSOURCE25
106 #define PIC_MASK 0xFFD00000
108 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
109 #define IRQ_AACI IRQ_SIC_AACI
110 #define IRQ_ETH IRQ_SIC_ETH
114 void __init
versatile_init_irq(void)
118 vic_init(VA_VIC_BASE
, IRQ_VIC_START
, ~0);
120 set_irq_chained_handler(IRQ_VICSOURCE31
, sic_handle_irq
);
122 /* Do second interrupt controller */
123 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
125 for (i
= IRQ_SIC_START
; i
<= IRQ_SIC_END
; i
++) {
126 if ((PIC_MASK
& (1 << (i
- IRQ_SIC_START
))) == 0) {
127 set_irq_chip(i
, &sic_chip
);
128 set_irq_handler(i
, handle_level_irq
);
129 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
134 * Interrupts on secondary controller from 0 to 8 are routed to
136 * Interrupts from 21 to 31 are routed directly to the VIC on
137 * the corresponding number on primary controller. This is controlled
138 * by setting PIC_ENABLEx.
140 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
143 static struct map_desc versatile_io_desc
[] __initdata
= {
145 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
146 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
150 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
151 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
155 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
156 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
160 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
161 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
165 #ifdef CONFIG_MACH_VERSATILE_AB
167 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
168 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
172 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
173 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
178 #ifdef CONFIG_DEBUG_LL
180 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
181 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
188 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
189 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
193 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE
,
194 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
195 .length
= VERSATILE_PCI_BASE_SIZE
,
198 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE
,
199 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
200 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
205 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
206 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
210 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
211 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
215 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
216 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
224 void __init
versatile_map_io(void)
226 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
229 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
232 * This is the Versatile sched_clock implementation. This has
233 * a resolution of 41.7ns, and a maximum value of about 35583 days.
235 * The return value is guaranteed to be monotonic in that range as
236 * long as there is always less than 89 seconds between successive
237 * calls to this function.
239 unsigned long long sched_clock(void)
241 unsigned long long v
= cnt32_to_63(readl(VERSATILE_REFCOUNTER
));
243 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
251 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
253 static int versatile_flash_init(void)
257 val
= __raw_readl(VERSATILE_FLASHCTRL
);
258 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
259 __raw_writel(val
, VERSATILE_FLASHCTRL
);
264 static void versatile_flash_exit(void)
268 val
= __raw_readl(VERSATILE_FLASHCTRL
);
269 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
270 __raw_writel(val
, VERSATILE_FLASHCTRL
);
273 static void versatile_flash_set_vpp(int on
)
277 val
= __raw_readl(VERSATILE_FLASHCTRL
);
279 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
281 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
282 __raw_writel(val
, VERSATILE_FLASHCTRL
);
285 static struct flash_platform_data versatile_flash_data
= {
286 .map_name
= "cfi_probe",
288 .init
= versatile_flash_init
,
289 .exit
= versatile_flash_exit
,
290 .set_vpp
= versatile_flash_set_vpp
,
293 static struct resource versatile_flash_resource
= {
294 .start
= VERSATILE_FLASH_BASE
,
295 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
- 1,
296 .flags
= IORESOURCE_MEM
,
299 static struct platform_device versatile_flash_device
= {
303 .platform_data
= &versatile_flash_data
,
306 .resource
= &versatile_flash_resource
,
309 static struct resource smc91x_resources
[] = {
311 .start
= VERSATILE_ETH_BASE
,
312 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
313 .flags
= IORESOURCE_MEM
,
318 .flags
= IORESOURCE_IRQ
,
322 static struct platform_device smc91x_device
= {
325 .num_resources
= ARRAY_SIZE(smc91x_resources
),
326 .resource
= smc91x_resources
,
329 static struct resource versatile_i2c_resource
= {
330 .start
= VERSATILE_I2C_BASE
,
331 .end
= VERSATILE_I2C_BASE
+ SZ_4K
- 1,
332 .flags
= IORESOURCE_MEM
,
335 static struct platform_device versatile_i2c_device
= {
336 .name
= "versatile-i2c",
339 .resource
= &versatile_i2c_resource
,
342 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
344 unsigned int mmc_status(struct device
*dev
)
346 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
349 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
354 return readl(VERSATILE_SYSMCI
) & mask
;
357 static struct mmc_platform_data mmc0_plat_data
= {
358 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
359 .status
= mmc_status
,
365 static const struct icst307_params versatile_oscvco_params
= {
374 static void versatile_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
376 void __iomem
*sys_lock
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_LOCK_OFFSET
;
377 void __iomem
*sys_osc
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_OSCCLCD_OFFSET
;
380 val
= readl(sys_osc
) & ~0x7ffff;
381 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
383 writel(0xa05f, sys_lock
);
384 writel(val
, sys_osc
);
388 static struct clk versatile_clcd_clk
= {
390 .params
= &versatile_oscvco_params
,
391 .setvco
= versatile_oscvco_set
,
397 #define SYS_CLCD_MODE_MASK (3 << 0)
398 #define SYS_CLCD_MODE_888 (0 << 0)
399 #define SYS_CLCD_MODE_5551 (1 << 0)
400 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
401 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
402 #define SYS_CLCD_NLCDIOON (1 << 2)
403 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
404 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
405 #define SYS_CLCD_ID_MASK (0x1f << 8)
406 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
407 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
408 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
409 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
410 #define SYS_CLCD_ID_VGA (0x1f << 8)
412 static struct clcd_panel vga
= {
426 .vmode
= FB_VMODE_NONINTERLACED
,
430 .tim2
= TIM2_BCD
| TIM2_IPC
,
431 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
435 static struct clcd_panel sanyo_3_8_in
= {
437 .name
= "Sanyo QVGA",
449 .vmode
= FB_VMODE_NONINTERLACED
,
454 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
458 static struct clcd_panel sanyo_2_5_in
= {
460 .name
= "Sanyo QVGA Portrait",
471 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
472 .vmode
= FB_VMODE_NONINTERLACED
,
476 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
477 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
481 static struct clcd_panel epson_2_2_in
= {
483 .name
= "Epson QCIF",
495 .vmode
= FB_VMODE_NONINTERLACED
,
499 .tim2
= TIM2_BCD
| TIM2_IPC
,
500 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
505 * Detect which LCD panel is connected, and return the appropriate
506 * clcd_panel structure. Note: we do not have any information on
507 * the required timings for the 8.4in panel, so we presently assume
510 static struct clcd_panel
*versatile_clcd_panel(void)
512 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
513 struct clcd_panel
*panel
= &vga
;
516 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
517 if (val
== SYS_CLCD_ID_SANYO_3_8
)
518 panel
= &sanyo_3_8_in
;
519 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
520 panel
= &sanyo_2_5_in
;
521 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
522 panel
= &epson_2_2_in
;
523 else if (val
== SYS_CLCD_ID_VGA
)
526 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
535 * Disable all display connectors on the interface module.
537 static void versatile_clcd_disable(struct clcd_fb
*fb
)
539 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
542 val
= readl(sys_clcd
);
543 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
544 writel(val
, sys_clcd
);
546 #ifdef CONFIG_MACH_VERSATILE_AB
548 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
550 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
551 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
554 ctrl
= readl(versatile_ib2_ctrl
);
556 writel(ctrl
, versatile_ib2_ctrl
);
562 * Enable the relevant connector on the interface module.
564 static void versatile_clcd_enable(struct clcd_fb
*fb
)
566 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
569 val
= readl(sys_clcd
);
570 val
&= ~SYS_CLCD_MODE_MASK
;
572 switch (fb
->fb
.var
.green
.length
) {
574 val
|= SYS_CLCD_MODE_5551
;
577 val
|= SYS_CLCD_MODE_565_RLSB
;
580 val
|= SYS_CLCD_MODE_888
;
587 writel(val
, sys_clcd
);
590 * And now enable the PSUs
592 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
593 writel(val
, sys_clcd
);
595 #ifdef CONFIG_MACH_VERSATILE_AB
597 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
599 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
600 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
603 ctrl
= readl(versatile_ib2_ctrl
);
605 writel(ctrl
, versatile_ib2_ctrl
);
610 static unsigned long framesize
= SZ_1M
;
612 static int versatile_clcd_setup(struct clcd_fb
*fb
)
616 fb
->panel
= versatile_clcd_panel();
618 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
620 if (!fb
->fb
.screen_base
) {
621 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
625 fb
->fb
.fix
.smem_start
= dma
;
626 fb
->fb
.fix
.smem_len
= framesize
;
631 static int versatile_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
633 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
635 fb
->fb
.fix
.smem_start
,
636 fb
->fb
.fix
.smem_len
);
639 static void versatile_clcd_remove(struct clcd_fb
*fb
)
641 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
642 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
645 static struct clcd_board clcd_plat_data
= {
647 .check
= clcdfb_check
,
648 .decode
= clcdfb_decode
,
649 .disable
= versatile_clcd_disable
,
650 .enable
= versatile_clcd_enable
,
651 .setup
= versatile_clcd_setup
,
652 .mmap
= versatile_clcd_mmap
,
653 .remove
= versatile_clcd_remove
,
656 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
657 #define AACI_DMA { 0x80, 0x81 }
658 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
659 #define MMCI0_DMA { 0x84, 0 }
660 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
661 #define KMI0_DMA { 0, 0 }
662 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
663 #define KMI1_DMA { 0, 0 }
666 * These devices are connected directly to the multi-layer AHB switch
668 #define SMC_IRQ { NO_IRQ, NO_IRQ }
669 #define SMC_DMA { 0, 0 }
670 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
671 #define MPMC_DMA { 0, 0 }
672 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
673 #define CLCD_DMA { 0, 0 }
674 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
675 #define DMAC_DMA { 0, 0 }
678 * These devices are connected via the core APB bridge
680 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
681 #define SCTL_DMA { 0, 0 }
682 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
683 #define WATCHDOG_DMA { 0, 0 }
684 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
685 #define GPIO0_DMA { 0, 0 }
686 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
687 #define GPIO1_DMA { 0, 0 }
688 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
689 #define RTC_DMA { 0, 0 }
692 * These devices are connected via the DMA APB bridge
694 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
695 #define SCI_DMA { 7, 6 }
696 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
697 #define UART0_DMA { 15, 14 }
698 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
699 #define UART1_DMA { 13, 12 }
700 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
701 #define UART2_DMA { 11, 10 }
702 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
703 #define SSP_DMA { 9, 8 }
705 /* FPGA Primecells */
706 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
707 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
708 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
709 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
711 /* DevChip Primecells */
712 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
713 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
714 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
715 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
716 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
717 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
718 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, NULL
);
719 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, NULL
);
720 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
721 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
722 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
723 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
724 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
725 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, NULL
);
727 static struct amba_device
*amba_devs
[] __initdata
= {
749 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
751 static void versatile_leds_event(led_event_t ledevt
)
756 local_irq_save(flags
);
757 val
= readl(VA_LEDS_BASE
);
761 val
= val
& ~VERSATILE_SYS_LED0
;
765 val
= val
| VERSATILE_SYS_LED0
;
769 val
= val
^ VERSATILE_SYS_LED1
;
780 writel(val
, VA_LEDS_BASE
);
781 local_irq_restore(flags
);
783 #endif /* CONFIG_LEDS */
785 void __init
versatile_init(void)
789 clk_register(&versatile_clcd_clk
);
791 platform_device_register(&versatile_flash_device
);
792 platform_device_register(&versatile_i2c_device
);
793 platform_device_register(&smc91x_device
);
795 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
796 struct amba_device
*d
= amba_devs
[i
];
797 amba_device_register(d
, &iomem_resource
);
801 leds_event
= versatile_leds_event
;
806 * Where is the timer (VA)?
808 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
809 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
810 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
811 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
812 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
815 * How long is the timer interval?
817 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
818 #if TIMER_INTERVAL >= 0x100000
819 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
820 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
821 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
822 #elif TIMER_INTERVAL >= 0x10000
823 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
824 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
825 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
827 #define TIMER_RELOAD (TIMER_INTERVAL)
828 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
829 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
832 static void timer_set_mode(enum clock_event_mode mode
,
833 struct clock_event_device
*clk
)
838 case CLOCK_EVT_MODE_PERIODIC
:
839 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
841 ctrl
= TIMER_CTRL_PERIODIC
;
842 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
| TIMER_CTRL_ENABLE
;
844 case CLOCK_EVT_MODE_ONESHOT
:
845 /* period set, and timer enabled in 'next_event' hook */
846 ctrl
= TIMER_CTRL_ONESHOT
;
847 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
;
849 case CLOCK_EVT_MODE_UNUSED
:
850 case CLOCK_EVT_MODE_SHUTDOWN
:
855 writel(ctrl
, TIMER0_VA_BASE
+ TIMER_CTRL
);
858 static int timer_set_next_event(unsigned long evt
,
859 struct clock_event_device
*unused
)
861 unsigned long ctrl
= readl(TIMER0_VA_BASE
+ TIMER_CTRL
);
863 writel(evt
, TIMER0_VA_BASE
+ TIMER_LOAD
);
864 writel(ctrl
| TIMER_CTRL_ENABLE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
869 static struct clock_event_device timer0_clockevent
= {
872 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
873 .set_mode
= timer_set_mode
,
874 .set_next_event
= timer_set_next_event
,
878 * IRQ handler for the timer
880 static irqreturn_t
versatile_timer_interrupt(int irq
, void *dev_id
)
882 struct clock_event_device
*evt
= &timer0_clockevent
;
884 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
886 evt
->event_handler(evt
);
891 static struct irqaction versatile_timer_irq
= {
892 .name
= "Versatile Timer Tick",
893 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
894 .handler
= versatile_timer_interrupt
,
897 static cycle_t
versatile_get_cycles(void)
899 return ~readl(TIMER3_VA_BASE
+ TIMER_VALUE
);
902 static struct clocksource clocksource_versatile
= {
905 .read
= versatile_get_cycles
,
906 .mask
= CLOCKSOURCE_MASK(32),
908 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
911 static int __init
versatile_clocksource_init(void)
913 /* setup timer3 as free-running clocksource */
914 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
915 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_LOAD
);
916 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_VALUE
);
917 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
918 TIMER3_VA_BASE
+ TIMER_CTRL
);
920 clocksource_versatile
.mult
=
921 clocksource_khz2mult(1000, clocksource_versatile
.shift
);
922 clocksource_register(&clocksource_versatile
);
928 * Set up timer interrupt, and return the current time in seconds.
930 static void __init
versatile_timer_init(void)
935 * set clock frequency:
936 * VERSATILE_REFCLK is 32KHz
937 * VERSATILE_TIMCLK is 1MHz
939 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
940 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
941 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
942 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
943 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
944 __io_address(VERSATILE_SCTL_BASE
));
947 * Initialise to a known state (all timers off)
949 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
950 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
951 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
952 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
955 * Make irqs happen for the system timer
957 setup_irq(IRQ_TIMERINT0_1
, &versatile_timer_irq
);
959 versatile_clocksource_init();
961 timer0_clockevent
.mult
=
962 div_sc(1000000, NSEC_PER_SEC
, timer0_clockevent
.shift
);
963 timer0_clockevent
.max_delta_ns
=
964 clockevent_delta2ns(0xffffffff, &timer0_clockevent
);
965 timer0_clockevent
.min_delta_ns
=
966 clockevent_delta2ns(0xf, &timer0_clockevent
);
968 timer0_clockevent
.cpumask
= cpumask_of_cpu(0);
969 clockevents_register_device(&timer0_clockevent
);
972 struct sys_timer versatile_timer
= {
973 .init
= versatile_timer_init
,