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[deliverable/linux.git] / arch / arm / mach-versatile / core.c
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/amba/mmci.h>
31 #include <linux/io.h>
32
33 #include <asm/clkdev.h>
34 #include <asm/system.h>
35 #include <asm/irq.h>
36 #include <asm/leds.h>
37 #include <asm/hardware/arm_timer.h>
38 #include <asm/hardware/icst.h>
39 #include <asm/hardware/vic.h>
40 #include <asm/mach-types.h>
41
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/map.h>
47 #include <mach/clkdev.h>
48 #include <mach/hardware.h>
49 #include <mach/platform.h>
50 #include <plat/timer-sp.h>
51
52 #include "core.h"
53
54 /*
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
56 * is the (PA >> 12).
57 *
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
59 */
60 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
61 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
62
63 static void sic_mask_irq(unsigned int irq)
64 {
65 irq -= IRQ_SIC_START;
66 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
67 }
68
69 static void sic_unmask_irq(unsigned int irq)
70 {
71 irq -= IRQ_SIC_START;
72 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
73 }
74
75 static struct irq_chip sic_chip = {
76 .name = "SIC",
77 .ack = sic_mask_irq,
78 .mask = sic_mask_irq,
79 .unmask = sic_unmask_irq,
80 };
81
82 static void
83 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
84 {
85 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
86
87 if (status == 0) {
88 do_bad_IRQ(irq, desc);
89 return;
90 }
91
92 do {
93 irq = ffs(status) - 1;
94 status &= ~(1 << irq);
95
96 irq += IRQ_SIC_START;
97
98 generic_handle_irq(irq);
99 } while (status);
100 }
101
102 #if 1
103 #define IRQ_MMCI0A IRQ_VICSOURCE22
104 #define IRQ_AACI IRQ_VICSOURCE24
105 #define IRQ_ETH IRQ_VICSOURCE25
106 #define PIC_MASK 0xFFD00000
107 #else
108 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
109 #define IRQ_AACI IRQ_SIC_AACI
110 #define IRQ_ETH IRQ_SIC_ETH
111 #define PIC_MASK 0
112 #endif
113
114 void __init versatile_init_irq(void)
115 {
116 unsigned int i;
117
118 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
119
120 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
121
122 /* Do second interrupt controller */
123 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
124
125 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
126 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
127 set_irq_chip(i, &sic_chip);
128 set_irq_handler(i, handle_level_irq);
129 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
130 }
131 }
132
133 /*
134 * Interrupts on secondary controller from 0 to 8 are routed to
135 * source 31 on PIC.
136 * Interrupts from 21 to 31 are routed directly to the VIC on
137 * the corresponding number on primary controller. This is controlled
138 * by setting PIC_ENABLEx.
139 */
140 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
141 }
142
143 static struct map_desc versatile_io_desc[] __initdata = {
144 {
145 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
146 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
147 .length = SZ_4K,
148 .type = MT_DEVICE
149 }, {
150 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
151 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
152 .length = SZ_4K,
153 .type = MT_DEVICE
154 }, {
155 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
156 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
157 .length = SZ_4K,
158 .type = MT_DEVICE
159 }, {
160 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
161 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
162 .length = SZ_4K * 9,
163 .type = MT_DEVICE
164 },
165 #ifdef CONFIG_MACH_VERSATILE_AB
166 {
167 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
168 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
169 .length = SZ_4K,
170 .type = MT_DEVICE
171 }, {
172 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
173 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
174 .length = SZ_64M,
175 .type = MT_DEVICE
176 },
177 #endif
178 #ifdef CONFIG_DEBUG_LL
179 {
180 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
181 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
182 .length = SZ_4K,
183 .type = MT_DEVICE
184 },
185 #endif
186 #ifdef CONFIG_PCI
187 {
188 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
189 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
190 .length = SZ_4K,
191 .type = MT_DEVICE
192 }, {
193 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
194 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
195 .length = VERSATILE_PCI_BASE_SIZE,
196 .type = MT_DEVICE
197 }, {
198 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
199 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
200 .length = VERSATILE_PCI_CFG_BASE_SIZE,
201 .type = MT_DEVICE
202 },
203 #if 0
204 {
205 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
206 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
207 .length = SZ_16M,
208 .type = MT_DEVICE
209 }, {
210 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
211 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
212 .length = SZ_16M,
213 .type = MT_DEVICE
214 }, {
215 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
216 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
217 .length = SZ_16M,
218 .type = MT_DEVICE
219 },
220 #endif
221 #endif
222 };
223
224 void __init versatile_map_io(void)
225 {
226 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
227 }
228
229
230 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
231
232 static int versatile_flash_init(void)
233 {
234 u32 val;
235
236 val = __raw_readl(VERSATILE_FLASHCTRL);
237 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
238 __raw_writel(val, VERSATILE_FLASHCTRL);
239
240 return 0;
241 }
242
243 static void versatile_flash_exit(void)
244 {
245 u32 val;
246
247 val = __raw_readl(VERSATILE_FLASHCTRL);
248 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
249 __raw_writel(val, VERSATILE_FLASHCTRL);
250 }
251
252 static void versatile_flash_set_vpp(int on)
253 {
254 u32 val;
255
256 val = __raw_readl(VERSATILE_FLASHCTRL);
257 if (on)
258 val |= VERSATILE_FLASHPROG_FLVPPEN;
259 else
260 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261 __raw_writel(val, VERSATILE_FLASHCTRL);
262 }
263
264 static struct flash_platform_data versatile_flash_data = {
265 .map_name = "cfi_probe",
266 .width = 4,
267 .init = versatile_flash_init,
268 .exit = versatile_flash_exit,
269 .set_vpp = versatile_flash_set_vpp,
270 };
271
272 static struct resource versatile_flash_resource = {
273 .start = VERSATILE_FLASH_BASE,
274 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
275 .flags = IORESOURCE_MEM,
276 };
277
278 static struct platform_device versatile_flash_device = {
279 .name = "armflash",
280 .id = 0,
281 .dev = {
282 .platform_data = &versatile_flash_data,
283 },
284 .num_resources = 1,
285 .resource = &versatile_flash_resource,
286 };
287
288 static struct resource smc91x_resources[] = {
289 [0] = {
290 .start = VERSATILE_ETH_BASE,
291 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = IRQ_ETH,
296 .end = IRQ_ETH,
297 .flags = IORESOURCE_IRQ,
298 },
299 };
300
301 static struct platform_device smc91x_device = {
302 .name = "smc91x",
303 .id = 0,
304 .num_resources = ARRAY_SIZE(smc91x_resources),
305 .resource = smc91x_resources,
306 };
307
308 static struct resource versatile_i2c_resource = {
309 .start = VERSATILE_I2C_BASE,
310 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
311 .flags = IORESOURCE_MEM,
312 };
313
314 static struct platform_device versatile_i2c_device = {
315 .name = "versatile-i2c",
316 .id = 0,
317 .num_resources = 1,
318 .resource = &versatile_i2c_resource,
319 };
320
321 static struct i2c_board_info versatile_i2c_board_info[] = {
322 {
323 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
324 },
325 };
326
327 static int __init versatile_i2c_init(void)
328 {
329 return i2c_register_board_info(0, versatile_i2c_board_info,
330 ARRAY_SIZE(versatile_i2c_board_info));
331 }
332 arch_initcall(versatile_i2c_init);
333
334 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
335
336 unsigned int mmc_status(struct device *dev)
337 {
338 struct amba_device *adev = container_of(dev, struct amba_device, dev);
339 u32 mask;
340
341 if (adev->res.start == VERSATILE_MMCI0_BASE)
342 mask = 1;
343 else
344 mask = 2;
345
346 return readl(VERSATILE_SYSMCI) & mask;
347 }
348
349 static struct mmci_platform_data mmc0_plat_data = {
350 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
351 .status = mmc_status,
352 .gpio_wp = -1,
353 .gpio_cd = -1,
354 };
355
356 /*
357 * Clock handling
358 */
359 static const struct icst_params versatile_oscvco_params = {
360 .ref = 24000000,
361 .vco_max = ICST307_VCO_MAX,
362 .vco_min = ICST307_VCO_MIN,
363 .vd_min = 4 + 8,
364 .vd_max = 511 + 8,
365 .rd_min = 1 + 2,
366 .rd_max = 127 + 2,
367 .s2div = icst307_s2div,
368 .idx2s = icst307_idx2s,
369 };
370
371 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
372 {
373 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
374 u32 val;
375
376 val = readl(clk->vcoreg) & ~0x7ffff;
377 val |= vco.v | (vco.r << 9) | (vco.s << 16);
378
379 writel(0xa05f, sys_lock);
380 writel(val, clk->vcoreg);
381 writel(0, sys_lock);
382 }
383
384 static const struct clk_ops osc4_clk_ops = {
385 .round = icst_clk_round,
386 .set = icst_clk_set,
387 .setvco = versatile_oscvco_set,
388 };
389
390 static struct clk osc4_clk = {
391 .ops = &osc4_clk_ops,
392 .params = &versatile_oscvco_params,
393 };
394
395 /*
396 * These are fixed clocks.
397 */
398 static struct clk ref24_clk = {
399 .rate = 24000000,
400 };
401
402 static struct clk_lookup lookups[] = {
403 { /* UART0 */
404 .dev_id = "dev:f1",
405 .clk = &ref24_clk,
406 }, { /* UART1 */
407 .dev_id = "dev:f2",
408 .clk = &ref24_clk,
409 }, { /* UART2 */
410 .dev_id = "dev:f3",
411 .clk = &ref24_clk,
412 }, { /* UART3 */
413 .dev_id = "fpga:09",
414 .clk = &ref24_clk,
415 }, { /* KMI0 */
416 .dev_id = "fpga:06",
417 .clk = &ref24_clk,
418 }, { /* KMI1 */
419 .dev_id = "fpga:07",
420 .clk = &ref24_clk,
421 }, { /* MMC0 */
422 .dev_id = "fpga:05",
423 .clk = &ref24_clk,
424 }, { /* MMC1 */
425 .dev_id = "fpga:0b",
426 .clk = &ref24_clk,
427 }, { /* CLCD */
428 .dev_id = "dev:20",
429 .clk = &osc4_clk,
430 }
431 };
432
433 /*
434 * CLCD support.
435 */
436 #define SYS_CLCD_MODE_MASK (3 << 0)
437 #define SYS_CLCD_MODE_888 (0 << 0)
438 #define SYS_CLCD_MODE_5551 (1 << 0)
439 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
440 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
441 #define SYS_CLCD_NLCDIOON (1 << 2)
442 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
443 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
444 #define SYS_CLCD_ID_MASK (0x1f << 8)
445 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
446 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
447 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
448 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
449 #define SYS_CLCD_ID_VGA (0x1f << 8)
450
451 static struct clcd_panel vga = {
452 .mode = {
453 .name = "VGA",
454 .refresh = 60,
455 .xres = 640,
456 .yres = 480,
457 .pixclock = 39721,
458 .left_margin = 40,
459 .right_margin = 24,
460 .upper_margin = 32,
461 .lower_margin = 11,
462 .hsync_len = 96,
463 .vsync_len = 2,
464 .sync = 0,
465 .vmode = FB_VMODE_NONINTERLACED,
466 },
467 .width = -1,
468 .height = -1,
469 .tim2 = TIM2_BCD | TIM2_IPC,
470 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
471 .bpp = 16,
472 };
473
474 static struct clcd_panel sanyo_3_8_in = {
475 .mode = {
476 .name = "Sanyo QVGA",
477 .refresh = 116,
478 .xres = 320,
479 .yres = 240,
480 .pixclock = 100000,
481 .left_margin = 6,
482 .right_margin = 6,
483 .upper_margin = 5,
484 .lower_margin = 5,
485 .hsync_len = 6,
486 .vsync_len = 6,
487 .sync = 0,
488 .vmode = FB_VMODE_NONINTERLACED,
489 },
490 .width = -1,
491 .height = -1,
492 .tim2 = TIM2_BCD,
493 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
494 .bpp = 16,
495 };
496
497 static struct clcd_panel sanyo_2_5_in = {
498 .mode = {
499 .name = "Sanyo QVGA Portrait",
500 .refresh = 116,
501 .xres = 240,
502 .yres = 320,
503 .pixclock = 100000,
504 .left_margin = 20,
505 .right_margin = 10,
506 .upper_margin = 2,
507 .lower_margin = 2,
508 .hsync_len = 10,
509 .vsync_len = 2,
510 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
511 .vmode = FB_VMODE_NONINTERLACED,
512 },
513 .width = -1,
514 .height = -1,
515 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
516 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
517 .bpp = 16,
518 };
519
520 static struct clcd_panel epson_2_2_in = {
521 .mode = {
522 .name = "Epson QCIF",
523 .refresh = 390,
524 .xres = 176,
525 .yres = 220,
526 .pixclock = 62500,
527 .left_margin = 3,
528 .right_margin = 2,
529 .upper_margin = 1,
530 .lower_margin = 0,
531 .hsync_len = 3,
532 .vsync_len = 2,
533 .sync = 0,
534 .vmode = FB_VMODE_NONINTERLACED,
535 },
536 .width = -1,
537 .height = -1,
538 .tim2 = TIM2_BCD | TIM2_IPC,
539 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
540 .bpp = 16,
541 };
542
543 /*
544 * Detect which LCD panel is connected, and return the appropriate
545 * clcd_panel structure. Note: we do not have any information on
546 * the required timings for the 8.4in panel, so we presently assume
547 * VGA timings.
548 */
549 static struct clcd_panel *versatile_clcd_panel(void)
550 {
551 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
552 struct clcd_panel *panel = &vga;
553 u32 val;
554
555 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
556 if (val == SYS_CLCD_ID_SANYO_3_8)
557 panel = &sanyo_3_8_in;
558 else if (val == SYS_CLCD_ID_SANYO_2_5)
559 panel = &sanyo_2_5_in;
560 else if (val == SYS_CLCD_ID_EPSON_2_2)
561 panel = &epson_2_2_in;
562 else if (val == SYS_CLCD_ID_VGA)
563 panel = &vga;
564 else {
565 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
566 val);
567 panel = &vga;
568 }
569
570 return panel;
571 }
572
573 /*
574 * Disable all display connectors on the interface module.
575 */
576 static void versatile_clcd_disable(struct clcd_fb *fb)
577 {
578 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
579 u32 val;
580
581 val = readl(sys_clcd);
582 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
583 writel(val, sys_clcd);
584
585 #ifdef CONFIG_MACH_VERSATILE_AB
586 /*
587 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
588 */
589 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
590 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
591 unsigned long ctrl;
592
593 ctrl = readl(versatile_ib2_ctrl);
594 ctrl &= ~0x01;
595 writel(ctrl, versatile_ib2_ctrl);
596 }
597 #endif
598 }
599
600 /*
601 * Enable the relevant connector on the interface module.
602 */
603 static void versatile_clcd_enable(struct clcd_fb *fb)
604 {
605 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
606 u32 val;
607
608 val = readl(sys_clcd);
609 val &= ~SYS_CLCD_MODE_MASK;
610
611 switch (fb->fb.var.green.length) {
612 case 5:
613 val |= SYS_CLCD_MODE_5551;
614 break;
615 case 6:
616 val |= SYS_CLCD_MODE_565_RLSB;
617 break;
618 case 8:
619 val |= SYS_CLCD_MODE_888;
620 break;
621 }
622
623 /*
624 * Set the MUX
625 */
626 writel(val, sys_clcd);
627
628 /*
629 * And now enable the PSUs
630 */
631 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
632 writel(val, sys_clcd);
633
634 #ifdef CONFIG_MACH_VERSATILE_AB
635 /*
636 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
637 */
638 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
639 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
640 unsigned long ctrl;
641
642 ctrl = readl(versatile_ib2_ctrl);
643 ctrl |= 0x01;
644 writel(ctrl, versatile_ib2_ctrl);
645 }
646 #endif
647 }
648
649 static unsigned long framesize = SZ_1M;
650
651 static int versatile_clcd_setup(struct clcd_fb *fb)
652 {
653 dma_addr_t dma;
654
655 fb->panel = versatile_clcd_panel();
656
657 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
658 &dma, GFP_KERNEL);
659 if (!fb->fb.screen_base) {
660 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
661 return -ENOMEM;
662 }
663
664 fb->fb.fix.smem_start = dma;
665 fb->fb.fix.smem_len = framesize;
666
667 return 0;
668 }
669
670 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
671 {
672 return dma_mmap_writecombine(&fb->dev->dev, vma,
673 fb->fb.screen_base,
674 fb->fb.fix.smem_start,
675 fb->fb.fix.smem_len);
676 }
677
678 static void versatile_clcd_remove(struct clcd_fb *fb)
679 {
680 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
681 fb->fb.screen_base, fb->fb.fix.smem_start);
682 }
683
684 static struct clcd_board clcd_plat_data = {
685 .name = "Versatile",
686 .check = clcdfb_check,
687 .decode = clcdfb_decode,
688 .disable = versatile_clcd_disable,
689 .enable = versatile_clcd_enable,
690 .setup = versatile_clcd_setup,
691 .mmap = versatile_clcd_mmap,
692 .remove = versatile_clcd_remove,
693 };
694
695 static struct pl061_platform_data gpio0_plat_data = {
696 .gpio_base = 0,
697 .irq_base = IRQ_GPIO0_START,
698 };
699
700 static struct pl061_platform_data gpio1_plat_data = {
701 .gpio_base = 8,
702 .irq_base = IRQ_GPIO1_START,
703 };
704
705 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
706 #define AACI_DMA { 0x80, 0x81 }
707 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
708 #define MMCI0_DMA { 0x84, 0 }
709 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
710 #define KMI0_DMA { 0, 0 }
711 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
712 #define KMI1_DMA { 0, 0 }
713
714 /*
715 * These devices are connected directly to the multi-layer AHB switch
716 */
717 #define SMC_IRQ { NO_IRQ, NO_IRQ }
718 #define SMC_DMA { 0, 0 }
719 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
720 #define MPMC_DMA { 0, 0 }
721 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
722 #define CLCD_DMA { 0, 0 }
723 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
724 #define DMAC_DMA { 0, 0 }
725
726 /*
727 * These devices are connected via the core APB bridge
728 */
729 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
730 #define SCTL_DMA { 0, 0 }
731 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
732 #define WATCHDOG_DMA { 0, 0 }
733 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
734 #define GPIO0_DMA { 0, 0 }
735 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
736 #define GPIO1_DMA { 0, 0 }
737 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
738 #define RTC_DMA { 0, 0 }
739
740 /*
741 * These devices are connected via the DMA APB bridge
742 */
743 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
744 #define SCI_DMA { 7, 6 }
745 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
746 #define UART0_DMA { 15, 14 }
747 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
748 #define UART1_DMA { 13, 12 }
749 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
750 #define UART2_DMA { 11, 10 }
751 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
752 #define SSP_DMA { 9, 8 }
753
754 /* FPGA Primecells */
755 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
756 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
757 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
758 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
759
760 /* DevChip Primecells */
761 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
762 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
763 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
764 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
765 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
766 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
767 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
768 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
769 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
770 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
771 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
772 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
773 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
774 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
775
776 static struct amba_device *amba_devs[] __initdata = {
777 &dmac_device,
778 &uart0_device,
779 &uart1_device,
780 &uart2_device,
781 &smc_device,
782 &mpmc_device,
783 &clcd_device,
784 &sctl_device,
785 &wdog_device,
786 &gpio0_device,
787 &gpio1_device,
788 &rtc_device,
789 &sci0_device,
790 &ssp0_device,
791 &aaci_device,
792 &mmc0_device,
793 &kmi0_device,
794 &kmi1_device,
795 };
796
797 #ifdef CONFIG_LEDS
798 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
799
800 static void versatile_leds_event(led_event_t ledevt)
801 {
802 unsigned long flags;
803 u32 val;
804
805 local_irq_save(flags);
806 val = readl(VA_LEDS_BASE);
807
808 switch (ledevt) {
809 case led_idle_start:
810 val = val & ~VERSATILE_SYS_LED0;
811 break;
812
813 case led_idle_end:
814 val = val | VERSATILE_SYS_LED0;
815 break;
816
817 case led_timer:
818 val = val ^ VERSATILE_SYS_LED1;
819 break;
820
821 case led_halted:
822 val = 0;
823 break;
824
825 default:
826 break;
827 }
828
829 writel(val, VA_LEDS_BASE);
830 local_irq_restore(flags);
831 }
832 #endif /* CONFIG_LEDS */
833
834 void __init versatile_init(void)
835 {
836 int i;
837
838 osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
839
840 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
841
842 platform_device_register(&versatile_flash_device);
843 platform_device_register(&versatile_i2c_device);
844 platform_device_register(&smc91x_device);
845
846 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
847 struct amba_device *d = amba_devs[i];
848 amba_device_register(d, &iomem_resource);
849 }
850
851 #ifdef CONFIG_LEDS
852 leds_event = versatile_leds_event;
853 #endif
854 }
855
856 /*
857 * Where is the timer (VA)?
858 */
859 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
860 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
861 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
862 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
863
864 /*
865 * Set up timer interrupt, and return the current time in seconds.
866 */
867 static void __init versatile_timer_init(void)
868 {
869 u32 val;
870
871 /*
872 * set clock frequency:
873 * VERSATILE_REFCLK is 32KHz
874 * VERSATILE_TIMCLK is 1MHz
875 */
876 val = readl(__io_address(VERSATILE_SCTL_BASE));
877 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
878 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
879 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
880 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
881 __io_address(VERSATILE_SCTL_BASE));
882
883 /*
884 * Initialise to a known state (all timers off)
885 */
886 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
887 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
888 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
889 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
890
891 sp804_clocksource_init(TIMER3_VA_BASE);
892 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
893 }
894
895 struct sys_timer versatile_timer = {
896 .init = versatile_timer_init,
897 };
898
Linux kernel - Deliverables
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