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Merge branch 'for-chris' of git://git.jan-o-sch.net/btrfs-unstable into for-linus
[deliverable/linux.git] / arch / arm / mach-versatile / core.c
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/io.h>
35 #include <linux/gfp.h>
36 #include <linux/clkdev.h>
37 #include <linux/mtd/physmap.h>
38
39 #include <asm/irq.h>
40 #include <asm/leds.h>
41 #include <asm/hardware/arm_timer.h>
42 #include <asm/hardware/icst.h>
43 #include <asm/hardware/vic.h>
44 #include <asm/mach-types.h>
45
46 #include <asm/mach/arch.h>
47 #include <asm/mach/irq.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/map.h>
50 #include <mach/hardware.h>
51 #include <mach/platform.h>
52 #include <asm/hardware/timer-sp.h>
53
54 #include <plat/clcd.h>
55 #include <plat/fpga-irq.h>
56 #include <plat/sched_clock.h>
57
58 #include "core.h"
59
60 /*
61 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
62 * is the (PA >> 12).
63 *
64 * Setup a VA for the Versatile Vectored Interrupt Controller.
65 */
66 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
67 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
68
69 static struct fpga_irq_data sic_irq = {
70 .base = VA_SIC_BASE,
71 .irq_start = IRQ_SIC_START,
72 .chip.name = "SIC",
73 };
74
75 #if 1
76 #define IRQ_MMCI0A IRQ_VICSOURCE22
77 #define IRQ_AACI IRQ_VICSOURCE24
78 #define IRQ_ETH IRQ_VICSOURCE25
79 #define PIC_MASK 0xFFD00000
80 #else
81 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
82 #define IRQ_AACI IRQ_SIC_AACI
83 #define IRQ_ETH IRQ_SIC_ETH
84 #define PIC_MASK 0
85 #endif
86
87 /* Lookup table for finding a DT node that represents the vic instance */
88 static const struct of_device_id vic_of_match[] __initconst = {
89 { .compatible = "arm,versatile-vic", },
90 {}
91 };
92
93 static const struct of_device_id sic_of_match[] __initconst = {
94 { .compatible = "arm,versatile-sic", },
95 {}
96 };
97
98 void __init versatile_init_irq(void)
99 {
100 struct device_node *np;
101
102 np = of_find_matching_node_by_address(NULL, vic_of_match,
103 VERSATILE_VIC_BASE);
104 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
105
106 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
107
108 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
109 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
110
111 /*
112 * Interrupts on secondary controller from 0 to 8 are routed to
113 * source 31 on PIC.
114 * Interrupts from 21 to 31 are routed directly to the VIC on
115 * the corresponding number on primary controller. This is controlled
116 * by setting PIC_ENABLEx.
117 */
118 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
119 }
120
121 static struct map_desc versatile_io_desc[] __initdata = {
122 {
123 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
124 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
125 .length = SZ_4K,
126 .type = MT_DEVICE
127 }, {
128 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
129 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
130 .length = SZ_4K,
131 .type = MT_DEVICE
132 }, {
133 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
134 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
135 .length = SZ_4K,
136 .type = MT_DEVICE
137 }, {
138 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
139 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
140 .length = SZ_4K * 9,
141 .type = MT_DEVICE
142 },
143 #ifdef CONFIG_MACH_VERSATILE_AB
144 {
145 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
146 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
147 .length = SZ_64M,
148 .type = MT_DEVICE
149 },
150 #endif
151 #ifdef CONFIG_DEBUG_LL
152 {
153 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
154 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
155 .length = SZ_4K,
156 .type = MT_DEVICE
157 },
158 #endif
159 #ifdef CONFIG_PCI
160 {
161 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
162 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
163 .length = SZ_4K,
164 .type = MT_DEVICE
165 }, {
166 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
167 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
168 .length = VERSATILE_PCI_BASE_SIZE,
169 .type = MT_DEVICE
170 }, {
171 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
172 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
173 .length = VERSATILE_PCI_CFG_BASE_SIZE,
174 .type = MT_DEVICE
175 },
176 #if 0
177 {
178 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
179 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
180 .length = SZ_16M,
181 .type = MT_DEVICE
182 }, {
183 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
184 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
185 .length = SZ_16M,
186 .type = MT_DEVICE
187 }, {
188 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
189 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
190 .length = SZ_16M,
191 .type = MT_DEVICE
192 },
193 #endif
194 #endif
195 };
196
197 void __init versatile_map_io(void)
198 {
199 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
200 }
201
202
203 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
204
205 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
206 {
207 u32 val;
208
209 val = __raw_readl(VERSATILE_FLASHCTRL);
210 if (on)
211 val |= VERSATILE_FLASHPROG_FLVPPEN;
212 else
213 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
214 __raw_writel(val, VERSATILE_FLASHCTRL);
215 }
216
217 static struct physmap_flash_data versatile_flash_data = {
218 .width = 4,
219 .set_vpp = versatile_flash_set_vpp,
220 };
221
222 static struct resource versatile_flash_resource = {
223 .start = VERSATILE_FLASH_BASE,
224 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
225 .flags = IORESOURCE_MEM,
226 };
227
228 static struct platform_device versatile_flash_device = {
229 .name = "physmap-flash",
230 .id = 0,
231 .dev = {
232 .platform_data = &versatile_flash_data,
233 },
234 .num_resources = 1,
235 .resource = &versatile_flash_resource,
236 };
237
238 static struct resource smc91x_resources[] = {
239 [0] = {
240 .start = VERSATILE_ETH_BASE,
241 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = IRQ_ETH,
246 .end = IRQ_ETH,
247 .flags = IORESOURCE_IRQ,
248 },
249 };
250
251 static struct platform_device smc91x_device = {
252 .name = "smc91x",
253 .id = 0,
254 .num_resources = ARRAY_SIZE(smc91x_resources),
255 .resource = smc91x_resources,
256 };
257
258 static struct resource versatile_i2c_resource = {
259 .start = VERSATILE_I2C_BASE,
260 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
261 .flags = IORESOURCE_MEM,
262 };
263
264 static struct platform_device versatile_i2c_device = {
265 .name = "versatile-i2c",
266 .id = 0,
267 .num_resources = 1,
268 .resource = &versatile_i2c_resource,
269 };
270
271 static struct i2c_board_info versatile_i2c_board_info[] = {
272 {
273 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
274 },
275 };
276
277 static int __init versatile_i2c_init(void)
278 {
279 return i2c_register_board_info(0, versatile_i2c_board_info,
280 ARRAY_SIZE(versatile_i2c_board_info));
281 }
282 arch_initcall(versatile_i2c_init);
283
284 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
285
286 unsigned int mmc_status(struct device *dev)
287 {
288 struct amba_device *adev = container_of(dev, struct amba_device, dev);
289 u32 mask;
290
291 if (adev->res.start == VERSATILE_MMCI0_BASE)
292 mask = 1;
293 else
294 mask = 2;
295
296 return readl(VERSATILE_SYSMCI) & mask;
297 }
298
299 static struct mmci_platform_data mmc0_plat_data = {
300 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
301 .status = mmc_status,
302 .gpio_wp = -1,
303 .gpio_cd = -1,
304 };
305
306 static struct resource char_lcd_resources[] = {
307 {
308 .start = VERSATILE_CHAR_LCD_BASE,
309 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
310 .flags = IORESOURCE_MEM,
311 },
312 };
313
314 static struct platform_device char_lcd_device = {
315 .name = "arm-charlcd",
316 .id = -1,
317 .num_resources = ARRAY_SIZE(char_lcd_resources),
318 .resource = char_lcd_resources,
319 };
320
321 /*
322 * Clock handling
323 */
324 static const struct icst_params versatile_oscvco_params = {
325 .ref = 24000000,
326 .vco_max = ICST307_VCO_MAX,
327 .vco_min = ICST307_VCO_MIN,
328 .vd_min = 4 + 8,
329 .vd_max = 511 + 8,
330 .rd_min = 1 + 2,
331 .rd_max = 127 + 2,
332 .s2div = icst307_s2div,
333 .idx2s = icst307_idx2s,
334 };
335
336 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
337 {
338 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
339 u32 val;
340
341 val = readl(clk->vcoreg) & ~0x7ffff;
342 val |= vco.v | (vco.r << 9) | (vco.s << 16);
343
344 writel(0xa05f, sys_lock);
345 writel(val, clk->vcoreg);
346 writel(0, sys_lock);
347 }
348
349 static const struct clk_ops osc4_clk_ops = {
350 .round = icst_clk_round,
351 .set = icst_clk_set,
352 .setvco = versatile_oscvco_set,
353 };
354
355 static struct clk osc4_clk = {
356 .ops = &osc4_clk_ops,
357 .params = &versatile_oscvco_params,
358 };
359
360 /*
361 * These are fixed clocks.
362 */
363 static struct clk ref24_clk = {
364 .rate = 24000000,
365 };
366
367 static struct clk sp804_clk = {
368 .rate = 1000000,
369 };
370
371 static struct clk dummy_apb_pclk;
372
373 static struct clk_lookup lookups[] = {
374 { /* AMBA bus clock */
375 .con_id = "apb_pclk",
376 .clk = &dummy_apb_pclk,
377 }, { /* UART0 */
378 .dev_id = "dev:f1",
379 .clk = &ref24_clk,
380 }, { /* UART1 */
381 .dev_id = "dev:f2",
382 .clk = &ref24_clk,
383 }, { /* UART2 */
384 .dev_id = "dev:f3",
385 .clk = &ref24_clk,
386 }, { /* UART3 */
387 .dev_id = "fpga:09",
388 .clk = &ref24_clk,
389 }, { /* KMI0 */
390 .dev_id = "fpga:06",
391 .clk = &ref24_clk,
392 }, { /* KMI1 */
393 .dev_id = "fpga:07",
394 .clk = &ref24_clk,
395 }, { /* MMC0 */
396 .dev_id = "fpga:05",
397 .clk = &ref24_clk,
398 }, { /* MMC1 */
399 .dev_id = "fpga:0b",
400 .clk = &ref24_clk,
401 }, { /* SSP */
402 .dev_id = "dev:f4",
403 .clk = &ref24_clk,
404 }, { /* CLCD */
405 .dev_id = "dev:20",
406 .clk = &osc4_clk,
407 }, { /* SP804 timers */
408 .dev_id = "sp804",
409 .clk = &sp804_clk,
410 },
411 };
412
413 /*
414 * CLCD support.
415 */
416 #define SYS_CLCD_MODE_MASK (3 << 0)
417 #define SYS_CLCD_MODE_888 (0 << 0)
418 #define SYS_CLCD_MODE_5551 (1 << 0)
419 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
420 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
421 #define SYS_CLCD_NLCDIOON (1 << 2)
422 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
423 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
424 #define SYS_CLCD_ID_MASK (0x1f << 8)
425 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
426 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
427 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
428 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
429 #define SYS_CLCD_ID_VGA (0x1f << 8)
430
431 static bool is_sanyo_2_5_lcd;
432
433 /*
434 * Disable all display connectors on the interface module.
435 */
436 static void versatile_clcd_disable(struct clcd_fb *fb)
437 {
438 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
439 u32 val;
440
441 val = readl(sys_clcd);
442 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
443 writel(val, sys_clcd);
444
445 #ifdef CONFIG_MACH_VERSATILE_AB
446 /*
447 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
448 */
449 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
450 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
451 unsigned long ctrl;
452
453 ctrl = readl(versatile_ib2_ctrl);
454 ctrl &= ~0x01;
455 writel(ctrl, versatile_ib2_ctrl);
456 }
457 #endif
458 }
459
460 /*
461 * Enable the relevant connector on the interface module.
462 */
463 static void versatile_clcd_enable(struct clcd_fb *fb)
464 {
465 struct fb_var_screeninfo *var = &fb->fb.var;
466 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
467 u32 val;
468
469 val = readl(sys_clcd);
470 val &= ~SYS_CLCD_MODE_MASK;
471
472 switch (var->green.length) {
473 case 5:
474 val |= SYS_CLCD_MODE_5551;
475 break;
476 case 6:
477 if (var->red.offset == 0)
478 val |= SYS_CLCD_MODE_565_RLSB;
479 else
480 val |= SYS_CLCD_MODE_565_BLSB;
481 break;
482 case 8:
483 val |= SYS_CLCD_MODE_888;
484 break;
485 }
486
487 /*
488 * Set the MUX
489 */
490 writel(val, sys_clcd);
491
492 /*
493 * And now enable the PSUs
494 */
495 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
496 writel(val, sys_clcd);
497
498 #ifdef CONFIG_MACH_VERSATILE_AB
499 /*
500 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
501 */
502 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
503 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
504 unsigned long ctrl;
505
506 ctrl = readl(versatile_ib2_ctrl);
507 ctrl |= 0x01;
508 writel(ctrl, versatile_ib2_ctrl);
509 }
510 #endif
511 }
512
513 /*
514 * Detect which LCD panel is connected, and return the appropriate
515 * clcd_panel structure. Note: we do not have any information on
516 * the required timings for the 8.4in panel, so we presently assume
517 * VGA timings.
518 */
519 static int versatile_clcd_setup(struct clcd_fb *fb)
520 {
521 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
522 const char *panel_name;
523 u32 val;
524
525 is_sanyo_2_5_lcd = false;
526
527 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
528 if (val == SYS_CLCD_ID_SANYO_3_8)
529 panel_name = "Sanyo TM38QV67A02A";
530 else if (val == SYS_CLCD_ID_SANYO_2_5) {
531 panel_name = "Sanyo QVGA Portrait";
532 is_sanyo_2_5_lcd = true;
533 } else if (val == SYS_CLCD_ID_EPSON_2_2)
534 panel_name = "Epson L2F50113T00";
535 else if (val == SYS_CLCD_ID_VGA)
536 panel_name = "VGA";
537 else {
538 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
539 val);
540 panel_name = "VGA";
541 }
542
543 fb->panel = versatile_clcd_get_panel(panel_name);
544 if (!fb->panel)
545 return -EINVAL;
546
547 return versatile_clcd_setup_dma(fb, SZ_1M);
548 }
549
550 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
551 {
552 clcdfb_decode(fb, regs);
553
554 /* Always clear BGR for RGB565: we do the routing externally */
555 if (fb->fb.var.green.length == 6)
556 regs->cntl &= ~CNTL_BGR;
557 }
558
559 static struct clcd_board clcd_plat_data = {
560 .name = "Versatile",
561 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
562 .check = clcdfb_check,
563 .decode = versatile_clcd_decode,
564 .disable = versatile_clcd_disable,
565 .enable = versatile_clcd_enable,
566 .setup = versatile_clcd_setup,
567 .mmap = versatile_clcd_mmap_dma,
568 .remove = versatile_clcd_remove_dma,
569 };
570
571 static struct pl061_platform_data gpio0_plat_data = {
572 .gpio_base = 0,
573 .irq_base = IRQ_GPIO0_START,
574 };
575
576 static struct pl061_platform_data gpio1_plat_data = {
577 .gpio_base = 8,
578 .irq_base = IRQ_GPIO1_START,
579 };
580
581 static struct pl022_ssp_controller ssp0_plat_data = {
582 .bus_id = 0,
583 .enable_dma = 0,
584 .num_chipselect = 1,
585 };
586
587 #define AACI_IRQ { IRQ_AACI }
588 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
589 #define KMI0_IRQ { IRQ_SIC_KMI0 }
590 #define KMI1_IRQ { IRQ_SIC_KMI1 }
591
592 /*
593 * These devices are connected directly to the multi-layer AHB switch
594 */
595 #define SMC_IRQ { }
596 #define MPMC_IRQ { }
597 #define CLCD_IRQ { IRQ_CLCDINT }
598 #define DMAC_IRQ { IRQ_DMAINT }
599
600 /*
601 * These devices are connected via the core APB bridge
602 */
603 #define SCTL_IRQ { }
604 #define WATCHDOG_IRQ { IRQ_WDOGINT }
605 #define GPIO0_IRQ { IRQ_GPIOINT0 }
606 #define GPIO1_IRQ { IRQ_GPIOINT1 }
607 #define RTC_IRQ { IRQ_RTCINT }
608
609 /*
610 * These devices are connected via the DMA APB bridge
611 */
612 #define SCI_IRQ { IRQ_SCIINT }
613 #define UART0_IRQ { IRQ_UARTINT0 }
614 #define UART1_IRQ { IRQ_UARTINT1 }
615 #define UART2_IRQ { IRQ_UARTINT2 }
616 #define SSP_IRQ { IRQ_SSPINT }
617
618 /* FPGA Primecells */
619 APB_DEVICE(aaci, "fpga:04", AACI, NULL);
620 APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
621 APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
622 APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
623
624 /* DevChip Primecells */
625 AHB_DEVICE(smc, "dev:00", SMC, NULL);
626 AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
627 AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
628 AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
629 APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
630 APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
631 APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
632 APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
633 APB_DEVICE(rtc, "dev:e8", RTC, NULL);
634 APB_DEVICE(sci0, "dev:f0", SCI, NULL);
635 APB_DEVICE(uart0, "dev:f1", UART0, NULL);
636 APB_DEVICE(uart1, "dev:f2", UART1, NULL);
637 APB_DEVICE(uart2, "dev:f3", UART2, NULL);
638 APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
639
640 static struct amba_device *amba_devs[] __initdata = {
641 &dmac_device,
642 &uart0_device,
643 &uart1_device,
644 &uart2_device,
645 &smc_device,
646 &mpmc_device,
647 &clcd_device,
648 &sctl_device,
649 &wdog_device,
650 &gpio0_device,
651 &gpio1_device,
652 &rtc_device,
653 &sci0_device,
654 &ssp0_device,
655 &aaci_device,
656 &mmc0_device,
657 &kmi0_device,
658 &kmi1_device,
659 };
660
661 #ifdef CONFIG_OF
662 /*
663 * Lookup table for attaching a specific name and platform_data pointer to
664 * devices as they get created by of_platform_populate(). Ideally this table
665 * would not exist, but the current clock implementation depends on some devices
666 * having a specific name.
667 */
668 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
674
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
680
681 #if 0
682 /*
683 * These entries are unnecessary because no clocks referencing
684 * them. I've left them in for now as place holders in case
685 * any of them need to be added back, but they should be
686 * removed before actually committing this patch. --gcl
687 */
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
691 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
693
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
696 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
700 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
701 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
702 #endif
703 {}
704 };
705 #endif
706
707 #ifdef CONFIG_LEDS
708 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
709
710 static void versatile_leds_event(led_event_t ledevt)
711 {
712 unsigned long flags;
713 u32 val;
714
715 local_irq_save(flags);
716 val = readl(VA_LEDS_BASE);
717
718 switch (ledevt) {
719 case led_idle_start:
720 val = val & ~VERSATILE_SYS_LED0;
721 break;
722
723 case led_idle_end:
724 val = val | VERSATILE_SYS_LED0;
725 break;
726
727 case led_timer:
728 val = val ^ VERSATILE_SYS_LED1;
729 break;
730
731 case led_halted:
732 val = 0;
733 break;
734
735 default:
736 break;
737 }
738
739 writel(val, VA_LEDS_BASE);
740 local_irq_restore(flags);
741 }
742 #endif /* CONFIG_LEDS */
743
744 void versatile_restart(char mode, const char *cmd)
745 {
746 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
747 u32 val;
748
749 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
750 val |= 0x105;
751
752 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
753 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
754 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
755 }
756
757 /* Early initializations */
758 void __init versatile_init_early(void)
759 {
760 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
761
762 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
763 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
764
765 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
766 }
767
768 void __init versatile_init(void)
769 {
770 int i;
771
772 platform_device_register(&versatile_flash_device);
773 platform_device_register(&versatile_i2c_device);
774 platform_device_register(&smc91x_device);
775 platform_device_register(&char_lcd_device);
776
777 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
778 struct amba_device *d = amba_devs[i];
779 amba_device_register(d, &iomem_resource);
780 }
781
782 #ifdef CONFIG_LEDS
783 leds_event = versatile_leds_event;
784 #endif
785 }
786
787 /*
788 * Where is the timer (VA)?
789 */
790 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
791 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
792 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
793 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
794
795 /*
796 * Set up timer interrupt, and return the current time in seconds.
797 */
798 static void __init versatile_timer_init(void)
799 {
800 u32 val;
801
802 /*
803 * set clock frequency:
804 * VERSATILE_REFCLK is 32KHz
805 * VERSATILE_TIMCLK is 1MHz
806 */
807 val = readl(__io_address(VERSATILE_SCTL_BASE));
808 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
809 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
810 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
811 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
812 __io_address(VERSATILE_SCTL_BASE));
813
814 /*
815 * Initialise to a known state (all timers off)
816 */
817 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
818 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
819 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
820 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
821
822 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
823 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
824 }
825
826 struct sys_timer versatile_timer = {
827 .init = versatile_timer_init,
828 };
829
Linux kernel - Deliverables
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