2 * linux/arch/arm/mach-versatile/pci.c
4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
5 * You can redistribute and/or modify this software under the terms of version 2
6 * of the GNU General Public License as published by the Free Software Foundation.
7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
12 * ARM Versatile PCI driver.
14 * 14/04/2005 Initial version, colin.king@philips.com
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/init.h>
25 #include <mach/hardware.h>
27 #include <asm/mach/pci.h>
30 * these spaces are mapped using the following base registers:
32 * Usage Local Bus Memory Base/Map registers used
34 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
35 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
36 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
37 * Cfg 42000000 - 42FFFFFF PCI config
40 #define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
41 #define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
42 #define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
43 #define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
44 #define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
45 #define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
46 #define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
47 #define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
48 #define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
50 #define DEVICE_ID_OFFSET 0x00
51 #define CSR_OFFSET 0x04
52 #define CLASS_ID_OFFSET 0x08
54 #define VP_PCI_DEVICE_ID 0x030010ee
55 #define VP_PCI_CLASS_ID 0x0b400000
57 static unsigned long pci_slot_ignore
= 0;
59 static int __init
versatile_pci_slot_ignore(char *str
)
64 while ((retval
= get_option(&str
,&slot
))) {
65 if ((slot
< 0) || (slot
> 31)) {
66 printk("Illegal slot value: %d\n",slot
);
68 pci_slot_ignore
|= (1 << slot
);
74 __setup("pci_slot_ignore=", versatile_pci_slot_ignore
);
77 static void __iomem
*__pci_addr(struct pci_bus
*bus
,
78 unsigned int devfn
, int offset
)
80 unsigned int busnr
= bus
->number
;
83 * Trap out illegal values
92 return VERSATILE_PCI_CFG_VIRT_BASE
+ ((busnr
<< 16) |
93 (PCI_SLOT(devfn
) << 11) | (PCI_FUNC(devfn
) << 8) | offset
);
96 static int versatile_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
99 void __iomem
*addr
= __pci_addr(bus
, devfn
, where
& ~3);
101 int slot
= PCI_SLOT(devfn
);
103 if (pci_slot_ignore
& (1 << slot
)) {
104 /* Ignore this slot */
118 v
= __raw_readl(addr
);
119 if (where
& 2) v
>>= 16;
120 if (where
& 1) v
>>= 8;
125 v
= __raw_readl(addr
);
126 if (where
& 2) v
>>= 16;
131 v
= __raw_readl(addr
);
137 return PCIBIOS_SUCCESSFUL
;
140 static int versatile_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
143 void __iomem
*addr
= __pci_addr(bus
, devfn
, where
);
144 int slot
= PCI_SLOT(devfn
);
146 if (pci_slot_ignore
& (1 << slot
)) {
147 return PCIBIOS_SUCCESSFUL
;
152 __raw_writeb((u8
)val
, addr
);
156 __raw_writew((u16
)val
, addr
);
160 __raw_writel(val
, addr
);
164 return PCIBIOS_SUCCESSFUL
;
167 static struct pci_ops pci_versatile_ops
= {
168 .read
= versatile_read_config
,
169 .write
= versatile_write_config
,
172 static struct resource io_port
= {
175 .end
= IO_SPACE_LIMIT
,
176 .flags
= IORESOURCE_IO
,
179 static struct resource io_mem
= {
180 .name
= "PCI I/O space",
181 .start
= VERSATILE_PCI_MEM_BASE0
,
182 .end
= VERSATILE_PCI_MEM_BASE0
+VERSATILE_PCI_MEM_BASE0_SIZE
-1,
183 .flags
= IORESOURCE_MEM
,
186 static struct resource non_mem
= {
187 .name
= "PCI non-prefetchable",
188 .start
= VERSATILE_PCI_MEM_BASE1
,
189 .end
= VERSATILE_PCI_MEM_BASE1
+VERSATILE_PCI_MEM_BASE1_SIZE
-1,
190 .flags
= IORESOURCE_MEM
,
193 static struct resource pre_mem
= {
194 .name
= "PCI prefetchable",
195 .start
= VERSATILE_PCI_MEM_BASE2
,
196 .end
= VERSATILE_PCI_MEM_BASE2
+VERSATILE_PCI_MEM_BASE2_SIZE
-1,
197 .flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
,
200 static int __init
pci_versatile_setup_resources(struct pci_sys_data
*sys
)
204 ret
= request_resource(&iomem_resource
, &io_mem
);
206 printk(KERN_ERR
"PCI: unable to allocate I/O "
207 "memory region (%d)\n", ret
);
210 ret
= request_resource(&ioport_resource
, &io_port
);
212 printk(KERN_ERR
"PCI: unable to allocate I/O "
213 "port region (%d)\n", ret
);
216 ret
= request_resource(&iomem_resource
, &non_mem
);
218 printk(KERN_ERR
"PCI: unable to allocate non-prefetchable "
219 "memory region (%d)\n", ret
);
222 ret
= request_resource(&iomem_resource
, &pre_mem
);
224 printk(KERN_ERR
"PCI: unable to allocate prefetchable "
225 "memory region (%d)\n", ret
);
226 goto release_non_mem
;
230 * the IO resource for this bus
231 * the mem resource for this bus
232 * the prefetch mem resource for this bus
234 pci_add_resource_offset(&sys
->resources
, &io_port
, sys
->io_offset
);
235 pci_add_resource_offset(&sys
->resources
, &non_mem
, sys
->mem_offset
);
236 pci_add_resource_offset(&sys
->resources
, &pre_mem
, sys
->mem_offset
);
241 release_resource(&non_mem
);
243 release_resource(&io_mem
);
248 int __init
pci_versatile_setup(int nr
, struct pci_sys_data
*sys
)
254 void __iomem
*local_pci_cfg_base
;
256 val
= __raw_readl(SYS_PCICTL
);
258 printk("Not plugged into PCI backplane!\n");
266 ret
= pci_versatile_setup_resources(sys
);
268 printk("pci_versatile_setup: resources... oops?\n");
272 printk("pci_versatile_setup: resources... nr == 0??\n");
277 * We need to discover the PCI core first to configure itself
278 * before the main PCI probing is performed
281 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE
+(i
<<11)+DEVICE_ID_OFFSET
) == VP_PCI_DEVICE_ID
) &&
282 (__raw_readl(VERSATILE_PCI_VIRT_BASE
+(i
<<11)+CLASS_ID_OFFSET
) == VP_PCI_CLASS_ID
)) {
288 printk("Cannot find PCI core!\n");
293 printk("PCI core found (slot %d)\n",myslot
);
295 __raw_writel(myslot
, PCI_SELFID
);
296 local_pci_cfg_base
= VERSATILE_PCI_CFG_VIRT_BASE
+ (myslot
<< 11);
298 val
= __raw_readl(local_pci_cfg_base
+ CSR_OFFSET
);
299 val
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
| PCI_COMMAND_INVALIDATE
;
300 __raw_writel(val
, local_pci_cfg_base
+ CSR_OFFSET
);
303 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
305 __raw_writel(PHYS_OFFSET
, local_pci_cfg_base
+ PCI_BASE_ADDRESS_0
);
306 __raw_writel(PHYS_OFFSET
, local_pci_cfg_base
+ PCI_BASE_ADDRESS_1
);
307 __raw_writel(PHYS_OFFSET
, local_pci_cfg_base
+ PCI_BASE_ADDRESS_2
);
310 * Do not to map Versatile FPGA PCI device into memory space
312 pci_slot_ignore
|= (1 << myslot
);
320 void __init
pci_versatile_preinit(void)
322 pcibios_min_io
= 0x44000000;
323 pcibios_min_mem
= 0x50000000;
325 __raw_writel(VERSATILE_PCI_MEM_BASE0
>> 28, PCI_IMAP0
);
326 __raw_writel(VERSATILE_PCI_MEM_BASE1
>> 28, PCI_IMAP1
);
327 __raw_writel(VERSATILE_PCI_MEM_BASE2
>> 28, PCI_IMAP2
);
329 __raw_writel(PHYS_OFFSET
>> 28, PCI_SMAP0
);
330 __raw_writel(PHYS_OFFSET
>> 28, PCI_SMAP1
);
331 __raw_writel(PHYS_OFFSET
>> 28, PCI_SMAP2
);
333 __raw_writel(1, SYS_PCICTL
);
337 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
339 static int __init
versatile_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
349 irq
= 27 + ((slot
- 24 + pin
- 1) & 3);
354 static struct hw_pci versatile_pci __initdata
= {
355 .map_irq
= versatile_map_irq
,
357 .ops
= &pci_versatile_ops
,
358 .setup
= pci_versatile_setup
,
359 .preinit
= pci_versatile_preinit
,
362 static int __init
versatile_pci_init(void)
364 pci_common_init(&versatile_pci
);
368 subsys_initcall(versatile_pci_init
);