arch/arm/mach-vt8500/irq.c

   1 /*
   2  *  arch/arm/mach-vt8500/irq.c
   3  *
   4  *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23  * This file is copied and modified from the original irq.c provided by
  24  * Alexey Charkov. Minor changes have been made for Device Tree Support.
  25  */
  26
  27 #include <linux/slab.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqdomain.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/bitops.h>
  33
  34 #include <linux/of.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/of_address.h>
  37
  38 #include <asm/irq.h>
  39
  40
  41 #define VT8500_ICPC_IRQ         0x20
  42 #define VT8500_ICPC_FIQ         0x24
  43 #define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
  44 #define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
  45
  46 /* ICPC */
  47 #define ICPC_MASK               0x3F
  48 #define ICPC_ROTATE             BIT(6)
  49
  50 /* IC_DCTR */
  51 #define ICDC_IRQ                0x00
  52 #define ICDC_FIQ                0x01
  53 #define ICDC_DSS0               0x02
  54 #define ICDC_DSS1               0x03
  55 #define ICDC_DSS2               0x04
  56 #define ICDC_DSS3               0x05
  57 #define ICDC_DSS4               0x06
  58 #define ICDC_DSS5               0x07
  59
  60 #define VT8500_INT_DISABLE      0
  61 #define VT8500_INT_ENABLE       BIT(3)
  62
  63 #define VT8500_TRIGGER_HIGH     0
  64 #define VT8500_TRIGGER_RISING   BIT(5)
  65 #define VT8500_TRIGGER_FALLING  BIT(6)
  66 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
  67                                 | VT8500_TRIGGER_FALLING)
  68
  69 static int irq_cnt;
  70
  71 struct vt8500_irq_priv {
  72         void __iomem *base;
  73 };
  74
  75 static void vt8500_irq_mask(struct irq_data *d)
  76 {
  77         struct vt8500_irq_priv *priv =
  78                         (struct vt8500_irq_priv *)(d->domain->host_data);
  79         void __iomem *base = priv->base;
  80         u8 edge;
  81
  82         edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
  83         if (edge) {
  84                 void __iomem *stat_reg = base + VT8500_ICIS
  85                                                 + (d->hwirq < 32 ? 0 : 4);
  86                 unsigned status = readl(stat_reg);
  87
  88                 status |= (1 << (d->hwirq & 0x1f));
  89                 writel(status, stat_reg);
  90         } else {
  91                 u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
  92
  93                 dctr &= ~VT8500_INT_ENABLE;
  94                 writeb(dctr, base + VT8500_ICDC + d->hwirq);
  95         }
  96 }
  97
  98 static void vt8500_irq_unmask(struct irq_data *d)
  99 {
 100         struct vt8500_irq_priv *priv =
 101                         (struct vt8500_irq_priv *)(d->domain->host_data);
 102         void __iomem *base = priv->base;
 103         u8 dctr;
 104
 105         dctr = readb(base + VT8500_ICDC + d->hwirq);
 106         dctr |= VT8500_INT_ENABLE;
 107         writeb(dctr, base + VT8500_ICDC + d->hwirq);
 108 }
 109
 110 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 111 {
 112         struct vt8500_irq_priv *priv =
 113                         (struct vt8500_irq_priv *)(d->domain->host_data);
 114         void __iomem *base = priv->base;
 115         u8 dctr;
 116
 117         dctr = readb(base + VT8500_ICDC + d->hwirq);
 118         dctr &= ~VT8500_EDGE;
 119
 120         switch (flow_type) {
 121         case IRQF_TRIGGER_LOW:
 122                 return -EINVAL;
 123         case IRQF_TRIGGER_HIGH:
 124                 dctr |= VT8500_TRIGGER_HIGH;
 125                 __irq_set_handler_locked(d->irq, handle_level_irq);
 126                 break;
 127         case IRQF_TRIGGER_FALLING:
 128                 dctr |= VT8500_TRIGGER_FALLING;
 129                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 130                 break;
 131         case IRQF_TRIGGER_RISING:
 132                 dctr |= VT8500_TRIGGER_RISING;
 133                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 134                 break;
 135         }
 136         writeb(dctr, base + VT8500_ICDC + d->hwirq);
 137
 138         return 0;
 139 }
 140
 141 static struct irq_chip vt8500_irq_chip = {
 142         .name = "vt8500",
 143         .irq_ack = vt8500_irq_mask,
 144         .irq_mask = vt8500_irq_mask,
 145         .irq_unmask = vt8500_irq_unmask,
 146         .irq_set_type = vt8500_irq_set_type,
 147 };
 148
 149 static void __init vt8500_init_irq_hw(void __iomem *base)
 150 {
 151         unsigned int i;
 152
 153         /* Enable rotating priority for IRQ */
 154         writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
 155         writel(0x00, base + VT8500_ICPC_FIQ);
 156
 157         for (i = 0; i < 64; i++) {
 158                 /* Disable all interrupts and route them to IRQ */
 159                 writeb(VT8500_INT_DISABLE | ICDC_IRQ,
 160                                                 base + VT8500_ICDC + i);
 161         }
 162 }
 163
 164 static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
 165                                                         irq_hw_number_t hw)
 166 {
 167         irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
 168         set_irq_flags(virq, IRQF_VALID);
 169
 170         return 0;
 171 }
 172
 173 static struct irq_domain_ops vt8500_irq_domain_ops = {
 174         .map = vt8500_irq_map,
 175         .xlate = irq_domain_xlate_onecell,
 176 };
 177
 178 int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 179 {
 180         struct irq_domain *vt8500_irq_domain;
 181         struct vt8500_irq_priv *priv;
 182         int irq, i;
 183         struct device_node *np = node;
 184
 185         priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
 186         priv->base = of_iomap(np, 0);
 187
 188         vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
 189                                 &vt8500_irq_domain_ops, priv);
 190         if (!vt8500_irq_domain)
 191                 pr_err("%s: Unable to add wmt irq domain!\n", __func__);
 192
 193         irq_set_default_host(vt8500_irq_domain);
 194
 195         vt8500_init_irq_hw(priv->base);
 196
 197         pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
 198                                                 (u32)(priv->base), irq_cnt);
 199
 200         /* check if this is a slaved controller */
 201         if (of_irq_count(np) != 0) {
 202                 /* check that we have the correct number of interrupts */
 203                 if (of_irq_count(np) != 8) {
 204                         pr_err("%s: Incorrect IRQ map for slave controller\n",
 205                                         __func__);
 206                         return -EINVAL;
 207                 }
 208
 209                 for (i = 0; i < 8; i++) {
 210                         irq = irq_of_parse_and_map(np, i);
 211                         enable_irq(irq);
 212                 }
 213
 214                 pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
 215         }
 216
 217         irq_cnt += 64;
 218
 219         return 0;
 220 }
 221