arch/arm/mach-zynq/slcr.c

   1 /*
   2  * Xilinx SLCR driver
   3  *
   4  * Copyright (c) 2011-2013 Xilinx Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  *
  11  * You should have received a copy of the GNU General Public
  12  * License along with this program; if not, write to the Free
  13  * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
  14  * 02139, USA.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of_address.h>
  20 #include <linux/regmap.h>
  21 #include <linux/clk/zynq.h>
  22 #include "common.h"
  23
  24 /* register offsets */
  25 #define SLCR_UNLOCK_OFFSET              0x8   /* SCLR unlock register */
  26 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
  27 #define SLCR_A9_CPU_RST_CTRL_OFFSET     0x244 /* CPU Software Reset Control */
  28 #define SLCR_REBOOT_STATUS_OFFSET       0x258 /* PS Reboot Status */
  29
  30 #define SLCR_UNLOCK_MAGIC               0xDF0D
  31 #define SLCR_A9_CPU_CLKSTOP             0x10
  32 #define SLCR_A9_CPU_RST                 0x1
  33
  34 void __iomem *zynq_slcr_base;
  35 static struct regmap *zynq_slcr_regmap;
  36
  37 /**
  38  * zynq_slcr_system_reset - Reset the entire system.
  39  */
  40 void zynq_slcr_system_reset(void)
  41 {
  42         u32 reboot;
  43
  44         /*
  45          * Unlock the SLCR then reset the system.
  46          * Note that this seems to require raw i/o
  47          * functions or there's a lockup?
  48          */
  49         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
  50
  51         /*
  52          * Clear 0x0F000000 bits of reboot status register to workaround
  53          * the FSBL not loading the bitstream after soft-reboot
  54          * This is a temporary solution until we know more.
  55          */
  56         reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
  57         writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
  58         writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
  59 }
  60
  61 /**
  62  * zynq_slcr_cpu_start - Start cpu
  63  * @cpu:        cpu number
  64  */
  65 void zynq_slcr_cpu_start(int cpu)
  66 {
  67         u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
  68         reg &= ~(SLCR_A9_CPU_RST << cpu);
  69         writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
  70         reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
  71         writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
  72 }
  73
  74 /**
  75  * zynq_slcr_cpu_stop - Stop cpu
  76  * @cpu:        cpu number
  77  */
  78 void zynq_slcr_cpu_stop(int cpu)
  79 {
  80         u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
  81         reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
  82         writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
  83 }
  84
  85 /**
  86  * zynq_slcr_init - Regular slcr driver init
  87  *
  88  * Return:      0 on success, negative errno otherwise.
  89  *
  90  * Called early during boot from platform code to remap SLCR area.
  91  */
  92 int __init zynq_slcr_init(void)
  93 {
  94         zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
  95         if (IS_ERR(zynq_slcr_regmap)) {
  96                 pr_err("%s: failed to find zynq-slcr\n", __func__);
  97                 return -ENODEV;
  98         }
  99
 100         return 0;
 101 }
 102
 103 /**
 104  * zynq_early_slcr_init - Early slcr init function
 105  *
 106  * Return:      0 on success, negative errno otherwise.
 107  *
 108  * Called very early during boot from platform code to unlock SLCR.
 109  */
 110 int __init zynq_early_slcr_init(void)
 111 {
 112         struct device_node *np;
 113
 114         np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
 115         if (!np) {
 116                 pr_err("%s: no slcr node found\n", __func__);
 117                 BUG();
 118         }
 119
 120         zynq_slcr_base = of_iomap(np, 0);
 121         if (!zynq_slcr_base) {
 122                 pr_err("%s: Unable to map I/O memory\n", __func__);
 123                 BUG();
 124         }
 125
 126         np->data = (__force void *)zynq_slcr_base;
 127
 128         /* unlock the SLCR so that registers can be changed */
 129         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
 130
 131         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 132
 133         of_node_put(np);
 134
 135         return 0;
 136 }