arch/arm/mach-zynq/slcr.c

   1 /*
   2  * Xilinx SLCR driver
   3  *
   4  * Copyright (c) 2011-2013 Xilinx Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  *
  11  * You should have received a copy of the GNU General Public
  12  * License along with this program; if not, write to the Free
  13  * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
  14  * 02139, USA.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of_address.h>
  20 #include <linux/regmap.h>
  21 #include <linux/clk/zynq.h>
  22 #include "common.h"
  23
  24 /* register offsets */
  25 #define SLCR_UNLOCK_OFFSET              0x8   /* SCLR unlock register */
  26 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
  27 #define SLCR_A9_CPU_RST_CTRL_OFFSET     0x244 /* CPU Software Reset Control */
  28 #define SLCR_REBOOT_STATUS_OFFSET       0x258 /* PS Reboot Status */
  29
  30 #define SLCR_UNLOCK_MAGIC               0xDF0D
  31 #define SLCR_A9_CPU_CLKSTOP             0x10
  32 #define SLCR_A9_CPU_RST                 0x1
  33
  34 static void __iomem *zynq_slcr_base;
  35 static struct regmap *zynq_slcr_regmap;
  36
  37 /**
  38  * zynq_slcr_write - Write to a register in SLCR block
  39  *
  40  * @val:        Value to write to the register
  41  * @offset:     Register offset in SLCR block
  42  *
  43  * Return:      a negative value on error, 0 on success
  44  */
  45 static int zynq_slcr_write(u32 val, u32 offset)
  46 {
  47         if (!zynq_slcr_regmap) {
  48                 writel(val, zynq_slcr_base + offset);
  49                 return 0;
  50         }
  51
  52         return regmap_write(zynq_slcr_regmap, offset, val);
  53 }
  54
  55 /**
  56  * zynq_slcr_read - Read a register in SLCR block
  57  *
  58  * @val:        Pointer to value to be read from SLCR
  59  * @offset:     Register offset in SLCR block
  60  *
  61  * Return:      a negative value on error, 0 on success
  62  */
  63 static int zynq_slcr_read(u32 *val, u32 offset)
  64 {
  65         if (zynq_slcr_regmap)
  66                 return regmap_read(zynq_slcr_regmap, offset, val);
  67
  68         *val = readl(zynq_slcr_base + offset);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  * zynq_slcr_system_reset - Reset the entire system.
  75  */
  76 void zynq_slcr_system_reset(void)
  77 {
  78         u32 reboot;
  79
  80         /*
  81          * Unlock the SLCR then reset the system.
  82          * Note that this seems to require raw i/o
  83          * functions or there's a lockup?
  84          */
  85         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
  86
  87         /*
  88          * Clear 0x0F000000 bits of reboot status register to workaround
  89          * the FSBL not loading the bitstream after soft-reboot
  90          * This is a temporary solution until we know more.
  91          */
  92         zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
  93         zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
  94         zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
  95 }
  96
  97 /**
  98  * zynq_slcr_cpu_start - Start cpu
  99  * @cpu:        cpu number
 100  */
 101 void zynq_slcr_cpu_start(int cpu)
 102 {
 103         u32 reg;
 104
 105         zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 106         reg &= ~(SLCR_A9_CPU_RST << cpu);
 107         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 108         reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
 109         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 110 }
 111
 112 /**
 113  * zynq_slcr_cpu_stop - Stop cpu
 114  * @cpu:        cpu number
 115  */
 116 void zynq_slcr_cpu_stop(int cpu)
 117 {
 118         u32 reg;
 119
 120         zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 121         reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
 122         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 123 }
 124
 125 /**
 126  * zynq_slcr_init - Regular slcr driver init
 127  *
 128  * Return:      0 on success, negative errno otherwise.
 129  *
 130  * Called early during boot from platform code to remap SLCR area.
 131  */
 132 int __init zynq_slcr_init(void)
 133 {
 134         zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
 135         if (IS_ERR(zynq_slcr_regmap)) {
 136                 pr_err("%s: failed to find zynq-slcr\n", __func__);
 137                 return -ENODEV;
 138         }
 139
 140         return 0;
 141 }
 142
 143 /**
 144  * zynq_early_slcr_init - Early slcr init function
 145  *
 146  * Return:      0 on success, negative errno otherwise.
 147  *
 148  * Called very early during boot from platform code to unlock SLCR.
 149  */
 150 int __init zynq_early_slcr_init(void)
 151 {
 152         struct device_node *np;
 153
 154         np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
 155         if (!np) {
 156                 pr_err("%s: no slcr node found\n", __func__);
 157                 BUG();
 158         }
 159
 160         zynq_slcr_base = of_iomap(np, 0);
 161         if (!zynq_slcr_base) {
 162                 pr_err("%s: Unable to map I/O memory\n", __func__);
 163                 BUG();
 164         }
 165
 166         np->data = (__force void *)zynq_slcr_base;
 167
 168         /* unlock the SLCR so that registers can be changed */
 169         writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
 170
 171         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 172
 173         of_node_put(np);
 174
 175         return 0;
 176 }