arch/arm/mach-zynq/timer.c

   1 /*
   2  * This file contains driver for the Xilinx PS Timer Counter IP.
   3  *
   4  *  Copyright (C) 2011 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/types.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/slab.h>
  30 #include <linux/clk-provider.h>
  31
  32 #include "common.h"
  33
  34 /*
  35  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  36  * and use same offsets for Timer 2
  37  */
  38 #define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
  39 #define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
  40 #define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
  41 #define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
  42 #define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
  43 #define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
  44
  45 #define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
  46
  47 /* Setup the timers to use pre-scaling, using a fixed value for now that will
  48  * work across most input frequency, but it may need to be more dynamic
  49  */
  50 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  51 #define PRESCALE                2048    /* The exponent must match this */
  52 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  53 #define CLK_CNTRL_PRESCALE_EN   1
  54 #define CNT_CNTRL_RESET         (1<<4)
  55
  56 /**
  57  * struct xttcps_timer - This definition defines local timer structure
  58  *
  59  * @base_addr:  Base address of timer
  60  **/
  61 struct xttcps_timer {
  62         void __iomem    *base_addr;
  63 };
  64
  65 struct xttcps_timer_clocksource {
  66         struct xttcps_timer     xttc;
  67         struct clocksource      cs;
  68 };
  69
  70 #define to_xttcps_timer_clksrc(x) \
  71                 container_of(x, struct xttcps_timer_clocksource, cs)
  72
  73 struct xttcps_timer_clockevent {
  74         struct xttcps_timer             xttc;
  75         struct clock_event_device       ce;
  76         struct clk                      *clk;
  77 };
  78
  79 #define to_xttcps_timer_clkevent(x) \
  80                 container_of(x, struct xttcps_timer_clockevent, ce)
  81
  82 /**
  83  * xttcps_set_interval - Set the timer interval value
  84  *
  85  * @timer:      Pointer to the timer instance
  86  * @cycles:     Timer interval ticks
  87  **/
  88 static void xttcps_set_interval(struct xttcps_timer *timer,
  89                                         unsigned long cycles)
  90 {
  91         u32 ctrl_reg;
  92
  93         /* Disable the counter, set the counter value  and re-enable counter */
  94         ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
  95         ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
  96         __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
  97
  98         __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
  99
 100         /* Reset the counter (0x10) so that it starts from 0, one-shot
 101            mode makes this needed for timing to be right. */
 102         ctrl_reg |= CNT_CNTRL_RESET;
 103         ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
 104         __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 105 }
 106
 107 /**
 108  * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 109  *
 110  * @irq:        IRQ number of the Timer
 111  * @dev_id:     void pointer to the xttcps_timer instance
 112  *
 113  * returns: Always IRQ_HANDLED - success
 114  **/
 115 static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
 116 {
 117         struct xttcps_timer_clockevent *xttce = dev_id;
 118         struct xttcps_timer *timer = &xttce->xttc;
 119
 120         /* Acknowledge the interrupt and call event handler */
 121         __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
 122
 123         xttce->ce.event_handler(&xttce->ce);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 /**
 129  * __xttc_clocksource_read - Reads the timer counter register
 130  *
 131  * returns: Current timer counter register value
 132  **/
 133 static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 134 {
 135         struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
 136
 137         return (cycle_t)__raw_readl(timer->base_addr +
 138                                 XTTCPS_COUNT_VAL_OFFSET);
 139 }
 140
 141 /**
 142  * xttcps_set_next_event - Sets the time interval for next event
 143  *
 144  * @cycles:     Timer interval ticks
 145  * @evt:        Address of clock event instance
 146  *
 147  * returns: Always 0 - success
 148  **/
 149 static int xttcps_set_next_event(unsigned long cycles,
 150                                         struct clock_event_device *evt)
 151 {
 152         struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
 153         struct xttcps_timer *timer = &xttce->xttc;
 154
 155         xttcps_set_interval(timer, cycles);
 156         return 0;
 157 }
 158
 159 /**
 160  * xttcps_set_mode - Sets the mode of timer
 161  *
 162  * @mode:       Mode to be set
 163  * @evt:        Address of clock event instance
 164  **/
 165 static void xttcps_set_mode(enum clock_event_mode mode,
 166                                         struct clock_event_device *evt)
 167 {
 168         struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
 169         struct xttcps_timer *timer = &xttce->xttc;
 170         u32 ctrl_reg;
 171
 172         switch (mode) {
 173         case CLOCK_EVT_MODE_PERIODIC:
 174                 xttcps_set_interval(timer,
 175                                      DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
 176                                                        PRESCALE * HZ));
 177                 break;
 178         case CLOCK_EVT_MODE_ONESHOT:
 179         case CLOCK_EVT_MODE_UNUSED:
 180         case CLOCK_EVT_MODE_SHUTDOWN:
 181                 ctrl_reg = __raw_readl(timer->base_addr +
 182                                         XTTCPS_CNT_CNTRL_OFFSET);
 183                 ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
 184                 __raw_writel(ctrl_reg,
 185                                 timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 186                 break;
 187         case CLOCK_EVT_MODE_RESUME:
 188                 ctrl_reg = __raw_readl(timer->base_addr +
 189                                         XTTCPS_CNT_CNTRL_OFFSET);
 190                 ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
 191                 __raw_writel(ctrl_reg,
 192                                 timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 193                 break;
 194         }
 195 }
 196
 197 static void __init zynq_ttc_setup_clocksource(struct device_node *np,
 198                                              void __iomem *base)
 199 {
 200         struct xttcps_timer_clocksource *ttccs;
 201         struct clk *clk;
 202         int err;
 203         u32 reg;
 204
 205         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 206         if (WARN_ON(!ttccs))
 207                 return;
 208
 209         err = of_property_read_u32(np, "reg", &reg);
 210         if (WARN_ON(err))
 211                 return;
 212
 213         clk = of_clk_get_by_name(np, "cpu_1x");
 214         if (WARN_ON(IS_ERR(clk)))
 215                 return;
 216
 217         err = clk_prepare_enable(clk);
 218         if (WARN_ON(err))
 219                 return;
 220
 221         ttccs->xttc.base_addr = base + reg * 4;
 222
 223         ttccs->cs.name = np->name;
 224         ttccs->cs.rating = 200;
 225         ttccs->cs.read = __xttc_clocksource_read;
 226         ttccs->cs.mask = CLOCKSOURCE_MASK(16);
 227         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 228
 229         __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
 230         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 231                      ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
 232         __raw_writel(CNT_CNTRL_RESET,
 233                      ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 234
 235         err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
 236         if (WARN_ON(err))
 237                 return;
 238 }
 239
 240 static void __init zynq_ttc_setup_clockevent(struct device_node *np,
 241                                             void __iomem *base)
 242 {
 243         struct xttcps_timer_clockevent *ttcce;
 244         int err, irq;
 245         u32 reg;
 246
 247         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 248         if (WARN_ON(!ttcce))
 249                 return;
 250
 251         err = of_property_read_u32(np, "reg", &reg);
 252         if (WARN_ON(err))
 253                 return;
 254
 255         ttcce->xttc.base_addr = base + reg * 4;
 256
 257         ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
 258         if (WARN_ON(IS_ERR(ttcce->clk)))
 259                 return;
 260
 261         err = clk_prepare_enable(ttcce->clk);
 262         if (WARN_ON(err))
 263                 return;
 264
 265         irq = irq_of_parse_and_map(np, 0);
 266         if (WARN_ON(!irq))
 267                 return;
 268
 269         ttcce->ce.name = np->name;
 270         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 271         ttcce->ce.set_next_event = xttcps_set_next_event;
 272         ttcce->ce.set_mode = xttcps_set_mode;
 273         ttcce->ce.rating = 200;
 274         ttcce->ce.irq = irq;
 275
 276         __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 277         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 278                      ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
 279         __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
 280
 281         err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
 282                           np->name, ttcce);
 283         if (WARN_ON(err))
 284                 return;
 285
 286         clockevents_config_and_register(&ttcce->ce,
 287                                         clk_get_rate(ttcce->clk) / PRESCALE,
 288                                         1, 0xfffe);
 289 }
 290
 291 static const __initconst struct of_device_id zynq_ttc_match[] = {
 292         { .compatible = "xlnx,ttc-counter-clocksource",
 293                 .data = zynq_ttc_setup_clocksource, },
 294         { .compatible = "xlnx,ttc-counter-clockevent",
 295                 .data = zynq_ttc_setup_clockevent, },
 296         {}
 297 };
 298
 299 /**
 300  * xttcps_timer_init - Initialize the timer
 301  *
 302  * Initializes the timer hardware and register the clock source and clock event
 303  * timers with Linux kernal timer framework
 304  **/
 305 void __init xttcps_timer_init(void)
 306 {
 307         struct device_node *np;
 308
 309         for_each_compatible_node(np, NULL, "xlnx,ttc") {
 310                 struct device_node *np_chld;
 311                 void __iomem *base;
 312
 313                 base = of_iomap(np, 0);
 314                 if (WARN_ON(!base))
 315                         return;
 316
 317                 for_each_available_child_of_node(np, np_chld) {
 318                         int (*cb)(struct device_node *np, void __iomem *base);
 319                         const struct of_device_id *match;
 320
 321                         match = of_match_node(zynq_ttc_match, np_chld);
 322                         if (match) {
 323                                 cb = match->data;
 324                                 cb(np_chld, base);
 325                         }
 326                 }
 327         }
 328 }