arch/arm/mach-zynq/timer.c

   1 /*
   2  * This file contains driver for the Xilinx PS Timer Counter IP.
   3  *
   4  *  Copyright (C) 2011 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/types.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/slab.h>
  30 #include <linux/clk-provider.h>
  31
  32 #include "common.h"
  33
  34 /*
  35  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  36  * and use same offsets for Timer 2
  37  */
  38 #define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
  39 #define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
  40 #define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
  41 #define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
  42 #define XTTCPS_MATCH_1_OFFSET           0x30 /* Match 1 Value Reg, RW */
  43 #define XTTCPS_MATCH_2_OFFSET           0x3C /* Match 2 Value Reg, RW */
  44 #define XTTCPS_MATCH_3_OFFSET           0x48 /* Match 3 Value Reg, RW */
  45 #define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
  46 #define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
  47
  48 #define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
  49
  50 /* Setup the timers to use pre-scaling, using a fixed value for now that will
  51  * work across most input frequency, but it may need to be more dynamic
  52  */
  53 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  54 #define PRESCALE                2048    /* The exponent must match this */
  55 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  56 #define CLK_CNTRL_PRESCALE_EN   1
  57 #define CNT_CNTRL_RESET         (1<<4)
  58
  59 /**
  60  * struct xttcps_timer - This definition defines local timer structure
  61  *
  62  * @base_addr:  Base address of timer
  63  **/
  64 struct xttcps_timer {
  65         void __iomem    *base_addr;
  66 };
  67
  68 struct xttcps_timer_clocksource {
  69         struct xttcps_timer     xttc;
  70         struct clocksource      cs;
  71 };
  72
  73 #define to_xttcps_timer_clksrc(x) \
  74                 container_of(x, struct xttcps_timer_clocksource, cs)
  75
  76 struct xttcps_timer_clockevent {
  77         struct xttcps_timer             xttc;
  78         struct clock_event_device       ce;
  79         struct clk                      *clk;
  80 };
  81
  82 #define to_xttcps_timer_clkevent(x) \
  83                 container_of(x, struct xttcps_timer_clockevent, ce)
  84
  85 /**
  86  * xttcps_set_interval - Set the timer interval value
  87  *
  88  * @timer:      Pointer to the timer instance
  89  * @cycles:     Timer interval ticks
  90  **/
  91 static void xttcps_set_interval(struct xttcps_timer *timer,
  92                                         unsigned long cycles)
  93 {
  94         u32 ctrl_reg;
  95
  96         /* Disable the counter, set the counter value  and re-enable counter */
  97         ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
  98         ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
  99         __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 100
 101         __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
 102
 103         /* Reset the counter (0x10) so that it starts from 0, one-shot
 104            mode makes this needed for timing to be right. */
 105         ctrl_reg |= CNT_CNTRL_RESET;
 106         ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
 107         __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 108 }
 109
 110 /**
 111  * xttcps_clock_event_interrupt - Clock event timer interrupt handler
 112  *
 113  * @irq:        IRQ number of the Timer
 114  * @dev_id:     void pointer to the xttcps_timer instance
 115  *
 116  * returns: Always IRQ_HANDLED - success
 117  **/
 118 static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
 119 {
 120         struct xttcps_timer_clockevent *xttce = dev_id;
 121         struct xttcps_timer *timer = &xttce->xttc;
 122
 123         /* Acknowledge the interrupt and call event handler */
 124         __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
 125
 126         xttce->ce.event_handler(&xttce->ce);
 127
 128         return IRQ_HANDLED;
 129 }
 130
 131 /**
 132  * __xttc_clocksource_read - Reads the timer counter register
 133  *
 134  * returns: Current timer counter register value
 135  **/
 136 static cycle_t __xttc_clocksource_read(struct clocksource *cs)
 137 {
 138         struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
 139
 140         return (cycle_t)__raw_readl(timer->base_addr +
 141                                 XTTCPS_COUNT_VAL_OFFSET);
 142 }
 143
 144 /**
 145  * xttcps_set_next_event - Sets the time interval for next event
 146  *
 147  * @cycles:     Timer interval ticks
 148  * @evt:        Address of clock event instance
 149  *
 150  * returns: Always 0 - success
 151  **/
 152 static int xttcps_set_next_event(unsigned long cycles,
 153                                         struct clock_event_device *evt)
 154 {
 155         struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
 156         struct xttcps_timer *timer = &xttce->xttc;
 157
 158         xttcps_set_interval(timer, cycles);
 159         return 0;
 160 }
 161
 162 /**
 163  * xttcps_set_mode - Sets the mode of timer
 164  *
 165  * @mode:       Mode to be set
 166  * @evt:        Address of clock event instance
 167  **/
 168 static void xttcps_set_mode(enum clock_event_mode mode,
 169                                         struct clock_event_device *evt)
 170 {
 171         struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
 172         struct xttcps_timer *timer = &xttce->xttc;
 173         u32 ctrl_reg;
 174
 175         switch (mode) {
 176         case CLOCK_EVT_MODE_PERIODIC:
 177                 xttcps_set_interval(timer,
 178                                      DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
 179                                                        PRESCALE * HZ));
 180                 break;
 181         case CLOCK_EVT_MODE_ONESHOT:
 182         case CLOCK_EVT_MODE_UNUSED:
 183         case CLOCK_EVT_MODE_SHUTDOWN:
 184                 ctrl_reg = __raw_readl(timer->base_addr +
 185                                         XTTCPS_CNT_CNTRL_OFFSET);
 186                 ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
 187                 __raw_writel(ctrl_reg,
 188                                 timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 189                 break;
 190         case CLOCK_EVT_MODE_RESUME:
 191                 ctrl_reg = __raw_readl(timer->base_addr +
 192                                         XTTCPS_CNT_CNTRL_OFFSET);
 193                 ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
 194                 __raw_writel(ctrl_reg,
 195                                 timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 196                 break;
 197         }
 198 }
 199
 200 static void __init zynq_ttc_setup_clocksource(struct device_node *np,
 201                                              void __iomem *base)
 202 {
 203         struct xttcps_timer_clocksource *ttccs;
 204         struct clk *clk;
 205         int err;
 206         u32 reg;
 207
 208         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 209         if (WARN_ON(!ttccs))
 210                 return;
 211
 212         err = of_property_read_u32(np, "reg", &reg);
 213         if (WARN_ON(err))
 214                 return;
 215
 216         clk = of_clk_get_by_name(np, "cpu_1x");
 217         if (WARN_ON(IS_ERR(clk)))
 218                 return;
 219
 220         err = clk_prepare_enable(clk);
 221         if (WARN_ON(err))
 222                 return;
 223
 224         ttccs->xttc.base_addr = base + reg * 4;
 225
 226         ttccs->cs.name = np->name;
 227         ttccs->cs.rating = 200;
 228         ttccs->cs.read = __xttc_clocksource_read;
 229         ttccs->cs.mask = CLOCKSOURCE_MASK(16);
 230         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 231
 232         __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
 233         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 234                      ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
 235         __raw_writel(CNT_CNTRL_RESET,
 236                      ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 237
 238         err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
 239         if (WARN_ON(err))
 240                 return;
 241 }
 242
 243 static void __init zynq_ttc_setup_clockevent(struct device_node *np,
 244                                             void __iomem *base)
 245 {
 246         struct xttcps_timer_clockevent *ttcce;
 247         int err, irq;
 248         u32 reg;
 249
 250         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 251         if (WARN_ON(!ttcce))
 252                 return;
 253
 254         err = of_property_read_u32(np, "reg", &reg);
 255         if (WARN_ON(err))
 256                 return;
 257
 258         ttcce->xttc.base_addr = base + reg * 4;
 259
 260         ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
 261         if (WARN_ON(IS_ERR(ttcce->clk)))
 262                 return;
 263
 264         err = clk_prepare_enable(ttcce->clk);
 265         if (WARN_ON(err))
 266                 return;
 267
 268         irq = irq_of_parse_and_map(np, 0);
 269         if (WARN_ON(!irq))
 270                 return;
 271
 272         ttcce->ce.name = np->name;
 273         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 274         ttcce->ce.set_next_event = xttcps_set_next_event;
 275         ttcce->ce.set_mode = xttcps_set_mode;
 276         ttcce->ce.rating = 200;
 277         ttcce->ce.irq = irq;
 278
 279         __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
 280         __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 281                      ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
 282         __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
 283
 284         err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
 285                           np->name, ttcce);
 286         if (WARN_ON(err))
 287                 return;
 288
 289         clockevents_config_and_register(&ttcce->ce,
 290                                         clk_get_rate(ttcce->clk) / PRESCALE,
 291                                         1, 0xfffe);
 292 }
 293
 294 static const __initconst struct of_device_id zynq_ttc_match[] = {
 295         { .compatible = "xlnx,ttc-counter-clocksource",
 296                 .data = zynq_ttc_setup_clocksource, },
 297         { .compatible = "xlnx,ttc-counter-clockevent",
 298                 .data = zynq_ttc_setup_clockevent, },
 299         {}
 300 };
 301
 302 /**
 303  * xttcps_timer_init - Initialize the timer
 304  *
 305  * Initializes the timer hardware and register the clock source and clock event
 306  * timers with Linux kernal timer framework
 307  **/
 308 void __init xttcps_timer_init(void)
 309 {
 310         struct device_node *np;
 311
 312         for_each_compatible_node(np, NULL, "xlnx,ttc") {
 313                 struct device_node *np_chld;
 314                 void __iomem *base;
 315
 316                 base = of_iomap(np, 0);
 317                 if (WARN_ON(!base))
 318                         return;
 319
 320                 for_each_available_child_of_node(np, np_chld) {
 321                         int (*cb)(struct device_node *np, void __iomem *base);
 322                         const struct of_device_id *match;
 323
 324                         match = of_match_node(zynq_ttc_match, np_chld);
 325                         if (match) {
 326                                 cb = match->data;
 327                                 cb(np_chld, base);
 328                         }
 329                 }
 330         }
 331 }