arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 # Select CPU types depending on the architecture selected.  This selects
   4 # which CPUs we support in the kernel image, and the compiler instruction
   5 # optimiser behaviour.
   6
   7 # ARM7TDMI
   8 config CPU_ARM7TDMI
   9         bool "Support ARM7TDMI processor"
  10         depends on !MMU
  11         select CPU_32v4T
  12         select CPU_ABRT_LV4T
  13         select CPU_PABRT_LEGACY
  14         select CPU_CACHE_V4
  15         help
  16           A 32-bit RISC microprocessor based on the ARM7 processor core
  17           which has no memory control unit and cache.
  18
  19           Say Y if you want support for the ARM7TDMI processor.
  20           Otherwise, say N.
  21
  22 # ARM720T
  23 config CPU_ARM720T
  24         bool "Support ARM720T processor" if ARCH_INTEGRATOR
  25         select CPU_32v4T
  26         select CPU_ABRT_LV4T
  27         select CPU_PABRT_LEGACY
  28         select CPU_CACHE_V4
  29         select CPU_CACHE_VIVT
  30         select CPU_CP15_MMU
  31         select CPU_COPY_V4WT if MMU
  32         select CPU_TLB_V4WT if MMU
  33         help
  34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  35           MMU built around an ARM7TDMI core.
  36
  37           Say Y if you want support for the ARM720T processor.
  38           Otherwise, say N.
  39
  40 # ARM740T
  41 config CPU_ARM740T
  42         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  43         depends on !MMU
  44         select CPU_32v4T
  45         select CPU_ABRT_LV4T
  46         select CPU_PABRT_LEGACY
  47         select CPU_CACHE_V3     # although the core is v4t
  48         select CPU_CP15_MPU
  49         help
  50           A 32-bit RISC processor with 8KB cache or 4KB variants,
  51           write buffer and MPU(Protection Unit) built around
  52           an ARM7TDMI core.
  53
  54           Say Y if you want support for the ARM740T processor.
  55           Otherwise, say N.
  56
  57 # ARM9TDMI
  58 config CPU_ARM9TDMI
  59         bool "Support ARM9TDMI processor"
  60         depends on !MMU
  61         select CPU_32v4T
  62         select CPU_ABRT_NOMMU
  63         select CPU_PABRT_LEGACY
  64         select CPU_CACHE_V4
  65         help
  66           A 32-bit RISC microprocessor based on the ARM9 processor core
  67           which has no memory control unit and cache.
  68
  69           Say Y if you want support for the ARM9TDMI processor.
  70           Otherwise, say N.
  71
  72 # ARM920T
  73 config CPU_ARM920T
  74         bool "Support ARM920T processor" if ARCH_INTEGRATOR
  75         select CPU_32v4T
  76         select CPU_ABRT_EV4T
  77         select CPU_PABRT_LEGACY
  78         select CPU_CACHE_V4WT
  79         select CPU_CACHE_VIVT
  80         select CPU_CP15_MMU
  81         select CPU_COPY_V4WB if MMU
  82         select CPU_TLB_V4WBI if MMU
  83         help
  84           The ARM920T is licensed to be produced by numerous vendors,
  85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
  86
  87           Say Y if you want support for the ARM920T processor.
  88           Otherwise, say N.
  89
  90 # ARM922T
  91 config CPU_ARM922T
  92         bool "Support ARM922T processor" if ARCH_INTEGRATOR
  93         select CPU_32v4T
  94         select CPU_ABRT_EV4T
  95         select CPU_PABRT_LEGACY
  96         select CPU_CACHE_V4WT
  97         select CPU_CACHE_VIVT
  98         select CPU_CP15_MMU
  99         select CPU_COPY_V4WB if MMU
 100         select CPU_TLB_V4WBI if MMU
 101         help
 102           The ARM922T is a version of the ARM920T, but with smaller
 103           instruction and data caches. It is used in Altera's
 104           Excalibur XA device family and Micrel's KS8695 Centaur.
 105
 106           Say Y if you want support for the ARM922T processor.
 107           Otherwise, say N.
 108
 109 # ARM925T
 110 config CPU_ARM925T
 111         bool "Support ARM925T processor" if ARCH_OMAP1
 112         select CPU_32v4T
 113         select CPU_ABRT_EV4T
 114         select CPU_PABRT_LEGACY
 115         select CPU_CACHE_V4WT
 116         select CPU_CACHE_VIVT
 117         select CPU_CP15_MMU
 118         select CPU_COPY_V4WB if MMU
 119         select CPU_TLB_V4WBI if MMU
 120         help
 121           The ARM925T is a mix between the ARM920T and ARM926T, but with
 122           different instruction and data caches. It is used in TI's OMAP
 123           device family.
 124
 125           Say Y if you want support for the ARM925T processor.
 126           Otherwise, say N.
 127
 128 # ARM926T
 129 config CPU_ARM926T
 130         bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
 131         select CPU_32v5
 132         select CPU_ABRT_EV5TJ
 133         select CPU_PABRT_LEGACY
 134         select CPU_CACHE_VIVT
 135         select CPU_CP15_MMU
 136         select CPU_COPY_V4WB if MMU
 137         select CPU_TLB_V4WBI if MMU
 138         help
 139           This is a variant of the ARM920.  It has slightly different
 140           instruction sequences for cache and TLB operations.  Curiously,
 141           there is no documentation on it at the ARM corporate website.
 142
 143           Say Y if you want support for the ARM926T processor.
 144           Otherwise, say N.
 145
 146 # FA526
 147 config CPU_FA526
 148         bool
 149         select CPU_32v4
 150         select CPU_ABRT_EV4
 151         select CPU_PABRT_LEGACY
 152         select CPU_CACHE_VIVT
 153         select CPU_CP15_MMU
 154         select CPU_CACHE_FA
 155         select CPU_COPY_FA if MMU
 156         select CPU_TLB_FA if MMU
 157         help
 158           The FA526 is a version of the ARMv4 compatible processor with
 159           Branch Target Buffer, Unified TLB and cache line size 16.
 160
 161           Say Y if you want support for the FA526 processor.
 162           Otherwise, say N.
 163
 164 # ARM940T
 165 config CPU_ARM940T
 166         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 167         depends on !MMU
 168         select CPU_32v4T
 169         select CPU_ABRT_NOMMU
 170         select CPU_PABRT_LEGACY
 171         select CPU_CACHE_VIVT
 172         select CPU_CP15_MPU
 173         help
 174           ARM940T is a member of the ARM9TDMI family of general-
 175           purpose microprocessors with MPU and separate 4KB
 176           instruction and 4KB data cases, each with a 4-word line
 177           length.
 178
 179           Say Y if you want support for the ARM940T processor.
 180           Otherwise, say N.
 181
 182 # ARM946E-S
 183 config CPU_ARM946E
 184         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 185         depends on !MMU
 186         select CPU_32v5
 187         select CPU_ABRT_NOMMU
 188         select CPU_PABRT_LEGACY
 189         select CPU_CACHE_VIVT
 190         select CPU_CP15_MPU
 191         help
 192           ARM946E-S is a member of the ARM9E-S family of high-
 193           performance, 32-bit system-on-chip processor solutions.
 194           The TCM and ARMv5TE 32-bit instruction set is supported.
 195
 196           Say Y if you want support for the ARM946E-S processor.
 197           Otherwise, say N.
 198
 199 # ARM1020 - needs validating
 200 config CPU_ARM1020
 201         bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
 202         select CPU_32v5
 203         select CPU_ABRT_EV4T
 204         select CPU_PABRT_LEGACY
 205         select CPU_CACHE_V4WT
 206         select CPU_CACHE_VIVT
 207         select CPU_CP15_MMU
 208         select CPU_COPY_V4WB if MMU
 209         select CPU_TLB_V4WBI if MMU
 210         help
 211           The ARM1020 is the 32K cached version of the ARM10 processor,
 212           with an addition of a floating-point unit.
 213
 214           Say Y if you want support for the ARM1020 processor.
 215           Otherwise, say N.
 216
 217 # ARM1020E - needs validating
 218 config CPU_ARM1020E
 219         bool "Support ARM1020E processor" if ARCH_INTEGRATOR
 220         select CPU_32v5
 221         select CPU_ABRT_EV4T
 222         select CPU_PABRT_LEGACY
 223         select CPU_CACHE_V4WT
 224         select CPU_CACHE_VIVT
 225         select CPU_CP15_MMU
 226         select CPU_COPY_V4WB if MMU
 227         select CPU_TLB_V4WBI if MMU
 228         depends on n
 229
 230 # ARM1022E
 231 config CPU_ARM1022
 232         bool "Support ARM1022E processor" if ARCH_INTEGRATOR
 233         select CPU_32v5
 234         select CPU_ABRT_EV4T
 235         select CPU_PABRT_LEGACY
 236         select CPU_CACHE_VIVT
 237         select CPU_CP15_MMU
 238         select CPU_COPY_V4WB if MMU # can probably do better
 239         select CPU_TLB_V4WBI if MMU
 240         help
 241           The ARM1022E is an implementation of the ARMv5TE architecture
 242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 243           embedded trace macrocell, and a floating-point unit.
 244
 245           Say Y if you want support for the ARM1022E processor.
 246           Otherwise, say N.
 247
 248 # ARM1026EJ-S
 249 config CPU_ARM1026
 250         bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
 251         select CPU_32v5
 252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 253         select CPU_PABRT_LEGACY
 254         select CPU_CACHE_VIVT
 255         select CPU_CP15_MMU
 256         select CPU_COPY_V4WB if MMU # can probably do better
 257         select CPU_TLB_V4WBI if MMU
 258         help
 259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 260           based upon the ARM10 integer core.
 261
 262           Say Y if you want support for the ARM1026EJ-S processor.
 263           Otherwise, say N.
 264
 265 # SA110
 266 config CPU_SA110
 267         bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
 268         select CPU_32v3 if ARCH_RPC
 269         select CPU_32v4 if !ARCH_RPC
 270         select CPU_ABRT_EV4
 271         select CPU_PABRT_LEGACY
 272         select CPU_CACHE_V4WB
 273         select CPU_CACHE_VIVT
 274         select CPU_CP15_MMU
 275         select CPU_COPY_V4WB if MMU
 276         select CPU_TLB_V4WB if MMU
 277         help
 278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 279           is available at five speeds ranging from 100 MHz to 233 MHz.
 280           More information is available at
 281           <http://developer.intel.com/design/strong/sa110.htm>.
 282
 283           Say Y if you want support for the SA-110 processor.
 284           Otherwise, say N.
 285
 286 # SA1100
 287 config CPU_SA1100
 288         bool
 289         select CPU_32v4
 290         select CPU_ABRT_EV4
 291         select CPU_PABRT_LEGACY
 292         select CPU_CACHE_V4WB
 293         select CPU_CACHE_VIVT
 294         select CPU_CP15_MMU
 295         select CPU_TLB_V4WB if MMU
 296
 297 # XScale
 298 config CPU_XSCALE
 299         bool
 300         select CPU_32v5
 301         select CPU_ABRT_EV5T
 302         select CPU_PABRT_LEGACY
 303         select CPU_CACHE_VIVT
 304         select CPU_CP15_MMU
 305         select CPU_TLB_V4WBI if MMU
 306
 307 # XScale Core Version 3
 308 config CPU_XSC3
 309         bool
 310         select CPU_32v5
 311         select CPU_ABRT_EV5T
 312         select CPU_PABRT_LEGACY
 313         select CPU_CACHE_VIVT
 314         select CPU_CP15_MMU
 315         select CPU_TLB_V4WBI if MMU
 316         select IO_36
 317
 318 # Marvell PJ1 (Mohawk)
 319 config CPU_MOHAWK
 320         bool
 321         select CPU_32v5
 322         select CPU_ABRT_EV5T
 323         select CPU_PABRT_LEGACY
 324         select CPU_CACHE_VIVT
 325         select CPU_CP15_MMU
 326         select CPU_TLB_V4WBI if MMU
 327         select CPU_COPY_V4WB if MMU
 328
 329 # Feroceon
 330 config CPU_FEROCEON
 331         bool
 332         select CPU_32v5
 333         select CPU_ABRT_EV5T
 334         select CPU_PABRT_LEGACY
 335         select CPU_CACHE_VIVT
 336         select CPU_CP15_MMU
 337         select CPU_COPY_FEROCEON if MMU
 338         select CPU_TLB_FEROCEON if MMU
 339
 340 config CPU_FEROCEON_OLD_ID
 341         bool "Accept early Feroceon cores with an ARM926 ID"
 342         depends on CPU_FEROCEON && !CPU_ARM926T
 343         default y
 344         help
 345           This enables the usage of some old Feroceon cores
 346           for which the CPU ID is equal to the ARM926 ID.
 347           Relevant for Feroceon-1850 and early Feroceon-2850.
 348
 349 # Marvell PJ4
 350 config CPU_PJ4
 351         bool
 352         select CPU_V7
 353         select ARM_THUMBEE
 354
 355 # ARMv6
 356 config CPU_V6
 357         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 358         select CPU_32v6
 359         select CPU_ABRT_EV6
 360         select CPU_PABRT_V6
 361         select CPU_CACHE_V6
 362         select CPU_CACHE_VIPT
 363         select CPU_CP15_MMU
 364         select CPU_HAS_ASID if MMU
 365         select CPU_COPY_V6 if MMU
 366         select CPU_TLB_V6 if MMU
 367
 368 # ARMv6k
 369 config CPU_V6K
 370         bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 371         select CPU_32v6
 372         select CPU_32v6K
 373         select CPU_ABRT_EV6
 374         select CPU_PABRT_V6
 375         select CPU_CACHE_V6
 376         select CPU_CACHE_VIPT
 377         select CPU_CP15_MMU
 378         select CPU_HAS_ASID if MMU
 379         select CPU_COPY_V6 if MMU
 380         select CPU_TLB_V6 if MMU
 381
 382 # ARMv7
 383 config CPU_V7
 384         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 385         select CPU_32v6K
 386         select CPU_32v7
 387         select CPU_ABRT_EV7
 388         select CPU_PABRT_V7
 389         select CPU_CACHE_V7
 390         select CPU_CACHE_VIPT
 391         select CPU_CP15_MMU
 392         select CPU_HAS_ASID if MMU
 393         select CPU_COPY_V6 if MMU
 394         select CPU_TLB_V7 if MMU
 395
 396 # Figure out what processor architecture version we should be using.
 397 # This defines the compiler instruction set which depends on the machine type.
 398 config CPU_32v3
 399         bool
 400         select TLS_REG_EMUL if SMP || !MMU
 401         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 402         select CPU_USE_DOMAINS if MMU
 403
 404 config CPU_32v4
 405         bool
 406         select TLS_REG_EMUL if SMP || !MMU
 407         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 408         select CPU_USE_DOMAINS if MMU
 409
 410 config CPU_32v4T
 411         bool
 412         select TLS_REG_EMUL if SMP || !MMU
 413         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 414         select CPU_USE_DOMAINS if MMU
 415
 416 config CPU_32v5
 417         bool
 418         select TLS_REG_EMUL if SMP || !MMU
 419         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 420         select CPU_USE_DOMAINS if MMU
 421
 422 config CPU_32v6
 423         bool
 424         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 425         select CPU_USE_DOMAINS if CPU_V6 && MMU
 426
 427 config CPU_32v6K
 428         bool
 429
 430 config CPU_32v7
 431         bool
 432
 433 # The abort model
 434 config CPU_ABRT_NOMMU
 435         bool
 436
 437 config CPU_ABRT_EV4
 438         bool
 439
 440 config CPU_ABRT_EV4T
 441         bool
 442
 443 config CPU_ABRT_LV4T
 444         bool
 445
 446 config CPU_ABRT_EV5T
 447         bool
 448
 449 config CPU_ABRT_EV5TJ
 450         bool
 451
 452 config CPU_ABRT_EV6
 453         bool
 454
 455 config CPU_ABRT_EV7
 456         bool
 457
 458 config CPU_PABRT_LEGACY
 459         bool
 460
 461 config CPU_PABRT_V6
 462         bool
 463
 464 config CPU_PABRT_V7
 465         bool
 466
 467 # The cache model
 468 config CPU_CACHE_V3
 469         bool
 470
 471 config CPU_CACHE_V4
 472         bool
 473
 474 config CPU_CACHE_V4WT
 475         bool
 476
 477 config CPU_CACHE_V4WB
 478         bool
 479
 480 config CPU_CACHE_V6
 481         bool
 482
 483 config CPU_CACHE_V7
 484         bool
 485
 486 config CPU_CACHE_VIVT
 487         bool
 488
 489 config CPU_CACHE_VIPT
 490         bool
 491
 492 config CPU_CACHE_FA
 493         bool
 494
 495 if MMU
 496 # The copy-page model
 497 config CPU_COPY_V4WT
 498         bool
 499
 500 config CPU_COPY_V4WB
 501         bool
 502
 503 config CPU_COPY_FEROCEON
 504         bool
 505
 506 config CPU_COPY_FA
 507         bool
 508
 509 config CPU_COPY_V6
 510         bool
 511
 512 # This selects the TLB model
 513 config CPU_TLB_V4WT
 514         bool
 515         help
 516           ARM Architecture Version 4 TLB with writethrough cache.
 517
 518 config CPU_TLB_V4WB
 519         bool
 520         help
 521           ARM Architecture Version 4 TLB with writeback cache.
 522
 523 config CPU_TLB_V4WBI
 524         bool
 525         help
 526           ARM Architecture Version 4 TLB with writeback cache and invalidate
 527           instruction cache entry.
 528
 529 config CPU_TLB_FEROCEON
 530         bool
 531         help
 532           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 533
 534 config CPU_TLB_FA
 535         bool
 536         help
 537           Faraday ARM FA526 architecture, unified TLB with writeback cache
 538           and invalidate instruction cache entry. Branch target buffer is
 539           also supported.
 540
 541 config CPU_TLB_V6
 542         bool
 543
 544 config CPU_TLB_V7
 545         bool
 546
 547 config VERIFY_PERMISSION_FAULT
 548         bool
 549 endif
 550
 551 config CPU_HAS_ASID
 552         bool
 553         help
 554           This indicates whether the CPU has the ASID register; used to
 555           tag TLB and possibly cache entries.
 556
 557 config CPU_CP15
 558         bool
 559         help
 560           Processor has the CP15 register.
 561
 562 config CPU_CP15_MMU
 563         bool
 564         select CPU_CP15
 565         help
 566           Processor has the CP15 register, which has MMU related registers.
 567
 568 config CPU_CP15_MPU
 569         bool
 570         select CPU_CP15
 571         help
 572           Processor has the CP15 register, which has MPU related registers.
 573
 574 config CPU_USE_DOMAINS
 575         bool
 576         help
 577           This option enables or disables the use of domain switching
 578           via the set_fs() function.
 579
 580 #
 581 # CPU supports 36-bit I/O
 582 #
 583 config IO_36
 584         bool
 585
 586 comment "Processor Features"
 587
 588 config ARM_LPAE
 589         bool "Support for the Large Physical Address Extension"
 590         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
 591                 !CPU_32v4 && !CPU_32v3
 592         help
 593           Say Y if you have an ARMv7 processor supporting the LPAE page
 594           table format and you would like to access memory beyond the
 595           4GB limit. The resulting kernel image will not run on
 596           processors without the LPA extension.
 597
 598           If unsure, say N.
 599
 600 config ARCH_PHYS_ADDR_T_64BIT
 601         def_bool ARM_LPAE
 602
 603 config ARCH_DMA_ADDR_T_64BIT
 604         bool
 605
 606 config ARM_THUMB
 607         bool "Support Thumb user binaries"
 608         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
 609         default y
 610         help
 611           Say Y if you want to include kernel support for running user space
 612           Thumb binaries.
 613
 614           The Thumb instruction set is a compressed form of the standard ARM
 615           instruction set resulting in smaller binaries at the expense of
 616           slightly less efficient code.
 617
 618           If you don't know what this all is, saying Y is a safe choice.
 619
 620 config ARM_THUMBEE
 621         bool "Enable ThumbEE CPU extension"
 622         depends on CPU_V7
 623         help
 624           Say Y here if you have a CPU with the ThumbEE extension and code to
 625           make use of it. Say N for code that can run on CPUs without ThumbEE.
 626
 627 config SWP_EMULATE
 628         bool "Emulate SWP/SWPB instructions"
 629         depends on !CPU_USE_DOMAINS && CPU_V7
 630         select HAVE_PROC_CPU if PROC_FS
 631         default y if SMP
 632         help
 633           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
 634           ARMv7 multiprocessing extensions introduce the ability to disable
 635           these instructions, triggering an undefined instruction exception
 636           when executed. Say Y here to enable software emulation of these
 637           instructions for userspace (not kernel) using LDREX/STREX.
 638           Also creates /proc/cpu/swp_emulation for statistics.
 639
 640           In some older versions of glibc [<=2.8] SWP is used during futex
 641           trylock() operations with the assumption that the code will not
 642           be preempted. This invalid assumption may be more likely to fail
 643           with SWP emulation enabled, leading to deadlock of the user
 644           application.
 645
 646           NOTE: when accessing uncached shared regions, LDREX/STREX rely
 647           on an external transaction monitoring block called a global
 648           monitor to maintain update atomicity. If your system does not
 649           implement a global monitor, this option can cause programs that
 650           perform SWP operations to uncached memory to deadlock.
 651
 652           If unsure, say Y.
 653
 654 config CPU_BIG_ENDIAN
 655         bool "Build big-endian kernel"
 656         depends on ARCH_SUPPORTS_BIG_ENDIAN
 657         help
 658           Say Y if you plan on running a kernel in big-endian mode.
 659           Note that your board must be properly built and your board
 660           port must properly enable any big-endian related features
 661           of your chipset/board/processor.
 662
 663 config CPU_ENDIAN_BE8
 664         bool
 665         depends on CPU_BIG_ENDIAN
 666         default CPU_V6 || CPU_V6K || CPU_V7
 667         help
 668           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 669
 670 config CPU_ENDIAN_BE32
 671         bool
 672         depends on CPU_BIG_ENDIAN
 673         default !CPU_ENDIAN_BE8
 674         help
 675           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 676
 677 config CPU_HIGH_VECTOR
 678         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 679         bool "Select the High exception vector"
 680         help
 681           Say Y here to select high exception vector(0xFFFF0000~).
 682           The exception vector can vary depending on the platform
 683           design in nommu mode. If your platform needs to select
 684           high exception vector, say Y.
 685           Otherwise or if you are unsure, say N, and the low exception
 686           vector (0x00000000~) will be used.
 687
 688 config CPU_ICACHE_DISABLE
 689         bool "Disable I-Cache (I-bit)"
 690         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 691         help
 692           Say Y here to disable the processor instruction cache. Unless
 693           you have a reason not to or are unsure, say N.
 694
 695 config CPU_DCACHE_DISABLE
 696         bool "Disable D-Cache (C-bit)"
 697         depends on CPU_CP15
 698         help
 699           Say Y here to disable the processor data cache. Unless
 700           you have a reason not to or are unsure, say N.
 701
 702 config CPU_DCACHE_SIZE
 703         hex
 704         depends on CPU_ARM740T || CPU_ARM946E
 705         default 0x00001000 if CPU_ARM740T
 706         default 0x00002000 # default size for ARM946E-S
 707         help
 708           Some cores are synthesizable to have various sized cache. For
 709           ARM946E-S case, it can vary from 0KB to 1MB.
 710           To support such cache operations, it is efficient to know the size
 711           before compile time.
 712           If your SoC is configured to have a different size, define the value
 713           here with proper conditions.
 714
 715 config CPU_DCACHE_WRITETHROUGH
 716         bool "Force write through D-cache"
 717         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
 718         default y if CPU_ARM925T
 719         help
 720           Say Y here to use the data cache in writethrough mode. Unless you
 721           specifically require this or are unsure, say N.
 722
 723 config CPU_CACHE_ROUND_ROBIN
 724         bool "Round robin I and D cache replacement algorithm"
 725         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 726         help
 727           Say Y here to use the predictable round-robin cache replacement
 728           policy.  Unless you specifically require this or are unsure, say N.
 729
 730 config CPU_BPREDICT_DISABLE
 731         bool "Disable branch prediction"
 732         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
 733         help
 734           Say Y here to disable branch prediction.  If unsure, say N.
 735
 736 config TLS_REG_EMUL
 737         bool
 738         help
 739           An SMP system using a pre-ARMv6 processor (there are apparently
 740           a few prototypes like that in existence) and therefore access to
 741           that required register must be emulated.
 742
 743 config NEEDS_SYSCALL_FOR_CMPXCHG
 744         bool
 745         help
 746           SMP on a pre-ARMv6 processor?  Well OK then.
 747           Forget about fast user space cmpxchg support.
 748           It is just not possible.
 749
 750 config DMA_CACHE_RWFO
 751         bool "Enable read/write for ownership DMA cache maintenance"
 752         depends on CPU_V6K && SMP
 753         default y
 754         help
 755           The Snoop Control Unit on ARM11MPCore does not detect the
 756           cache maintenance operations and the dma_{map,unmap}_area()
 757           functions may leave stale cache entries on other CPUs. By
 758           enabling this option, Read or Write For Ownership in the ARMv6
 759           DMA cache maintenance functions is performed. These LDR/STR
 760           instructions change the cache line state to shared or modified
 761           so that the cache operation has the desired effect.
 762
 763           Note that the workaround is only valid on processors that do
 764           not perform speculative loads into the D-cache. For such
 765           processors, if cache maintenance operations are not broadcast
 766           in hardware, other workarounds are needed (e.g. cache
 767           maintenance broadcasting in software via FIQ).
 768
 769 config OUTER_CACHE
 770         bool
 771
 772 config OUTER_CACHE_SYNC
 773         bool
 774         help
 775           The outer cache has a outer_cache_fns.sync function pointer
 776           that can be used to drain the write buffer of the outer cache.
 777
 778 config CACHE_FEROCEON_L2
 779         bool "Enable the Feroceon L2 cache controller"
 780         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
 781         default y
 782         select OUTER_CACHE
 783         help
 784           This option enables the Feroceon L2 cache controller.
 785
 786 config CACHE_FEROCEON_L2_WRITETHROUGH
 787         bool "Force Feroceon L2 cache write through"
 788         depends on CACHE_FEROCEON_L2
 789         help
 790           Say Y here to use the Feroceon L2 cache in writethrough mode.
 791           Unless you specifically require this, say N for writeback mode.
 792
 793 config MIGHT_HAVE_CACHE_L2X0
 794         bool
 795         help
 796           This option should be selected by machines which have a L2x0
 797           or PL310 cache controller, but where its use is optional.
 798
 799           The only effect of this option is to make CACHE_L2X0 and
 800           related options available to the user for configuration.
 801
 802           Boards or SoCs which always require the cache controller
 803           support to be present should select CACHE_L2X0 directly
 804           instead of this option, thus preventing the user from
 805           inadvertently configuring a broken kernel.
 806
 807 config CACHE_L2X0
 808         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
 809         default MIGHT_HAVE_CACHE_L2X0
 810         select OUTER_CACHE
 811         select OUTER_CACHE_SYNC
 812         help
 813           This option enables the L2x0 PrimeCell.
 814
 815 config CACHE_PL310
 816         bool
 817         depends on CACHE_L2X0
 818         default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
 819         help
 820           This option enables optimisations for the PL310 cache
 821           controller.
 822
 823 config CACHE_TAUROS2
 824         bool "Enable the Tauros2 L2 cache controller"
 825         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
 826         default y
 827         select OUTER_CACHE
 828         help
 829           This option enables the Tauros2 L2 cache controller (as
 830           found on PJ1/PJ4).
 831
 832 config CACHE_XSC3L2
 833         bool "Enable the L2 cache on XScale3"
 834         depends on CPU_XSC3
 835         default y
 836         select OUTER_CACHE
 837         help
 838           This option enables the L2 cache on XScale3.
 839
 840 config ARM_L1_CACHE_SHIFT_6
 841         bool
 842         default y if CPU_V7
 843         help
 844           Setting ARM L1 cache line size to 64 Bytes.
 845
 846 config ARM_L1_CACHE_SHIFT
 847         int
 848         default 6 if ARM_L1_CACHE_SHIFT_6
 849         default 5
 850
 851 config ARM_DMA_MEM_BUFFERABLE
 852         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
 853         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
 854                      MACH_REALVIEW_PB11MP)
 855         default y if CPU_V6 || CPU_V6K || CPU_V7
 856         help
 857           Historically, the kernel has used strongly ordered mappings to
 858           provide DMA coherent memory.  With the advent of ARMv7, mapping
 859           memory with differing types results in unpredictable behaviour,
 860           so on these CPUs, this option is forced on.
 861
 862           Multiple mappings with differing attributes is also unpredictable
 863           on ARMv6 CPUs, but since they do not have aggressive speculative
 864           prefetch, no harm appears to occur.
 865
 866           However, drivers may be missing the necessary barriers for ARMv6,
 867           and therefore turning this on may result in unpredictable driver
 868           behaviour.  Therefore, we offer this as an option.
 869
 870           You are recommended say 'Y' here and debug any affected drivers.
 871
 872 config ARCH_HAS_BARRIERS
 873         bool
 874         help
 875           This option allows the use of custom mandatory barriers
 876           included via the mach/barriers.h file.