arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 # Select CPU types depending on the architecture selected.  This selects
   4 # which CPUs we support in the kernel image, and the compiler instruction
   5 # optimiser behaviour.
   6
   7 # ARM7TDMI
   8 config CPU_ARM7TDMI
   9         bool "Support ARM7TDMI processor"
  10         depends on !MMU
  11         select CPU_32v4T
  12         select CPU_ABRT_LV4T
  13         select CPU_CACHE_V4
  14         select CPU_PABRT_LEGACY
  15         help
  16           A 32-bit RISC microprocessor based on the ARM7 processor core
  17           which has no memory control unit and cache.
  18
  19           Say Y if you want support for the ARM7TDMI processor.
  20           Otherwise, say N.
  21
  22 # ARM720T
  23 config CPU_ARM720T
  24         bool "Support ARM720T processor" if ARCH_INTEGRATOR
  25         select CPU_32v4T
  26         select CPU_ABRT_LV4T
  27         select CPU_CACHE_V4
  28         select CPU_CACHE_VIVT
  29         select CPU_COPY_V4WT if MMU
  30         select CPU_CP15_MMU
  31         select CPU_PABRT_LEGACY
  32         select CPU_TLB_V4WT if MMU
  33         help
  34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  35           MMU built around an ARM7TDMI core.
  36
  37           Say Y if you want support for the ARM720T processor.
  38           Otherwise, say N.
  39
  40 # ARM740T
  41 config CPU_ARM740T
  42         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  43         depends on !MMU
  44         select CPU_32v4T
  45         select CPU_ABRT_LV4T
  46         select CPU_CACHE_V4
  47         select CPU_CP15_MPU
  48         select CPU_PABRT_LEGACY
  49         help
  50           A 32-bit RISC processor with 8KB cache or 4KB variants,
  51           write buffer and MPU(Protection Unit) built around
  52           an ARM7TDMI core.
  53
  54           Say Y if you want support for the ARM740T processor.
  55           Otherwise, say N.
  56
  57 # ARM9TDMI
  58 config CPU_ARM9TDMI
  59         bool "Support ARM9TDMI processor"
  60         depends on !MMU
  61         select CPU_32v4T
  62         select CPU_ABRT_NOMMU
  63         select CPU_CACHE_V4
  64         select CPU_PABRT_LEGACY
  65         help
  66           A 32-bit RISC microprocessor based on the ARM9 processor core
  67           which has no memory control unit and cache.
  68
  69           Say Y if you want support for the ARM9TDMI processor.
  70           Otherwise, say N.
  71
  72 # ARM920T
  73 config CPU_ARM920T
  74         bool "Support ARM920T processor" if ARCH_INTEGRATOR
  75         select CPU_32v4T
  76         select CPU_ABRT_EV4T
  77         select CPU_CACHE_V4WT
  78         select CPU_CACHE_VIVT
  79         select CPU_COPY_V4WB if MMU
  80         select CPU_CP15_MMU
  81         select CPU_PABRT_LEGACY
  82         select CPU_TLB_V4WBI if MMU
  83         help
  84           The ARM920T is licensed to be produced by numerous vendors,
  85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
  86
  87           Say Y if you want support for the ARM920T processor.
  88           Otherwise, say N.
  89
  90 # ARM922T
  91 config CPU_ARM922T
  92         bool "Support ARM922T processor" if ARCH_INTEGRATOR
  93         select CPU_32v4T
  94         select CPU_ABRT_EV4T
  95         select CPU_CACHE_V4WT
  96         select CPU_CACHE_VIVT
  97         select CPU_COPY_V4WB if MMU
  98         select CPU_CP15_MMU
  99         select CPU_PABRT_LEGACY
 100         select CPU_TLB_V4WBI if MMU
 101         help
 102           The ARM922T is a version of the ARM920T, but with smaller
 103           instruction and data caches. It is used in Altera's
 104           Excalibur XA device family and Micrel's KS8695 Centaur.
 105
 106           Say Y if you want support for the ARM922T processor.
 107           Otherwise, say N.
 108
 109 # ARM925T
 110 config CPU_ARM925T
 111         bool "Support ARM925T processor" if ARCH_OMAP1
 112         select CPU_32v4T
 113         select CPU_ABRT_EV4T
 114         select CPU_CACHE_V4WT
 115         select CPU_CACHE_VIVT
 116         select CPU_COPY_V4WB if MMU
 117         select CPU_CP15_MMU
 118         select CPU_PABRT_LEGACY
 119         select CPU_TLB_V4WBI if MMU
 120         help
 121           The ARM925T is a mix between the ARM920T and ARM926T, but with
 122           different instruction and data caches. It is used in TI's OMAP
 123           device family.
 124
 125           Say Y if you want support for the ARM925T processor.
 126           Otherwise, say N.
 127
 128 # ARM926T
 129 config CPU_ARM926T
 130         bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
 131         select CPU_32v5
 132         select CPU_ABRT_EV5TJ
 133         select CPU_CACHE_VIVT
 134         select CPU_COPY_V4WB if MMU
 135         select CPU_CP15_MMU
 136         select CPU_PABRT_LEGACY
 137         select CPU_TLB_V4WBI if MMU
 138         help
 139           This is a variant of the ARM920.  It has slightly different
 140           instruction sequences for cache and TLB operations.  Curiously,
 141           there is no documentation on it at the ARM corporate website.
 142
 143           Say Y if you want support for the ARM926T processor.
 144           Otherwise, say N.
 145
 146 # FA526
 147 config CPU_FA526
 148         bool
 149         select CPU_32v4
 150         select CPU_ABRT_EV4
 151         select CPU_CACHE_FA
 152         select CPU_CACHE_VIVT
 153         select CPU_COPY_FA if MMU
 154         select CPU_CP15_MMU
 155         select CPU_PABRT_LEGACY
 156         select CPU_TLB_FA if MMU
 157         help
 158           The FA526 is a version of the ARMv4 compatible processor with
 159           Branch Target Buffer, Unified TLB and cache line size 16.
 160
 161           Say Y if you want support for the FA526 processor.
 162           Otherwise, say N.
 163
 164 # ARM940T
 165 config CPU_ARM940T
 166         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 167         depends on !MMU
 168         select CPU_32v4T
 169         select CPU_ABRT_NOMMU
 170         select CPU_CACHE_VIVT
 171         select CPU_CP15_MPU
 172         select CPU_PABRT_LEGACY
 173         help
 174           ARM940T is a member of the ARM9TDMI family of general-
 175           purpose microprocessors with MPU and separate 4KB
 176           instruction and 4KB data cases, each with a 4-word line
 177           length.
 178
 179           Say Y if you want support for the ARM940T processor.
 180           Otherwise, say N.
 181
 182 # ARM946E-S
 183 config CPU_ARM946E
 184         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 185         depends on !MMU
 186         select CPU_32v5
 187         select CPU_ABRT_NOMMU
 188         select CPU_CACHE_VIVT
 189         select CPU_CP15_MPU
 190         select CPU_PABRT_LEGACY
 191         help
 192           ARM946E-S is a member of the ARM9E-S family of high-
 193           performance, 32-bit system-on-chip processor solutions.
 194           The TCM and ARMv5TE 32-bit instruction set is supported.
 195
 196           Say Y if you want support for the ARM946E-S processor.
 197           Otherwise, say N.
 198
 199 # ARM1020 - needs validating
 200 config CPU_ARM1020
 201         bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
 202         select CPU_32v5
 203         select CPU_ABRT_EV4T
 204         select CPU_CACHE_V4WT
 205         select CPU_CACHE_VIVT
 206         select CPU_COPY_V4WB if MMU
 207         select CPU_CP15_MMU
 208         select CPU_PABRT_LEGACY
 209         select CPU_TLB_V4WBI if MMU
 210         help
 211           The ARM1020 is the 32K cached version of the ARM10 processor,
 212           with an addition of a floating-point unit.
 213
 214           Say Y if you want support for the ARM1020 processor.
 215           Otherwise, say N.
 216
 217 # ARM1020E - needs validating
 218 config CPU_ARM1020E
 219         bool "Support ARM1020E processor" if ARCH_INTEGRATOR
 220         depends on n
 221         select CPU_32v5
 222         select CPU_ABRT_EV4T
 223         select CPU_CACHE_V4WT
 224         select CPU_CACHE_VIVT
 225         select CPU_COPY_V4WB if MMU
 226         select CPU_CP15_MMU
 227         select CPU_PABRT_LEGACY
 228         select CPU_TLB_V4WBI if MMU
 229
 230 # ARM1022E
 231 config CPU_ARM1022
 232         bool "Support ARM1022E processor" if ARCH_INTEGRATOR
 233         select CPU_32v5
 234         select CPU_ABRT_EV4T
 235         select CPU_CACHE_VIVT
 236         select CPU_COPY_V4WB if MMU # can probably do better
 237         select CPU_CP15_MMU
 238         select CPU_PABRT_LEGACY
 239         select CPU_TLB_V4WBI if MMU
 240         help
 241           The ARM1022E is an implementation of the ARMv5TE architecture
 242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 243           embedded trace macrocell, and a floating-point unit.
 244
 245           Say Y if you want support for the ARM1022E processor.
 246           Otherwise, say N.
 247
 248 # ARM1026EJ-S
 249 config CPU_ARM1026
 250         bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
 251         select CPU_32v5
 252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 253         select CPU_CACHE_VIVT
 254         select CPU_COPY_V4WB if MMU # can probably do better
 255         select CPU_CP15_MMU
 256         select CPU_PABRT_LEGACY
 257         select CPU_TLB_V4WBI if MMU
 258         help
 259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 260           based upon the ARM10 integer core.
 261
 262           Say Y if you want support for the ARM1026EJ-S processor.
 263           Otherwise, say N.
 264
 265 # SA110
 266 config CPU_SA110
 267         bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
 268         select CPU_32v3 if ARCH_RPC
 269         select CPU_32v4 if !ARCH_RPC
 270         select CPU_ABRT_EV4
 271         select CPU_CACHE_V4WB
 272         select CPU_CACHE_VIVT
 273         select CPU_COPY_V4WB if MMU
 274         select CPU_CP15_MMU
 275         select CPU_PABRT_LEGACY
 276         select CPU_TLB_V4WB if MMU
 277         help
 278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 279           is available at five speeds ranging from 100 MHz to 233 MHz.
 280           More information is available at
 281           <http://developer.intel.com/design/strong/sa110.htm>.
 282
 283           Say Y if you want support for the SA-110 processor.
 284           Otherwise, say N.
 285
 286 # SA1100
 287 config CPU_SA1100
 288         bool
 289         select CPU_32v4
 290         select CPU_ABRT_EV4
 291         select CPU_CACHE_V4WB
 292         select CPU_CACHE_VIVT
 293         select CPU_CP15_MMU
 294         select CPU_PABRT_LEGACY
 295         select CPU_TLB_V4WB if MMU
 296
 297 # XScale
 298 config CPU_XSCALE
 299         bool
 300         select CPU_32v5
 301         select CPU_ABRT_EV5T
 302         select CPU_CACHE_VIVT
 303         select CPU_CP15_MMU
 304         select CPU_PABRT_LEGACY
 305         select CPU_TLB_V4WBI if MMU
 306
 307 # XScale Core Version 3
 308 config CPU_XSC3
 309         bool
 310         select CPU_32v5
 311         select CPU_ABRT_EV5T
 312         select CPU_CACHE_VIVT
 313         select CPU_CP15_MMU
 314         select CPU_PABRT_LEGACY
 315         select CPU_TLB_V4WBI if MMU
 316         select IO_36
 317
 318 # Marvell PJ1 (Mohawk)
 319 config CPU_MOHAWK
 320         bool
 321         select CPU_32v5
 322         select CPU_ABRT_EV5T
 323         select CPU_CACHE_VIVT
 324         select CPU_COPY_V4WB if MMU
 325         select CPU_CP15_MMU
 326         select CPU_PABRT_LEGACY
 327         select CPU_TLB_V4WBI if MMU
 328
 329 # Feroceon
 330 config CPU_FEROCEON
 331         bool
 332         select CPU_32v5
 333         select CPU_ABRT_EV5T
 334         select CPU_CACHE_VIVT
 335         select CPU_COPY_FEROCEON if MMU
 336         select CPU_CP15_MMU
 337         select CPU_PABRT_LEGACY
 338         select CPU_TLB_FEROCEON if MMU
 339
 340 config CPU_FEROCEON_OLD_ID
 341         bool "Accept early Feroceon cores with an ARM926 ID"
 342         depends on CPU_FEROCEON && !CPU_ARM926T
 343         default y
 344         help
 345           This enables the usage of some old Feroceon cores
 346           for which the CPU ID is equal to the ARM926 ID.
 347           Relevant for Feroceon-1850 and early Feroceon-2850.
 348
 349 # Marvell PJ4
 350 config CPU_PJ4
 351         bool
 352         select ARM_THUMBEE
 353         select CPU_V7
 354
 355 config CPU_PJ4B
 356         bool
 357         select CPU_V7
 358
 359 # ARMv6
 360 config CPU_V6
 361         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 362         select CPU_32v6
 363         select CPU_ABRT_EV6
 364         select CPU_CACHE_V6
 365         select CPU_CACHE_VIPT
 366         select CPU_COPY_V6 if MMU
 367         select CPU_CP15_MMU
 368         select CPU_HAS_ASID if MMU
 369         select CPU_PABRT_V6
 370         select CPU_TLB_V6 if MMU
 371
 372 # ARMv6k
 373 config CPU_V6K
 374         bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 375         select CPU_32v6
 376         select CPU_32v6K
 377         select CPU_ABRT_EV6
 378         select CPU_CACHE_V6
 379         select CPU_CACHE_VIPT
 380         select CPU_COPY_V6 if MMU
 381         select CPU_CP15_MMU
 382         select CPU_HAS_ASID if MMU
 383         select CPU_PABRT_V6
 384         select CPU_TLB_V6 if MMU
 385
 386 # ARMv7
 387 config CPU_V7
 388         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 389         select CPU_32v6K
 390         select CPU_32v7
 391         select CPU_ABRT_EV7
 392         select CPU_CACHE_V7
 393         select CPU_CACHE_VIPT
 394         select CPU_COPY_V6 if MMU
 395         select CPU_CP15_MMU if MMU
 396         select CPU_CP15_MPU if !MMU
 397         select CPU_HAS_ASID if MMU
 398         select CPU_PABRT_V7
 399         select CPU_TLB_V7 if MMU
 400
 401 # ARMv7M
 402 config CPU_V7M
 403         bool
 404         select CPU_32v7M
 405         select CPU_ABRT_NOMMU
 406         select CPU_CACHE_NOP
 407         select CPU_PABRT_LEGACY
 408         select CPU_THUMBONLY
 409
 410 config CPU_THUMBONLY
 411         bool
 412         # There are no CPUs available with MMU that don't implement an ARM ISA:
 413         depends on !MMU
 414         help
 415           Select this if your CPU doesn't support the 32 bit ARM instructions.
 416
 417 # Figure out what processor architecture version we should be using.
 418 # This defines the compiler instruction set which depends on the machine type.
 419 config CPU_32v3
 420         bool
 421         select CPU_USE_DOMAINS if MMU
 422         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 423         select TLS_REG_EMUL if SMP || !MMU
 424
 425 config CPU_32v4
 426         bool
 427         select CPU_USE_DOMAINS if MMU
 428         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 429         select TLS_REG_EMUL if SMP || !MMU
 430
 431 config CPU_32v4T
 432         bool
 433         select CPU_USE_DOMAINS if MMU
 434         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 435         select TLS_REG_EMUL if SMP || !MMU
 436
 437 config CPU_32v5
 438         bool
 439         select CPU_USE_DOMAINS if MMU
 440         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 441         select TLS_REG_EMUL if SMP || !MMU
 442
 443 config CPU_32v6
 444         bool
 445         select CPU_USE_DOMAINS if CPU_V6 && MMU
 446         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 447
 448 config CPU_32v6K
 449         bool
 450
 451 config CPU_32v7
 452         bool
 453
 454 config CPU_32v7M
 455         bool
 456
 457 # The abort model
 458 config CPU_ABRT_NOMMU
 459         bool
 460
 461 config CPU_ABRT_EV4
 462         bool
 463
 464 config CPU_ABRT_EV4T
 465         bool
 466
 467 config CPU_ABRT_LV4T
 468         bool
 469
 470 config CPU_ABRT_EV5T
 471         bool
 472
 473 config CPU_ABRT_EV5TJ
 474         bool
 475
 476 config CPU_ABRT_EV6
 477         bool
 478
 479 config CPU_ABRT_EV7
 480         bool
 481
 482 config CPU_PABRT_LEGACY
 483         bool
 484
 485 config CPU_PABRT_V6
 486         bool
 487
 488 config CPU_PABRT_V7
 489         bool
 490
 491 # The cache model
 492 config CPU_CACHE_V4
 493         bool
 494
 495 config CPU_CACHE_V4WT
 496         bool
 497
 498 config CPU_CACHE_V4WB
 499         bool
 500
 501 config CPU_CACHE_V6
 502         bool
 503
 504 config CPU_CACHE_V7
 505         bool
 506
 507 config CPU_CACHE_NOP
 508         bool
 509
 510 config CPU_CACHE_VIVT
 511         bool
 512
 513 config CPU_CACHE_VIPT
 514         bool
 515
 516 config CPU_CACHE_FA
 517         bool
 518
 519 if MMU
 520 # The copy-page model
 521 config CPU_COPY_V4WT
 522         bool
 523
 524 config CPU_COPY_V4WB
 525         bool
 526
 527 config CPU_COPY_FEROCEON
 528         bool
 529
 530 config CPU_COPY_FA
 531         bool
 532
 533 config CPU_COPY_V6
 534         bool
 535
 536 # This selects the TLB model
 537 config CPU_TLB_V4WT
 538         bool
 539         help
 540           ARM Architecture Version 4 TLB with writethrough cache.
 541
 542 config CPU_TLB_V4WB
 543         bool
 544         help
 545           ARM Architecture Version 4 TLB with writeback cache.
 546
 547 config CPU_TLB_V4WBI
 548         bool
 549         help
 550           ARM Architecture Version 4 TLB with writeback cache and invalidate
 551           instruction cache entry.
 552
 553 config CPU_TLB_FEROCEON
 554         bool
 555         help
 556           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 557
 558 config CPU_TLB_FA
 559         bool
 560         help
 561           Faraday ARM FA526 architecture, unified TLB with writeback cache
 562           and invalidate instruction cache entry. Branch target buffer is
 563           also supported.
 564
 565 config CPU_TLB_V6
 566         bool
 567
 568 config CPU_TLB_V7
 569         bool
 570
 571 config VERIFY_PERMISSION_FAULT
 572         bool
 573 endif
 574
 575 config CPU_HAS_ASID
 576         bool
 577         help
 578           This indicates whether the CPU has the ASID register; used to
 579           tag TLB and possibly cache entries.
 580
 581 config CPU_CP15
 582         bool
 583         help
 584           Processor has the CP15 register.
 585
 586 config CPU_CP15_MMU
 587         bool
 588         select CPU_CP15
 589         help
 590           Processor has the CP15 register, which has MMU related registers.
 591
 592 config CPU_CP15_MPU
 593         bool
 594         select CPU_CP15
 595         help
 596           Processor has the CP15 register, which has MPU related registers.
 597
 598 config CPU_USE_DOMAINS
 599         bool
 600         help
 601           This option enables or disables the use of domain switching
 602           via the set_fs() function.
 603
 604 #
 605 # CPU supports 36-bit I/O
 606 #
 607 config IO_36
 608         bool
 609
 610 comment "Processor Features"
 611
 612 config ARM_LPAE
 613         bool "Support for the Large Physical Address Extension"
 614         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
 615                 !CPU_32v4 && !CPU_32v3
 616         help
 617           Say Y if you have an ARMv7 processor supporting the LPAE page
 618           table format and you would like to access memory beyond the
 619           4GB limit. The resulting kernel image will not run on
 620           processors without the LPA extension.
 621
 622           If unsure, say N.
 623
 624 config ARCH_PHYS_ADDR_T_64BIT
 625         def_bool ARM_LPAE
 626
 627 config ARCH_DMA_ADDR_T_64BIT
 628         bool
 629
 630 config ARM_THUMB
 631         bool "Support Thumb user binaries" if !CPU_THUMBONLY
 632         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
 633                 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
 634                 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 635                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
 636                 CPU_V7 || CPU_FEROCEON || CPU_V7M
 637         default y
 638         help
 639           Say Y if you want to include kernel support for running user space
 640           Thumb binaries.
 641
 642           The Thumb instruction set is a compressed form of the standard ARM
 643           instruction set resulting in smaller binaries at the expense of
 644           slightly less efficient code.
 645
 646           If you don't know what this all is, saying Y is a safe choice.
 647
 648 config ARM_THUMBEE
 649         bool "Enable ThumbEE CPU extension"
 650         depends on CPU_V7
 651         help
 652           Say Y here if you have a CPU with the ThumbEE extension and code to
 653           make use of it. Say N for code that can run on CPUs without ThumbEE.
 654
 655 config ARM_VIRT_EXT
 656         bool
 657         depends on MMU
 658         default y if CPU_V7
 659         help
 660           Enable the kernel to make use of the ARM Virtualization
 661           Extensions to install hypervisors without run-time firmware
 662           assistance.
 663
 664           A compliant bootloader is required in order to make maximum
 665           use of this feature.  Refer to Documentation/arm/Booting for
 666           details.
 667
 668 config SWP_EMULATE
 669         bool "Emulate SWP/SWPB instructions"
 670         depends on !CPU_USE_DOMAINS && CPU_V7
 671         default y if SMP
 672         select HAVE_PROC_CPU if PROC_FS
 673         help
 674           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
 675           ARMv7 multiprocessing extensions introduce the ability to disable
 676           these instructions, triggering an undefined instruction exception
 677           when executed. Say Y here to enable software emulation of these
 678           instructions for userspace (not kernel) using LDREX/STREX.
 679           Also creates /proc/cpu/swp_emulation for statistics.
 680
 681           In some older versions of glibc [<=2.8] SWP is used during futex
 682           trylock() operations with the assumption that the code will not
 683           be preempted. This invalid assumption may be more likely to fail
 684           with SWP emulation enabled, leading to deadlock of the user
 685           application.
 686
 687           NOTE: when accessing uncached shared regions, LDREX/STREX rely
 688           on an external transaction monitoring block called a global
 689           monitor to maintain update atomicity. If your system does not
 690           implement a global monitor, this option can cause programs that
 691           perform SWP operations to uncached memory to deadlock.
 692
 693           If unsure, say Y.
 694
 695 config CPU_BIG_ENDIAN
 696         bool "Build big-endian kernel"
 697         depends on ARCH_SUPPORTS_BIG_ENDIAN
 698         help
 699           Say Y if you plan on running a kernel in big-endian mode.
 700           Note that your board must be properly built and your board
 701           port must properly enable any big-endian related features
 702           of your chipset/board/processor.
 703
 704 config CPU_ENDIAN_BE8
 705         bool
 706         depends on CPU_BIG_ENDIAN
 707         default CPU_V6 || CPU_V6K || CPU_V7
 708         help
 709           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 710
 711 config CPU_ENDIAN_BE32
 712         bool
 713         depends on CPU_BIG_ENDIAN
 714         default !CPU_ENDIAN_BE8
 715         help
 716           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 717
 718 config CPU_HIGH_VECTOR
 719         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 720         bool "Select the High exception vector"
 721         help
 722           Say Y here to select high exception vector(0xFFFF0000~).
 723           The exception vector can vary depending on the platform
 724           design in nommu mode. If your platform needs to select
 725           high exception vector, say Y.
 726           Otherwise or if you are unsure, say N, and the low exception
 727           vector (0x00000000~) will be used.
 728
 729 config CPU_ICACHE_DISABLE
 730         bool "Disable I-Cache (I-bit)"
 731         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 732         help
 733           Say Y here to disable the processor instruction cache. Unless
 734           you have a reason not to or are unsure, say N.
 735
 736 config CPU_DCACHE_DISABLE
 737         bool "Disable D-Cache (C-bit)"
 738         depends on CPU_CP15
 739         help
 740           Say Y here to disable the processor data cache. Unless
 741           you have a reason not to or are unsure, say N.
 742
 743 config CPU_DCACHE_SIZE
 744         hex
 745         depends on CPU_ARM740T || CPU_ARM946E
 746         default 0x00001000 if CPU_ARM740T
 747         default 0x00002000 # default size for ARM946E-S
 748         help
 749           Some cores are synthesizable to have various sized cache. For
 750           ARM946E-S case, it can vary from 0KB to 1MB.
 751           To support such cache operations, it is efficient to know the size
 752           before compile time.
 753           If your SoC is configured to have a different size, define the value
 754           here with proper conditions.
 755
 756 config CPU_DCACHE_WRITETHROUGH
 757         bool "Force write through D-cache"
 758         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
 759         default y if CPU_ARM925T
 760         help
 761           Say Y here to use the data cache in writethrough mode. Unless you
 762           specifically require this or are unsure, say N.
 763
 764 config CPU_CACHE_ROUND_ROBIN
 765         bool "Round robin I and D cache replacement algorithm"
 766         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 767         help
 768           Say Y here to use the predictable round-robin cache replacement
 769           policy.  Unless you specifically require this or are unsure, say N.
 770
 771 config CPU_BPREDICT_DISABLE
 772         bool "Disable branch prediction"
 773         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
 774         help
 775           Say Y here to disable branch prediction.  If unsure, say N.
 776
 777 config TLS_REG_EMUL
 778         bool
 779         help
 780           An SMP system using a pre-ARMv6 processor (there are apparently
 781           a few prototypes like that in existence) and therefore access to
 782           that required register must be emulated.
 783
 784 config NEEDS_SYSCALL_FOR_CMPXCHG
 785         bool
 786         help
 787           SMP on a pre-ARMv6 processor?  Well OK then.
 788           Forget about fast user space cmpxchg support.
 789           It is just not possible.
 790
 791 config DMA_CACHE_RWFO
 792         bool "Enable read/write for ownership DMA cache maintenance"
 793         depends on CPU_V6K && SMP
 794         default y
 795         help
 796           The Snoop Control Unit on ARM11MPCore does not detect the
 797           cache maintenance operations and the dma_{map,unmap}_area()
 798           functions may leave stale cache entries on other CPUs. By
 799           enabling this option, Read or Write For Ownership in the ARMv6
 800           DMA cache maintenance functions is performed. These LDR/STR
 801           instructions change the cache line state to shared or modified
 802           so that the cache operation has the desired effect.
 803
 804           Note that the workaround is only valid on processors that do
 805           not perform speculative loads into the D-cache. For such
 806           processors, if cache maintenance operations are not broadcast
 807           in hardware, other workarounds are needed (e.g. cache
 808           maintenance broadcasting in software via FIQ).
 809
 810 config OUTER_CACHE
 811         bool
 812
 813 config OUTER_CACHE_SYNC
 814         bool
 815         help
 816           The outer cache has a outer_cache_fns.sync function pointer
 817           that can be used to drain the write buffer of the outer cache.
 818
 819 config CACHE_FEROCEON_L2
 820         bool "Enable the Feroceon L2 cache controller"
 821         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
 822         default y
 823         select OUTER_CACHE
 824         help
 825           This option enables the Feroceon L2 cache controller.
 826
 827 config CACHE_FEROCEON_L2_WRITETHROUGH
 828         bool "Force Feroceon L2 cache write through"
 829         depends on CACHE_FEROCEON_L2
 830         help
 831           Say Y here to use the Feroceon L2 cache in writethrough mode.
 832           Unless you specifically require this, say N for writeback mode.
 833
 834 config MIGHT_HAVE_CACHE_L2X0
 835         bool
 836         help
 837           This option should be selected by machines which have a L2x0
 838           or PL310 cache controller, but where its use is optional.
 839
 840           The only effect of this option is to make CACHE_L2X0 and
 841           related options available to the user for configuration.
 842
 843           Boards or SoCs which always require the cache controller
 844           support to be present should select CACHE_L2X0 directly
 845           instead of this option, thus preventing the user from
 846           inadvertently configuring a broken kernel.
 847
 848 config CACHE_L2X0
 849         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
 850         default MIGHT_HAVE_CACHE_L2X0
 851         select OUTER_CACHE
 852         select OUTER_CACHE_SYNC
 853         help
 854           This option enables the L2x0 PrimeCell.
 855
 856 config CACHE_PL310
 857         bool
 858         depends on CACHE_L2X0
 859         default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
 860         help
 861           This option enables optimisations for the PL310 cache
 862           controller.
 863
 864 config CACHE_TAUROS2
 865         bool "Enable the Tauros2 L2 cache controller"
 866         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
 867         default y
 868         select OUTER_CACHE
 869         help
 870           This option enables the Tauros2 L2 cache controller (as
 871           found on PJ1/PJ4).
 872
 873 config CACHE_XSC3L2
 874         bool "Enable the L2 cache on XScale3"
 875         depends on CPU_XSC3
 876         default y
 877         select OUTER_CACHE
 878         help
 879           This option enables the L2 cache on XScale3.
 880
 881 config ARM_L1_CACHE_SHIFT_6
 882         bool
 883         default y if CPU_V7
 884         help
 885           Setting ARM L1 cache line size to 64 Bytes.
 886
 887 config ARM_L1_CACHE_SHIFT
 888         int
 889         default 6 if ARM_L1_CACHE_SHIFT_6
 890         default 5
 891
 892 config ARM_DMA_MEM_BUFFERABLE
 893         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
 894         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
 895                      MACH_REALVIEW_PB11MP)
 896         default y if CPU_V6 || CPU_V6K || CPU_V7
 897         help
 898           Historically, the kernel has used strongly ordered mappings to
 899           provide DMA coherent memory.  With the advent of ARMv7, mapping
 900           memory with differing types results in unpredictable behaviour,
 901           so on these CPUs, this option is forced on.
 902
 903           Multiple mappings with differing attributes is also unpredictable
 904           on ARMv6 CPUs, but since they do not have aggressive speculative
 905           prefetch, no harm appears to occur.
 906
 907           However, drivers may be missing the necessary barriers for ARMv6,
 908           and therefore turning this on may result in unpredictable driver
 909           behaviour.  Therefore, we offer this as an option.
 910
 911           You are recommended say 'Y' here and debug any affected drivers.
 912
 913 config ARCH_HAS_BARRIERS
 914         bool
 915         help
 916           This option allows the use of custom mandatory barriers
 917           included via the mach/barriers.h file.