arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor" if ARCH_RPC
  14         select CPU_32v3
  15         select CPU_CACHE_V3
  16         select CPU_CACHE_VIVT
  17         select CPU_CP15_MMU
  18         select CPU_COPY_V3 if MMU
  19         select CPU_TLB_V3 if MMU
  20         select CPU_PABRT_LEGACY
  21         help
  22           The ARM610 is the successor to the ARM3 processor
  23           and was produced by VLSI Technology Inc.
  24
  25           Say Y if you want support for the ARM610 processor.
  26           Otherwise, say N.
  27
  28 # ARM7TDMI
  29 config CPU_ARM7TDMI
  30         bool "Support ARM7TDMI processor"
  31         depends on !MMU
  32         select CPU_32v4T
  33         select CPU_ABRT_LV4T
  34         select CPU_PABRT_LEGACY
  35         select CPU_CACHE_V4
  36         help
  37           A 32-bit RISC microprocessor based on the ARM7 processor core
  38           which has no memory control unit and cache.
  39
  40           Say Y if you want support for the ARM7TDMI processor.
  41           Otherwise, say N.
  42
  43 # ARM710
  44 config CPU_ARM710
  45         bool "Support ARM710 processor" if ARCH_RPC
  46         select CPU_32v3
  47         select CPU_CACHE_V3
  48         select CPU_CACHE_VIVT
  49         select CPU_CP15_MMU
  50         select CPU_COPY_V3 if MMU
  51         select CPU_TLB_V3 if MMU
  52         select CPU_PABRT_LEGACY
  53         help
  54           A 32-bit RISC microprocessor based on the ARM7 processor core
  55           designed by Advanced RISC Machines Ltd. The ARM710 is the
  56           successor to the ARM610 processor. It was released in
  57           July 1994 by VLSI Technology Inc.
  58
  59           Say Y if you want support for the ARM710 processor.
  60           Otherwise, say N.
  61
  62 # ARM720T
  63 config CPU_ARM720T
  64         bool "Support ARM720T processor" if ARCH_INTEGRATOR
  65         select CPU_32v4T
  66         select CPU_ABRT_LV4T
  67         select CPU_PABRT_LEGACY
  68         select CPU_CACHE_V4
  69         select CPU_CACHE_VIVT
  70         select CPU_CP15_MMU
  71         select CPU_COPY_V4WT if MMU
  72         select CPU_TLB_V4WT if MMU
  73         help
  74           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  75           MMU built around an ARM7TDMI core.
  76
  77           Say Y if you want support for the ARM720T processor.
  78           Otherwise, say N.
  79
  80 # ARM740T
  81 config CPU_ARM740T
  82         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  83         depends on !MMU
  84         select CPU_32v4T
  85         select CPU_ABRT_LV4T
  86         select CPU_PABRT_LEGACY
  87         select CPU_CACHE_V3     # although the core is v4t
  88         select CPU_CP15_MPU
  89         help
  90           A 32-bit RISC processor with 8KB cache or 4KB variants,
  91           write buffer and MPU(Protection Unit) built around
  92           an ARM7TDMI core.
  93
  94           Say Y if you want support for the ARM740T processor.
  95           Otherwise, say N.
  96
  97 # ARM9TDMI
  98 config CPU_ARM9TDMI
  99         bool "Support ARM9TDMI processor"
 100         depends on !MMU
 101         select CPU_32v4T
 102         select CPU_ABRT_NOMMU
 103         select CPU_PABRT_LEGACY
 104         select CPU_CACHE_V4
 105         help
 106           A 32-bit RISC microprocessor based on the ARM9 processor core
 107           which has no memory control unit and cache.
 108
 109           Say Y if you want support for the ARM9TDMI processor.
 110           Otherwise, say N.
 111
 112 # ARM920T
 113 config CPU_ARM920T
 114         bool "Support ARM920T processor" if ARCH_INTEGRATOR
 115         select CPU_32v4T
 116         select CPU_ABRT_EV4T
 117         select CPU_PABRT_LEGACY
 118         select CPU_CACHE_V4WT
 119         select CPU_CACHE_VIVT
 120         select CPU_CP15_MMU
 121         select CPU_COPY_V4WB if MMU
 122         select CPU_TLB_V4WBI if MMU
 123         help
 124           The ARM920T is licensed to be produced by numerous vendors,
 125           and is used in the Maverick EP9312 and the Samsung S3C2410.
 126
 127           More information on the Maverick EP9312 at
 128           <http://linuxdevices.com/products/PD2382866068.html>.
 129
 130           Say Y if you want support for the ARM920T processor.
 131           Otherwise, say N.
 132
 133 # ARM922T
 134 config CPU_ARM922T
 135         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 136         select CPU_32v4T
 137         select CPU_ABRT_EV4T
 138         select CPU_PABRT_LEGACY
 139         select CPU_CACHE_V4WT
 140         select CPU_CACHE_VIVT
 141         select CPU_CP15_MMU
 142         select CPU_COPY_V4WB if MMU
 143         select CPU_TLB_V4WBI if MMU
 144         help
 145           The ARM922T is a version of the ARM920T, but with smaller
 146           instruction and data caches. It is used in Altera's
 147           Excalibur XA device family and Micrel's KS8695 Centaur.
 148
 149           Say Y if you want support for the ARM922T processor.
 150           Otherwise, say N.
 151
 152 # ARM925T
 153 config CPU_ARM925T
 154         bool "Support ARM925T processor" if ARCH_OMAP1
 155         select CPU_32v4T
 156         select CPU_ABRT_EV4T
 157         select CPU_PABRT_LEGACY
 158         select CPU_CACHE_V4WT
 159         select CPU_CACHE_VIVT
 160         select CPU_CP15_MMU
 161         select CPU_COPY_V4WB if MMU
 162         select CPU_TLB_V4WBI if MMU
 163         help
 164           The ARM925T is a mix between the ARM920T and ARM926T, but with
 165           different instruction and data caches. It is used in TI's OMAP
 166           device family.
 167
 168           Say Y if you want support for the ARM925T processor.
 169           Otherwise, say N.
 170
 171 # ARM926T
 172 config CPU_ARM926T
 173         bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
 174         select CPU_32v5
 175         select CPU_ABRT_EV5TJ
 176         select CPU_PABRT_LEGACY
 177         select CPU_CACHE_VIVT
 178         select CPU_CP15_MMU
 179         select CPU_COPY_V4WB if MMU
 180         select CPU_TLB_V4WBI if MMU
 181         help
 182           This is a variant of the ARM920.  It has slightly different
 183           instruction sequences for cache and TLB operations.  Curiously,
 184           there is no documentation on it at the ARM corporate website.
 185
 186           Say Y if you want support for the ARM926T processor.
 187           Otherwise, say N.
 188
 189 # FA526
 190 config CPU_FA526
 191         bool
 192         select CPU_32v4
 193         select CPU_ABRT_EV4
 194         select CPU_PABRT_LEGACY
 195         select CPU_CACHE_VIVT
 196         select CPU_CP15_MMU
 197         select CPU_CACHE_FA
 198         select CPU_COPY_FA if MMU
 199         select CPU_TLB_FA if MMU
 200         help
 201           The FA526 is a version of the ARMv4 compatible processor with
 202           Branch Target Buffer, Unified TLB and cache line size 16.
 203
 204           Say Y if you want support for the FA526 processor.
 205           Otherwise, say N.
 206
 207 # ARM940T
 208 config CPU_ARM940T
 209         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 210         depends on !MMU
 211         select CPU_32v4T
 212         select CPU_ABRT_NOMMU
 213         select CPU_PABRT_LEGACY
 214         select CPU_CACHE_VIVT
 215         select CPU_CP15_MPU
 216         help
 217           ARM940T is a member of the ARM9TDMI family of general-
 218           purpose microprocessors with MPU and separate 4KB
 219           instruction and 4KB data cases, each with a 4-word line
 220           length.
 221
 222           Say Y if you want support for the ARM940T processor.
 223           Otherwise, say N.
 224
 225 # ARM946E-S
 226 config CPU_ARM946E
 227         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 228         depends on !MMU
 229         select CPU_32v5
 230         select CPU_ABRT_NOMMU
 231         select CPU_PABRT_LEGACY
 232         select CPU_CACHE_VIVT
 233         select CPU_CP15_MPU
 234         help
 235           ARM946E-S is a member of the ARM9E-S family of high-
 236           performance, 32-bit system-on-chip processor solutions.
 237           The TCM and ARMv5TE 32-bit instruction set is supported.
 238
 239           Say Y if you want support for the ARM946E-S processor.
 240           Otherwise, say N.
 241
 242 # ARM1020 - needs validating
 243 config CPU_ARM1020
 244         bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
 245         select CPU_32v5
 246         select CPU_ABRT_EV4T
 247         select CPU_PABRT_LEGACY
 248         select CPU_CACHE_V4WT
 249         select CPU_CACHE_VIVT
 250         select CPU_CP15_MMU
 251         select CPU_COPY_V4WB if MMU
 252         select CPU_TLB_V4WBI if MMU
 253         help
 254           The ARM1020 is the 32K cached version of the ARM10 processor,
 255           with an addition of a floating-point unit.
 256
 257           Say Y if you want support for the ARM1020 processor.
 258           Otherwise, say N.
 259
 260 # ARM1020E - needs validating
 261 config CPU_ARM1020E
 262         bool "Support ARM1020E processor" if ARCH_INTEGRATOR
 263         select CPU_32v5
 264         select CPU_ABRT_EV4T
 265         select CPU_PABRT_LEGACY
 266         select CPU_CACHE_V4WT
 267         select CPU_CACHE_VIVT
 268         select CPU_CP15_MMU
 269         select CPU_COPY_V4WB if MMU
 270         select CPU_TLB_V4WBI if MMU
 271         depends on n
 272
 273 # ARM1022E
 274 config CPU_ARM1022
 275         bool "Support ARM1022E processor" if ARCH_INTEGRATOR
 276         select CPU_32v5
 277         select CPU_ABRT_EV4T
 278         select CPU_PABRT_LEGACY
 279         select CPU_CACHE_VIVT
 280         select CPU_CP15_MMU
 281         select CPU_COPY_V4WB if MMU # can probably do better
 282         select CPU_TLB_V4WBI if MMU
 283         help
 284           The ARM1022E is an implementation of the ARMv5TE architecture
 285           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 286           embedded trace macrocell, and a floating-point unit.
 287
 288           Say Y if you want support for the ARM1022E processor.
 289           Otherwise, say N.
 290
 291 # ARM1026EJ-S
 292 config CPU_ARM1026
 293         bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
 294         select CPU_32v5
 295         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 296         select CPU_PABRT_LEGACY
 297         select CPU_CACHE_VIVT
 298         select CPU_CP15_MMU
 299         select CPU_COPY_V4WB if MMU # can probably do better
 300         select CPU_TLB_V4WBI if MMU
 301         help
 302           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 303           based upon the ARM10 integer core.
 304
 305           Say Y if you want support for the ARM1026EJ-S processor.
 306           Otherwise, say N.
 307
 308 # SA110
 309 config CPU_SA110
 310         bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
 311         select CPU_32v3 if ARCH_RPC
 312         select CPU_32v4 if !ARCH_RPC
 313         select CPU_ABRT_EV4
 314         select CPU_PABRT_LEGACY
 315         select CPU_CACHE_V4WB
 316         select CPU_CACHE_VIVT
 317         select CPU_CP15_MMU
 318         select CPU_COPY_V4WB if MMU
 319         select CPU_TLB_V4WB if MMU
 320         help
 321           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 322           is available at five speeds ranging from 100 MHz to 233 MHz.
 323           More information is available at
 324           <http://developer.intel.com/design/strong/sa110.htm>.
 325
 326           Say Y if you want support for the SA-110 processor.
 327           Otherwise, say N.
 328
 329 # SA1100
 330 config CPU_SA1100
 331         bool
 332         select CPU_32v4
 333         select CPU_ABRT_EV4
 334         select CPU_PABRT_LEGACY
 335         select CPU_CACHE_V4WB
 336         select CPU_CACHE_VIVT
 337         select CPU_CP15_MMU
 338         select CPU_TLB_V4WB if MMU
 339
 340 # XScale
 341 config CPU_XSCALE
 342         bool
 343         select CPU_32v5
 344         select CPU_ABRT_EV5T
 345         select CPU_PABRT_LEGACY
 346         select CPU_CACHE_VIVT
 347         select CPU_CP15_MMU
 348         select CPU_TLB_V4WBI if MMU
 349
 350 # XScale Core Version 3
 351 config CPU_XSC3
 352         bool
 353         select CPU_32v5
 354         select CPU_ABRT_EV5T
 355         select CPU_PABRT_LEGACY
 356         select CPU_CACHE_VIVT
 357         select CPU_CP15_MMU
 358         select CPU_TLB_V4WBI if MMU
 359         select IO_36
 360
 361 # Marvell PJ1 (Mohawk)
 362 config CPU_MOHAWK
 363         bool
 364         select CPU_32v5
 365         select CPU_ABRT_EV5T
 366         select CPU_PABRT_LEGACY
 367         select CPU_CACHE_VIVT
 368         select CPU_CP15_MMU
 369         select CPU_TLB_V4WBI if MMU
 370         select CPU_COPY_V4WB if MMU
 371
 372 # Feroceon
 373 config CPU_FEROCEON
 374         bool
 375         select CPU_32v5
 376         select CPU_ABRT_EV5T
 377         select CPU_PABRT_LEGACY
 378         select CPU_CACHE_VIVT
 379         select CPU_CP15_MMU
 380         select CPU_COPY_FEROCEON if MMU
 381         select CPU_TLB_FEROCEON if MMU
 382
 383 config CPU_FEROCEON_OLD_ID
 384         bool "Accept early Feroceon cores with an ARM926 ID"
 385         depends on CPU_FEROCEON && !CPU_ARM926T
 386         default y
 387         help
 388           This enables the usage of some old Feroceon cores
 389           for which the CPU ID is equal to the ARM926 ID.
 390           Relevant for Feroceon-1850 and early Feroceon-2850.
 391
 392 # ARMv6
 393 config CPU_V6
 394         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 395         select CPU_32v6
 396         select CPU_ABRT_EV6
 397         select CPU_PABRT_V6
 398         select CPU_CACHE_V6
 399         select CPU_CACHE_VIPT
 400         select CPU_CP15_MMU
 401         select CPU_HAS_ASID if MMU
 402         select CPU_COPY_V6 if MMU
 403         select CPU_TLB_V6 if MMU
 404
 405 # ARMv6k
 406 config CPU_32v6K
 407         bool "Support ARM V6K processor extensions" if !SMP
 408         depends on CPU_V6
 409         default y if SMP && !ARCH_MX3
 410         help
 411           Say Y here if your ARMv6 processor supports the 'K' extension.
 412           This enables the kernel to use some instructions not present
 413           on previous processors, and as such a kernel build with this
 414           enabled will not boot on processors with do not support these
 415           instructions.
 416
 417 # ARMv7
 418 config CPU_V7
 419         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 420         select CPU_32v6K
 421         select CPU_32v7
 422         select CPU_ABRT_EV7
 423         select CPU_PABRT_V7
 424         select CPU_CACHE_V7
 425         select CPU_CACHE_VIPT
 426         select CPU_CP15_MMU
 427         select CPU_HAS_ASID if MMU
 428         select CPU_COPY_V6 if MMU
 429         select CPU_TLB_V7 if MMU
 430
 431 # Figure out what processor architecture version we should be using.
 432 # This defines the compiler instruction set which depends on the machine type.
 433 config CPU_32v3
 434         bool
 435         select TLS_REG_EMUL if SMP || !MMU
 436         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 437
 438 config CPU_32v4
 439         bool
 440         select TLS_REG_EMUL if SMP || !MMU
 441         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 442
 443 config CPU_32v4T
 444         bool
 445         select TLS_REG_EMUL if SMP || !MMU
 446         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 447
 448 config CPU_32v5
 449         bool
 450         select TLS_REG_EMUL if SMP || !MMU
 451         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 452
 453 config CPU_32v6
 454         bool
 455         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 456
 457 config CPU_32v7
 458         bool
 459
 460 # The abort model
 461 config CPU_ABRT_NOMMU
 462         bool
 463
 464 config CPU_ABRT_EV4
 465         bool
 466
 467 config CPU_ABRT_EV4T
 468         bool
 469
 470 config CPU_ABRT_LV4T
 471         bool
 472
 473 config CPU_ABRT_EV5T
 474         bool
 475
 476 config CPU_ABRT_EV5TJ
 477         bool
 478
 479 config CPU_ABRT_EV6
 480         bool
 481
 482 config CPU_ABRT_EV7
 483         bool
 484
 485 config CPU_PABRT_LEGACY
 486         bool
 487
 488 config CPU_PABRT_V6
 489         bool
 490
 491 config CPU_PABRT_V7
 492         bool
 493
 494 # The cache model
 495 config CPU_CACHE_V3
 496         bool
 497
 498 config CPU_CACHE_V4
 499         bool
 500
 501 config CPU_CACHE_V4WT
 502         bool
 503
 504 config CPU_CACHE_V4WB
 505         bool
 506
 507 config CPU_CACHE_V6
 508         bool
 509
 510 config CPU_CACHE_V7
 511         bool
 512
 513 config CPU_CACHE_VIVT
 514         bool
 515
 516 config CPU_CACHE_VIPT
 517         bool
 518
 519 config CPU_CACHE_FA
 520         bool
 521
 522 if MMU
 523 # The copy-page model
 524 config CPU_COPY_V3
 525         bool
 526
 527 config CPU_COPY_V4WT
 528         bool
 529
 530 config CPU_COPY_V4WB
 531         bool
 532
 533 config CPU_COPY_FEROCEON
 534         bool
 535
 536 config CPU_COPY_FA
 537         bool
 538
 539 config CPU_COPY_V6
 540         bool
 541
 542 # This selects the TLB model
 543 config CPU_TLB_V3
 544         bool
 545         help
 546           ARM Architecture Version 3 TLB.
 547
 548 config CPU_TLB_V4WT
 549         bool
 550         help
 551           ARM Architecture Version 4 TLB with writethrough cache.
 552
 553 config CPU_TLB_V4WB
 554         bool
 555         help
 556           ARM Architecture Version 4 TLB with writeback cache.
 557
 558 config CPU_TLB_V4WBI
 559         bool
 560         help
 561           ARM Architecture Version 4 TLB with writeback cache and invalidate
 562           instruction cache entry.
 563
 564 config CPU_TLB_FEROCEON
 565         bool
 566         help
 567           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 568
 569 config CPU_TLB_FA
 570         bool
 571         help
 572           Faraday ARM FA526 architecture, unified TLB with writeback cache
 573           and invalidate instruction cache entry. Branch target buffer is
 574           also supported.
 575
 576 config CPU_TLB_V6
 577         bool
 578
 579 config CPU_TLB_V7
 580         bool
 581
 582 endif
 583
 584 config CPU_HAS_ASID
 585         bool
 586         help
 587           This indicates whether the CPU has the ASID register; used to
 588           tag TLB and possibly cache entries.
 589
 590 config CPU_CP15
 591         bool
 592         help
 593           Processor has the CP15 register.
 594
 595 config CPU_CP15_MMU
 596         bool
 597         select CPU_CP15
 598         help
 599           Processor has the CP15 register, which has MMU related registers.
 600
 601 config CPU_CP15_MPU
 602         bool
 603         select CPU_CP15
 604         help
 605           Processor has the CP15 register, which has MPU related registers.
 606
 607 #
 608 # CPU supports 36-bit I/O
 609 #
 610 config IO_36
 611         bool
 612
 613 comment "Processor Features"
 614
 615 config ARM_THUMB
 616         bool "Support Thumb user binaries"
 617         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
 618         default y
 619         help
 620           Say Y if you want to include kernel support for running user space
 621           Thumb binaries.
 622
 623           The Thumb instruction set is a compressed form of the standard ARM
 624           instruction set resulting in smaller binaries at the expense of
 625           slightly less efficient code.
 626
 627           If you don't know what this all is, saying Y is a safe choice.
 628
 629 config ARM_THUMBEE
 630         bool "Enable ThumbEE CPU extension"
 631         depends on CPU_V7
 632         help
 633           Say Y here if you have a CPU with the ThumbEE extension and code to
 634           make use of it. Say N for code that can run on CPUs without ThumbEE.
 635
 636 config CPU_BIG_ENDIAN
 637         bool "Build big-endian kernel"
 638         depends on ARCH_SUPPORTS_BIG_ENDIAN
 639         help
 640           Say Y if you plan on running a kernel in big-endian mode.
 641           Note that your board must be properly built and your board
 642           port must properly enable any big-endian related features
 643           of your chipset/board/processor.
 644
 645 config CPU_ENDIAN_BE8
 646         bool
 647         depends on CPU_BIG_ENDIAN
 648         default CPU_V6 || CPU_V7
 649         help
 650           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 651
 652 config CPU_ENDIAN_BE32
 653         bool
 654         depends on CPU_BIG_ENDIAN
 655         default !CPU_ENDIAN_BE8
 656         help
 657           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 658
 659 config CPU_HIGH_VECTOR
 660         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 661         bool "Select the High exception vector"
 662         help
 663           Say Y here to select high exception vector(0xFFFF0000~).
 664           The exception vector can be vary depending on the platform
 665           design in nommu mode. If your platform needs to select
 666           high exception vector, say Y.
 667           Otherwise or if you are unsure, say N, and the low exception
 668           vector (0x00000000~) will be used.
 669
 670 config CPU_ICACHE_DISABLE
 671         bool "Disable I-Cache (I-bit)"
 672         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 673         help
 674           Say Y here to disable the processor instruction cache. Unless
 675           you have a reason not to or are unsure, say N.
 676
 677 config CPU_DCACHE_DISABLE
 678         bool "Disable D-Cache (C-bit)"
 679         depends on CPU_CP15
 680         help
 681           Say Y here to disable the processor data cache. Unless
 682           you have a reason not to or are unsure, say N.
 683
 684 config CPU_DCACHE_SIZE
 685         hex
 686         depends on CPU_ARM740T || CPU_ARM946E
 687         default 0x00001000 if CPU_ARM740T
 688         default 0x00002000 # default size for ARM946E-S
 689         help
 690           Some cores are synthesizable to have various sized cache. For
 691           ARM946E-S case, it can vary from 0KB to 1MB.
 692           To support such cache operations, it is efficient to know the size
 693           before compile time.
 694           If your SoC is configured to have a different size, define the value
 695           here with proper conditions.
 696
 697 config CPU_DCACHE_WRITETHROUGH
 698         bool "Force write through D-cache"
 699         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
 700         default y if CPU_ARM925T
 701         help
 702           Say Y here to use the data cache in writethrough mode. Unless you
 703           specifically require this or are unsure, say N.
 704
 705 config CPU_CACHE_ROUND_ROBIN
 706         bool "Round robin I and D cache replacement algorithm"
 707         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 708         help
 709           Say Y here to use the predictable round-robin cache replacement
 710           policy.  Unless you specifically require this or are unsure, say N.
 711
 712 config CPU_BPREDICT_DISABLE
 713         bool "Disable branch prediction"
 714         depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
 715         help
 716           Say Y here to disable branch prediction.  If unsure, say N.
 717
 718 config TLS_REG_EMUL
 719         bool
 720         help
 721           An SMP system using a pre-ARMv6 processor (there are apparently
 722           a few prototypes like that in existence) and therefore access to
 723           that required register must be emulated.
 724
 725 config HAS_TLS_REG
 726         bool
 727         depends on !TLS_REG_EMUL
 728         default y if SMP || CPU_32v7
 729         help
 730           This selects support for the CP15 thread register.
 731           It is defined to be available on some ARMv6 processors (including
 732           all SMP capable ARMv6's) or later processors.  User space may
 733           assume directly accessing that register and always obtain the
 734           expected value only on ARMv7 and above.
 735
 736 config NEEDS_SYSCALL_FOR_CMPXCHG
 737         bool
 738         help
 739           SMP on a pre-ARMv6 processor?  Well OK then.
 740           Forget about fast user space cmpxchg support.
 741           It is just not possible.
 742
 743 config OUTER_CACHE
 744         bool
 745
 746 config CACHE_FEROCEON_L2
 747         bool "Enable the Feroceon L2 cache controller"
 748         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
 749         default y
 750         select OUTER_CACHE
 751         help
 752           This option enables the Feroceon L2 cache controller.
 753
 754 config CACHE_FEROCEON_L2_WRITETHROUGH
 755         bool "Force Feroceon L2 cache write through"
 756         depends on CACHE_FEROCEON_L2
 757         help
 758           Say Y here to use the Feroceon L2 cache in writethrough mode.
 759           Unless you specifically require this, say N for writeback mode.
 760
 761 config CACHE_L2X0
 762         bool "Enable the L2x0 outer cache controller"
 763         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 764                    REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
 765         default y
 766         select OUTER_CACHE
 767         help
 768           This option enables the L2x0 PrimeCell.
 769
 770 config CACHE_XSC3L2
 771         bool "Enable the L2 cache on XScale3"
 772         depends on CPU_XSC3
 773         default y
 774         select OUTER_CACHE
 775         help
 776           This option enables the L2 cache on XScale3.
 777
 778 config ARM_L1_CACHE_SHIFT
 779         int
 780         default 6 if ARCH_OMAP3
 781         default 5