arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor"
  14         depends on ARCH_RPC
  15         select CPU_32v3
  16         select CPU_CACHE_V3
  17         select CPU_CACHE_VIVT
  18         select CPU_CP15_MMU
  19         select CPU_COPY_V3 if MMU
  20         select CPU_TLB_V3 if MMU
  21         help
  22           The ARM610 is the successor to the ARM3 processor
  23           and was produced by VLSI Technology Inc.
  24
  25           Say Y if you want support for the ARM610 processor.
  26           Otherwise, say N.
  27
  28 # ARM7TDMI
  29 config CPU_ARM7TDMI
  30         bool "Support ARM7TDMI processor"
  31         select CPU_32v4T
  32         select CPU_ABRT_LV4T
  33         select CPU_CACHE_V4
  34         help
  35           A 32-bit RISC microprocessor based on the ARM7 processor core
  36           which has no memory control unit and cache.
  37
  38           Say Y if you want support for the ARM7TDMI processor.
  39           Otherwise, say N.
  40
  41 # ARM710
  42 config CPU_ARM710
  43         bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  44         default y if ARCH_CLPS7500
  45         select CPU_32v3
  46         select CPU_CACHE_V3
  47         select CPU_CACHE_VIVT
  48         select CPU_CP15_MMU
  49         select CPU_COPY_V3 if MMU
  50         select CPU_TLB_V3 if MMU
  51         help
  52           A 32-bit RISC microprocessor based on the ARM7 processor core
  53           designed by Advanced RISC Machines Ltd. The ARM710 is the
  54           successor to the ARM610 processor. It was released in
  55           July 1994 by VLSI Technology Inc.
  56
  57           Say Y if you want support for the ARM710 processor.
  58           Otherwise, say N.
  59
  60 # ARM720T
  61 config CPU_ARM720T
  62         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  63         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  64         select CPU_32v4T
  65         select CPU_ABRT_LV4T
  66         select CPU_CACHE_V4
  67         select CPU_CACHE_VIVT
  68         select CPU_CP15_MMU
  69         select CPU_COPY_V4WT if MMU
  70         select CPU_TLB_V4WT if MMU
  71         help
  72           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  73           MMU built around an ARM7TDMI core.
  74
  75           Say Y if you want support for the ARM720T processor.
  76           Otherwise, say N.
  77
  78 # ARM740T
  79 config CPU_ARM740T
  80         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  81         select CPU_32v4T
  82         select CPU_ABRT_LV4T
  83         select CPU_CACHE_V3     # although the core is v4t
  84         select CPU_CP15_MPU
  85         help
  86           A 32-bit RISC processor with 8KB cache or 4KB variants,
  87           write buffer and MPU(Protection Unit) built around
  88           an ARM7TDMI core.
  89
  90           Say Y if you want support for the ARM740T processor.
  91           Otherwise, say N.
  92
  93 # ARM9TDMI
  94 config CPU_ARM9TDMI
  95         bool "Support ARM9TDMI processor"
  96         select CPU_32v4T
  97         select CPU_ABRT_EV4T
  98         select CPU_CACHE_V4
  99         help
 100           A 32-bit RISC microprocessor based on the ARM9 processor core
 101           which has no memory control unit and cache.
 102
 103           Say Y if you want support for the ARM9TDMI processor.
 104           Otherwise, say N.
 105
 106 # ARM920T
 107 config CPU_ARM920T
 108         bool "Support ARM920T processor"
 109         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
 110         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
 111         select CPU_32v4T
 112         select CPU_ABRT_EV4T
 113         select CPU_CACHE_V4WT
 114         select CPU_CACHE_VIVT
 115         select CPU_CP15_MMU
 116         select CPU_COPY_V4WB if MMU
 117         select CPU_TLB_V4WBI if MMU
 118         help
 119           The ARM920T is licensed to be produced by numerous vendors,
 120           and is used in the Maverick EP9312 and the Samsung S3C2410.
 121
 122           More information on the Maverick EP9312 at
 123           <http://linuxdevices.com/products/PD2382866068.html>.
 124
 125           Say Y if you want support for the ARM920T processor.
 126           Otherwise, say N.
 127
 128 # ARM922T
 129 config CPU_ARM922T
 130         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 131         depends on ARCH_LH7A40X || ARCH_INTEGRATOR
 132         default y if ARCH_LH7A40X
 133         select CPU_32v4T
 134         select CPU_ABRT_EV4T
 135         select CPU_CACHE_V4WT
 136         select CPU_CACHE_VIVT
 137         select CPU_CP15_MMU
 138         select CPU_COPY_V4WB if MMU
 139         select CPU_TLB_V4WBI if MMU
 140         help
 141           The ARM922T is a version of the ARM920T, but with smaller
 142           instruction and data caches. It is used in Altera's
 143           Excalibur XA device family.
 144
 145           Say Y if you want support for the ARM922T processor.
 146           Otherwise, say N.
 147
 148 # ARM925T
 149 config CPU_ARM925T
 150         bool "Support ARM925T processor" if ARCH_OMAP1
 151         depends on ARCH_OMAP15XX
 152         default y if ARCH_OMAP15XX
 153         select CPU_32v4T
 154         select CPU_ABRT_EV4T
 155         select CPU_CACHE_V4WT
 156         select CPU_CACHE_VIVT
 157         select CPU_CP15_MMU
 158         select CPU_COPY_V4WB if MMU
 159         select CPU_TLB_V4WBI if MMU
 160         help
 161           The ARM925T is a mix between the ARM920T and ARM926T, but with
 162           different instruction and data caches. It is used in TI's OMAP
 163           device family.
 164
 165           Say Y if you want support for the ARM925T processor.
 166           Otherwise, say N.
 167
 168 # ARM926T
 169 config CPU_ARM926T
 170         bool "Support ARM926T processor"
 171         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
 172         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
 173         select CPU_32v5
 174         select CPU_ABRT_EV5TJ
 175         select CPU_CACHE_VIVT
 176         select CPU_CP15_MMU
 177         select CPU_COPY_V4WB if MMU
 178         select CPU_TLB_V4WBI if MMU
 179         help
 180           This is a variant of the ARM920.  It has slightly different
 181           instruction sequences for cache and TLB operations.  Curiously,
 182           there is no documentation on it at the ARM corporate website.
 183
 184           Say Y if you want support for the ARM926T processor.
 185           Otherwise, say N.
 186
 187 # ARM1020 - needs validating
 188 config CPU_ARM1020
 189         bool "Support ARM1020T (rev 0) processor"
 190         depends on ARCH_INTEGRATOR
 191         select CPU_32v5
 192         select CPU_ABRT_EV4T
 193         select CPU_CACHE_V4WT
 194         select CPU_CACHE_VIVT
 195         select CPU_CP15_MMU
 196         select CPU_COPY_V4WB if MMU
 197         select CPU_TLB_V4WBI if MMU
 198         help
 199           The ARM1020 is the 32K cached version of the ARM10 processor,
 200           with an addition of a floating-point unit.
 201
 202           Say Y if you want support for the ARM1020 processor.
 203           Otherwise, say N.
 204
 205 # ARM1020E - needs validating
 206 config CPU_ARM1020E
 207         bool "Support ARM1020E processor"
 208         depends on ARCH_INTEGRATOR
 209         select CPU_32v5
 210         select CPU_ABRT_EV4T
 211         select CPU_CACHE_V4WT
 212         select CPU_CACHE_VIVT
 213         select CPU_CP15_MMU
 214         select CPU_COPY_V4WB if MMU
 215         select CPU_TLB_V4WBI if MMU
 216         depends on n
 217
 218 # ARM1022E
 219 config CPU_ARM1022
 220         bool "Support ARM1022E processor"
 221         depends on ARCH_INTEGRATOR
 222         select CPU_32v5
 223         select CPU_ABRT_EV4T
 224         select CPU_CACHE_VIVT
 225         select CPU_CP15_MMU
 226         select CPU_COPY_V4WB if MMU # can probably do better
 227         select CPU_TLB_V4WBI if MMU
 228         help
 229           The ARM1022E is an implementation of the ARMv5TE architecture
 230           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 231           embedded trace macrocell, and a floating-point unit.
 232
 233           Say Y if you want support for the ARM1022E processor.
 234           Otherwise, say N.
 235
 236 # ARM1026EJ-S
 237 config CPU_ARM1026
 238         bool "Support ARM1026EJ-S processor"
 239         depends on ARCH_INTEGRATOR
 240         select CPU_32v5
 241         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 242         select CPU_CACHE_VIVT
 243         select CPU_CP15_MMU
 244         select CPU_COPY_V4WB if MMU # can probably do better
 245         select CPU_TLB_V4WBI if MMU
 246         help
 247           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 248           based upon the ARM10 integer core.
 249
 250           Say Y if you want support for the ARM1026EJ-S processor.
 251           Otherwise, say N.
 252
 253 # SA110
 254 config CPU_SA110
 255         bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
 256         default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
 257         select CPU_32v3 if ARCH_RPC
 258         select CPU_32v4 if !ARCH_RPC
 259         select CPU_ABRT_EV4
 260         select CPU_CACHE_V4WB
 261         select CPU_CACHE_VIVT
 262         select CPU_CP15_MMU
 263         select CPU_COPY_V4WB if MMU
 264         select CPU_TLB_V4WB if MMU
 265         help
 266           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 267           is available at five speeds ranging from 100 MHz to 233 MHz.
 268           More information is available at
 269           <http://developer.intel.com/design/strong/sa110.htm>.
 270
 271           Say Y if you want support for the SA-110 processor.
 272           Otherwise, say N.
 273
 274 # SA1100
 275 config CPU_SA1100
 276         bool
 277         depends on ARCH_SA1100
 278         default y
 279         select CPU_32v4
 280         select CPU_ABRT_EV4
 281         select CPU_CACHE_V4WB
 282         select CPU_CACHE_VIVT
 283         select CPU_CP15_MMU
 284         select CPU_TLB_V4WB if MMU
 285
 286 # XScale
 287 config CPU_XSCALE
 288         bool
 289         depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
 290         default y
 291         select CPU_32v5
 292         select CPU_ABRT_EV5T
 293         select CPU_CACHE_VIVT
 294         select CPU_CP15_MMU
 295         select CPU_TLB_V4WBI if MMU
 296
 297 # XScale Core Version 3
 298 config CPU_XSC3
 299         bool
 300         depends on ARCH_IXP23XX
 301         default y
 302         select CPU_32v5
 303         select CPU_ABRT_EV5T
 304         select CPU_CACHE_VIVT
 305         select CPU_CP15_MMU
 306         select CPU_TLB_V4WBI if MMU
 307         select IO_36
 308
 309 # ARMv6
 310 config CPU_V6
 311         bool "Support ARM V6 processor"
 312         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
 313         select CPU_32v6
 314         select CPU_ABRT_EV6
 315         select CPU_CACHE_V6
 316         select CPU_CACHE_VIPT
 317         select CPU_CP15_MMU
 318         select CPU_COPY_V6 if MMU
 319         select CPU_TLB_V6 if MMU
 320
 321 # ARMv6k
 322 config CPU_32v6K
 323         bool "Support ARM V6K processor extensions" if !SMP
 324         depends on CPU_V6
 325         default y if SMP
 326         help
 327           Say Y here if your ARMv6 processor supports the 'K' extension.
 328           This enables the kernel to use some instructions not present
 329           on previous processors, and as such a kernel build with this
 330           enabled will not boot on processors with do not support these
 331           instructions.
 332
 333 # Figure out what processor architecture version we should be using.
 334 # This defines the compiler instruction set which depends on the machine type.
 335 config CPU_32v3
 336         bool
 337         select TLS_REG_EMUL if SMP || !MMU
 338         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 339
 340 config CPU_32v4
 341         bool
 342         select TLS_REG_EMUL if SMP || !MMU
 343         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 344
 345 config CPU_32v4T
 346         bool
 347         select TLS_REG_EMUL if SMP || !MMU
 348         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 349
 350 config CPU_32v5
 351         bool
 352         select TLS_REG_EMUL if SMP || !MMU
 353         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 354
 355 config CPU_32v6
 356         bool
 357
 358 # The abort model
 359 config CPU_ABRT_EV4
 360         bool
 361
 362 config CPU_ABRT_EV4T
 363         bool
 364
 365 config CPU_ABRT_LV4T
 366         bool
 367
 368 config CPU_ABRT_EV5T
 369         bool
 370
 371 config CPU_ABRT_EV5TJ
 372         bool
 373
 374 config CPU_ABRT_EV6
 375         bool
 376
 377 # The cache model
 378 config CPU_CACHE_V3
 379         bool
 380
 381 config CPU_CACHE_V4
 382         bool
 383
 384 config CPU_CACHE_V4WT
 385         bool
 386
 387 config CPU_CACHE_V4WB
 388         bool
 389
 390 config CPU_CACHE_V6
 391         bool
 392
 393 config CPU_CACHE_VIVT
 394         bool
 395
 396 config CPU_CACHE_VIPT
 397         bool
 398
 399 if MMU
 400 # The copy-page model
 401 config CPU_COPY_V3
 402         bool
 403
 404 config CPU_COPY_V4WT
 405         bool
 406
 407 config CPU_COPY_V4WB
 408         bool
 409
 410 config CPU_COPY_V6
 411         bool
 412
 413 # This selects the TLB model
 414 config CPU_TLB_V3
 415         bool
 416         help
 417           ARM Architecture Version 3 TLB.
 418
 419 config CPU_TLB_V4WT
 420         bool
 421         help
 422           ARM Architecture Version 4 TLB with writethrough cache.
 423
 424 config CPU_TLB_V4WB
 425         bool
 426         help
 427           ARM Architecture Version 4 TLB with writeback cache.
 428
 429 config CPU_TLB_V4WBI
 430         bool
 431         help
 432           ARM Architecture Version 4 TLB with writeback cache and invalidate
 433           instruction cache entry.
 434
 435 config CPU_TLB_V6
 436         bool
 437
 438 endif
 439
 440 config CPU_CP15
 441         bool
 442         help
 443           Processor has the CP15 register.
 444
 445 config CPU_CP15_MMU
 446         bool
 447         select CPU_CP15
 448         help
 449           Processor has the CP15 register, which has MMU related registers.
 450
 451 config CPU_CP15_MPU
 452         bool
 453         select CPU_CP15
 454         help
 455           Processor has the CP15 register, which has MPU related registers.
 456
 457 #
 458 # CPU supports 36-bit I/O
 459 #
 460 config IO_36
 461         bool
 462
 463 comment "Processor Features"
 464
 465 config ARM_THUMB
 466         bool "Support Thumb user binaries"
 467         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
 468         default y
 469         help
 470           Say Y if you want to include kernel support for running user space
 471           Thumb binaries.
 472
 473           The Thumb instruction set is a compressed form of the standard ARM
 474           instruction set resulting in smaller binaries at the expense of
 475           slightly less efficient code.
 476
 477           If you don't know what this all is, saying Y is a safe choice.
 478
 479 config CPU_BIG_ENDIAN
 480         bool "Build big-endian kernel"
 481         depends on ARCH_SUPPORTS_BIG_ENDIAN
 482         help
 483           Say Y if you plan on running a kernel in big-endian mode.
 484           Note that your board must be properly built and your board
 485           port must properly enable any big-endian related features
 486           of your chipset/board/processor.
 487
 488 config CPU_ICACHE_DISABLE
 489         bool "Disable I-Cache (I-bit)"
 490         depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 491         help
 492           Say Y here to disable the processor instruction cache. Unless
 493           you have a reason not to or are unsure, say N.
 494
 495 config CPU_DCACHE_DISABLE
 496         bool "Disable D-Cache (C-bit)"
 497         depends on CPU_CP15
 498         help
 499           Say Y here to disable the processor data cache. Unless
 500           you have a reason not to or are unsure, say N.
 501
 502 config CPU_DCACHE_WRITETHROUGH
 503         bool "Force write through D-cache"
 504         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
 505         default y if CPU_ARM925T
 506         help
 507           Say Y here to use the data cache in writethrough mode. Unless you
 508           specifically require this or are unsure, say N.
 509
 510 config CPU_CACHE_ROUND_ROBIN
 511         bool "Round robin I and D cache replacement algorithm"
 512         depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 513         help
 514           Say Y here to use the predictable round-robin cache replacement
 515           policy.  Unless you specifically require this or are unsure, say N.
 516
 517 config CPU_BPREDICT_DISABLE
 518         bool "Disable branch prediction"
 519         depends on CPU_ARM1020 || CPU_V6
 520         help
 521           Say Y here to disable branch prediction.  If unsure, say N.
 522
 523 config TLS_REG_EMUL
 524         bool
 525         help
 526           An SMP system using a pre-ARMv6 processor (there are apparently
 527           a few prototypes like that in existence) and therefore access to
 528           that required register must be emulated.
 529
 530 config HAS_TLS_REG
 531         bool
 532         depends on !TLS_REG_EMUL
 533         default y if SMP || CPU_32v7
 534         help
 535           This selects support for the CP15 thread register.
 536           It is defined to be available on some ARMv6 processors (including
 537           all SMP capable ARMv6's) or later processors.  User space may
 538           assume directly accessing that register and always obtain the
 539           expected value only on ARMv7 and above.
 540
 541 config NEEDS_SYSCALL_FOR_CMPXCHG
 542         bool
 543         help
 544           SMP on a pre-ARMv6 processor?  Well OK then.
 545           Forget about fast user space cmpxchg support.
 546           It is just not possible.
 547