arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 # Select CPU types depending on the architecture selected.  This selects
   4 # which CPUs we support in the kernel image, and the compiler instruction
   5 # optimiser behaviour.
   6
   7 # ARM7TDMI
   8 config CPU_ARM7TDMI
   9         bool "Support ARM7TDMI processor"
  10         depends on !MMU
  11         select CPU_32v4T
  12         select CPU_ABRT_LV4T
  13         select CPU_CACHE_V4
  14         select CPU_PABRT_LEGACY
  15         help
  16           A 32-bit RISC microprocessor based on the ARM7 processor core
  17           which has no memory control unit and cache.
  18
  19           Say Y if you want support for the ARM7TDMI processor.
  20           Otherwise, say N.
  21
  22 # ARM720T
  23 config CPU_ARM720T
  24         bool "Support ARM720T processor" if ARCH_INTEGRATOR
  25         select CPU_32v4T
  26         select CPU_ABRT_LV4T
  27         select CPU_CACHE_V4
  28         select CPU_CACHE_VIVT
  29         select CPU_COPY_V4WT if MMU
  30         select CPU_CP15_MMU
  31         select CPU_PABRT_LEGACY
  32         select CPU_TLB_V4WT if MMU
  33         help
  34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  35           MMU built around an ARM7TDMI core.
  36
  37           Say Y if you want support for the ARM720T processor.
  38           Otherwise, say N.
  39
  40 # ARM740T
  41 config CPU_ARM740T
  42         bool "Support ARM740T processor" if ARCH_INTEGRATOR
  43         depends on !MMU
  44         select CPU_32v4T
  45         select CPU_ABRT_LV4T
  46         select CPU_CACHE_V4
  47         select CPU_CP15_MPU
  48         select CPU_PABRT_LEGACY
  49         help
  50           A 32-bit RISC processor with 8KB cache or 4KB variants,
  51           write buffer and MPU(Protection Unit) built around
  52           an ARM7TDMI core.
  53
  54           Say Y if you want support for the ARM740T processor.
  55           Otherwise, say N.
  56
  57 # ARM9TDMI
  58 config CPU_ARM9TDMI
  59         bool "Support ARM9TDMI processor"
  60         depends on !MMU
  61         select CPU_32v4T
  62         select CPU_ABRT_NOMMU
  63         select CPU_CACHE_V4
  64         select CPU_PABRT_LEGACY
  65         help
  66           A 32-bit RISC microprocessor based on the ARM9 processor core
  67           which has no memory control unit and cache.
  68
  69           Say Y if you want support for the ARM9TDMI processor.
  70           Otherwise, say N.
  71
  72 # ARM920T
  73 config CPU_ARM920T
  74         bool "Support ARM920T processor" if ARCH_INTEGRATOR
  75         select CPU_32v4T
  76         select CPU_ABRT_EV4T
  77         select CPU_CACHE_V4WT
  78         select CPU_CACHE_VIVT
  79         select CPU_COPY_V4WB if MMU
  80         select CPU_CP15_MMU
  81         select CPU_PABRT_LEGACY
  82         select CPU_TLB_V4WBI if MMU
  83         help
  84           The ARM920T is licensed to be produced by numerous vendors,
  85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
  86
  87           Say Y if you want support for the ARM920T processor.
  88           Otherwise, say N.
  89
  90 # ARM922T
  91 config CPU_ARM922T
  92         bool "Support ARM922T processor" if ARCH_INTEGRATOR
  93         select CPU_32v4T
  94         select CPU_ABRT_EV4T
  95         select CPU_CACHE_V4WT
  96         select CPU_CACHE_VIVT
  97         select CPU_COPY_V4WB if MMU
  98         select CPU_CP15_MMU
  99         select CPU_PABRT_LEGACY
 100         select CPU_TLB_V4WBI if MMU
 101         help
 102           The ARM922T is a version of the ARM920T, but with smaller
 103           instruction and data caches. It is used in Altera's
 104           Excalibur XA device family and Micrel's KS8695 Centaur.
 105
 106           Say Y if you want support for the ARM922T processor.
 107           Otherwise, say N.
 108
 109 # ARM925T
 110 config CPU_ARM925T
 111         bool "Support ARM925T processor" if ARCH_OMAP1
 112         select CPU_32v4T
 113         select CPU_ABRT_EV4T
 114         select CPU_CACHE_V4WT
 115         select CPU_CACHE_VIVT
 116         select CPU_COPY_V4WB if MMU
 117         select CPU_CP15_MMU
 118         select CPU_PABRT_LEGACY
 119         select CPU_TLB_V4WBI if MMU
 120         help
 121           The ARM925T is a mix between the ARM920T and ARM926T, but with
 122           different instruction and data caches. It is used in TI's OMAP
 123           device family.
 124
 125           Say Y if you want support for the ARM925T processor.
 126           Otherwise, say N.
 127
 128 # ARM926T
 129 config CPU_ARM926T
 130         bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
 131         select CPU_32v5
 132         select CPU_ABRT_EV5TJ
 133         select CPU_CACHE_VIVT
 134         select CPU_COPY_V4WB if MMU
 135         select CPU_CP15_MMU
 136         select CPU_PABRT_LEGACY
 137         select CPU_TLB_V4WBI if MMU
 138         help
 139           This is a variant of the ARM920.  It has slightly different
 140           instruction sequences for cache and TLB operations.  Curiously,
 141           there is no documentation on it at the ARM corporate website.
 142
 143           Say Y if you want support for the ARM926T processor.
 144           Otherwise, say N.
 145
 146 # FA526
 147 config CPU_FA526
 148         bool
 149         select CPU_32v4
 150         select CPU_ABRT_EV4
 151         select CPU_CACHE_FA
 152         select CPU_CACHE_VIVT
 153         select CPU_COPY_FA if MMU
 154         select CPU_CP15_MMU
 155         select CPU_PABRT_LEGACY
 156         select CPU_TLB_FA if MMU
 157         help
 158           The FA526 is a version of the ARMv4 compatible processor with
 159           Branch Target Buffer, Unified TLB and cache line size 16.
 160
 161           Say Y if you want support for the FA526 processor.
 162           Otherwise, say N.
 163
 164 # ARM940T
 165 config CPU_ARM940T
 166         bool "Support ARM940T processor" if ARCH_INTEGRATOR
 167         depends on !MMU
 168         select CPU_32v4T
 169         select CPU_ABRT_NOMMU
 170         select CPU_CACHE_VIVT
 171         select CPU_CP15_MPU
 172         select CPU_PABRT_LEGACY
 173         help
 174           ARM940T is a member of the ARM9TDMI family of general-
 175           purpose microprocessors with MPU and separate 4KB
 176           instruction and 4KB data cases, each with a 4-word line
 177           length.
 178
 179           Say Y if you want support for the ARM940T processor.
 180           Otherwise, say N.
 181
 182 # ARM946E-S
 183 config CPU_ARM946E
 184         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
 185         depends on !MMU
 186         select CPU_32v5
 187         select CPU_ABRT_NOMMU
 188         select CPU_CACHE_VIVT
 189         select CPU_CP15_MPU
 190         select CPU_PABRT_LEGACY
 191         help
 192           ARM946E-S is a member of the ARM9E-S family of high-
 193           performance, 32-bit system-on-chip processor solutions.
 194           The TCM and ARMv5TE 32-bit instruction set is supported.
 195
 196           Say Y if you want support for the ARM946E-S processor.
 197           Otherwise, say N.
 198
 199 # ARM1020 - needs validating
 200 config CPU_ARM1020
 201         bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
 202         select CPU_32v5
 203         select CPU_ABRT_EV4T
 204         select CPU_CACHE_V4WT
 205         select CPU_CACHE_VIVT
 206         select CPU_COPY_V4WB if MMU
 207         select CPU_CP15_MMU
 208         select CPU_PABRT_LEGACY
 209         select CPU_TLB_V4WBI if MMU
 210         help
 211           The ARM1020 is the 32K cached version of the ARM10 processor,
 212           with an addition of a floating-point unit.
 213
 214           Say Y if you want support for the ARM1020 processor.
 215           Otherwise, say N.
 216
 217 # ARM1020E - needs validating
 218 config CPU_ARM1020E
 219         bool "Support ARM1020E processor" if ARCH_INTEGRATOR
 220         depends on n
 221         select CPU_32v5
 222         select CPU_ABRT_EV4T
 223         select CPU_CACHE_V4WT
 224         select CPU_CACHE_VIVT
 225         select CPU_COPY_V4WB if MMU
 226         select CPU_CP15_MMU
 227         select CPU_PABRT_LEGACY
 228         select CPU_TLB_V4WBI if MMU
 229
 230 # ARM1022E
 231 config CPU_ARM1022
 232         bool "Support ARM1022E processor" if ARCH_INTEGRATOR
 233         select CPU_32v5
 234         select CPU_ABRT_EV4T
 235         select CPU_CACHE_VIVT
 236         select CPU_COPY_V4WB if MMU # can probably do better
 237         select CPU_CP15_MMU
 238         select CPU_PABRT_LEGACY
 239         select CPU_TLB_V4WBI if MMU
 240         help
 241           The ARM1022E is an implementation of the ARMv5TE architecture
 242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 243           embedded trace macrocell, and a floating-point unit.
 244
 245           Say Y if you want support for the ARM1022E processor.
 246           Otherwise, say N.
 247
 248 # ARM1026EJ-S
 249 config CPU_ARM1026
 250         bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
 251         select CPU_32v5
 252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 253         select CPU_CACHE_VIVT
 254         select CPU_COPY_V4WB if MMU # can probably do better
 255         select CPU_CP15_MMU
 256         select CPU_PABRT_LEGACY
 257         select CPU_TLB_V4WBI if MMU
 258         help
 259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 260           based upon the ARM10 integer core.
 261
 262           Say Y if you want support for the ARM1026EJ-S processor.
 263           Otherwise, say N.
 264
 265 # SA110
 266 config CPU_SA110
 267         bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
 268         select CPU_32v3 if ARCH_RPC
 269         select CPU_32v4 if !ARCH_RPC
 270         select CPU_ABRT_EV4
 271         select CPU_CACHE_V4WB
 272         select CPU_CACHE_VIVT
 273         select CPU_COPY_V4WB if MMU
 274         select CPU_CP15_MMU
 275         select CPU_PABRT_LEGACY
 276         select CPU_TLB_V4WB if MMU
 277         help
 278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 279           is available at five speeds ranging from 100 MHz to 233 MHz.
 280           More information is available at
 281           <http://developer.intel.com/design/strong/sa110.htm>.
 282
 283           Say Y if you want support for the SA-110 processor.
 284           Otherwise, say N.
 285
 286 # SA1100
 287 config CPU_SA1100
 288         bool
 289         select CPU_32v4
 290         select CPU_ABRT_EV4
 291         select CPU_CACHE_V4WB
 292         select CPU_CACHE_VIVT
 293         select CPU_CP15_MMU
 294         select CPU_PABRT_LEGACY
 295         select CPU_TLB_V4WB if MMU
 296
 297 # XScale
 298 config CPU_XSCALE
 299         bool
 300         select CPU_32v5
 301         select CPU_ABRT_EV5T
 302         select CPU_CACHE_VIVT
 303         select CPU_CP15_MMU
 304         select CPU_PABRT_LEGACY
 305         select CPU_TLB_V4WBI if MMU
 306
 307 # XScale Core Version 3
 308 config CPU_XSC3
 309         bool
 310         select CPU_32v5
 311         select CPU_ABRT_EV5T
 312         select CPU_CACHE_VIVT
 313         select CPU_CP15_MMU
 314         select CPU_PABRT_LEGACY
 315         select CPU_TLB_V4WBI if MMU
 316         select IO_36
 317
 318 # Marvell PJ1 (Mohawk)
 319 config CPU_MOHAWK
 320         bool
 321         select CPU_32v5
 322         select CPU_ABRT_EV5T
 323         select CPU_CACHE_VIVT
 324         select CPU_COPY_V4WB if MMU
 325         select CPU_CP15_MMU
 326         select CPU_PABRT_LEGACY
 327         select CPU_TLB_V4WBI if MMU
 328
 329 # Feroceon
 330 config CPU_FEROCEON
 331         bool
 332         select CPU_32v5
 333         select CPU_ABRT_EV5T
 334         select CPU_CACHE_VIVT
 335         select CPU_COPY_FEROCEON if MMU
 336         select CPU_CP15_MMU
 337         select CPU_PABRT_LEGACY
 338         select CPU_TLB_FEROCEON if MMU
 339
 340 config CPU_FEROCEON_OLD_ID
 341         bool "Accept early Feroceon cores with an ARM926 ID"
 342         depends on CPU_FEROCEON && !CPU_ARM926T
 343         default y
 344         help
 345           This enables the usage of some old Feroceon cores
 346           for which the CPU ID is equal to the ARM926 ID.
 347           Relevant for Feroceon-1850 and early Feroceon-2850.
 348
 349 # Marvell PJ4
 350 config CPU_PJ4
 351         bool
 352         select ARM_THUMBEE
 353         select CPU_V7
 354
 355 config CPU_PJ4B
 356         bool
 357         select CPU_V7
 358
 359 # ARMv6
 360 config CPU_V6
 361         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 362         select CPU_32v6
 363         select CPU_ABRT_EV6
 364         select CPU_CACHE_V6
 365         select CPU_CACHE_VIPT
 366         select CPU_COPY_V6 if MMU
 367         select CPU_CP15_MMU
 368         select CPU_HAS_ASID if MMU
 369         select CPU_PABRT_V6
 370         select CPU_TLB_V6 if MMU
 371
 372 # ARMv6k
 373 config CPU_V6K
 374         bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 375         select CPU_32v6
 376         select CPU_32v6K
 377         select CPU_ABRT_EV6
 378         select CPU_CACHE_V6
 379         select CPU_CACHE_VIPT
 380         select CPU_COPY_V6 if MMU
 381         select CPU_CP15_MMU
 382         select CPU_HAS_ASID if MMU
 383         select CPU_PABRT_V6
 384         select CPU_TLB_V6 if MMU
 385
 386 # ARMv7
 387 config CPU_V7
 388         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
 389         select CPU_32v6K
 390         select CPU_32v7
 391         select CPU_ABRT_EV7
 392         select CPU_CACHE_V7
 393         select CPU_CACHE_VIPT
 394         select CPU_COPY_V6 if MMU
 395         select CPU_CP15_MMU
 396         select CPU_HAS_ASID if MMU
 397         select CPU_PABRT_V7
 398         select CPU_TLB_V7 if MMU
 399
 400 config CPU_THUMBONLY
 401         bool
 402         # There are no CPUs available with MMU that don't implement an ARM ISA:
 403         depends on !MMU
 404         help
 405           Select this if your CPU doesn't support the 32 bit ARM instructions.
 406
 407 # Figure out what processor architecture version we should be using.
 408 # This defines the compiler instruction set which depends on the machine type.
 409 config CPU_32v3
 410         bool
 411         select CPU_USE_DOMAINS if MMU
 412         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 413         select TLS_REG_EMUL if SMP || !MMU
 414
 415 config CPU_32v4
 416         bool
 417         select CPU_USE_DOMAINS if MMU
 418         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 419         select TLS_REG_EMUL if SMP || !MMU
 420
 421 config CPU_32v4T
 422         bool
 423         select CPU_USE_DOMAINS if MMU
 424         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 425         select TLS_REG_EMUL if SMP || !MMU
 426
 427 config CPU_32v5
 428         bool
 429         select CPU_USE_DOMAINS if MMU
 430         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 431         select TLS_REG_EMUL if SMP || !MMU
 432
 433 config CPU_32v6
 434         bool
 435         select CPU_USE_DOMAINS if CPU_V6 && MMU
 436         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 437
 438 config CPU_32v6K
 439         bool
 440
 441 config CPU_32v7
 442         bool
 443
 444 # The abort model
 445 config CPU_ABRT_NOMMU
 446         bool
 447
 448 config CPU_ABRT_EV4
 449         bool
 450
 451 config CPU_ABRT_EV4T
 452         bool
 453
 454 config CPU_ABRT_LV4T
 455         bool
 456
 457 config CPU_ABRT_EV5T
 458         bool
 459
 460 config CPU_ABRT_EV5TJ
 461         bool
 462
 463 config CPU_ABRT_EV6
 464         bool
 465
 466 config CPU_ABRT_EV7
 467         bool
 468
 469 config CPU_PABRT_LEGACY
 470         bool
 471
 472 config CPU_PABRT_V6
 473         bool
 474
 475 config CPU_PABRT_V7
 476         bool
 477
 478 # The cache model
 479 config CPU_CACHE_V4
 480         bool
 481
 482 config CPU_CACHE_V4WT
 483         bool
 484
 485 config CPU_CACHE_V4WB
 486         bool
 487
 488 config CPU_CACHE_V6
 489         bool
 490
 491 config CPU_CACHE_V7
 492         bool
 493
 494 config CPU_CACHE_VIVT
 495         bool
 496
 497 config CPU_CACHE_VIPT
 498         bool
 499
 500 config CPU_CACHE_FA
 501         bool
 502
 503 if MMU
 504 # The copy-page model
 505 config CPU_COPY_V4WT
 506         bool
 507
 508 config CPU_COPY_V4WB
 509         bool
 510
 511 config CPU_COPY_FEROCEON
 512         bool
 513
 514 config CPU_COPY_FA
 515         bool
 516
 517 config CPU_COPY_V6
 518         bool
 519
 520 # This selects the TLB model
 521 config CPU_TLB_V4WT
 522         bool
 523         help
 524           ARM Architecture Version 4 TLB with writethrough cache.
 525
 526 config CPU_TLB_V4WB
 527         bool
 528         help
 529           ARM Architecture Version 4 TLB with writeback cache.
 530
 531 config CPU_TLB_V4WBI
 532         bool
 533         help
 534           ARM Architecture Version 4 TLB with writeback cache and invalidate
 535           instruction cache entry.
 536
 537 config CPU_TLB_FEROCEON
 538         bool
 539         help
 540           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 541
 542 config CPU_TLB_FA
 543         bool
 544         help
 545           Faraday ARM FA526 architecture, unified TLB with writeback cache
 546           and invalidate instruction cache entry. Branch target buffer is
 547           also supported.
 548
 549 config CPU_TLB_V6
 550         bool
 551
 552 config CPU_TLB_V7
 553         bool
 554
 555 config VERIFY_PERMISSION_FAULT
 556         bool
 557 endif
 558
 559 config CPU_HAS_ASID
 560         bool
 561         help
 562           This indicates whether the CPU has the ASID register; used to
 563           tag TLB and possibly cache entries.
 564
 565 config CPU_CP15
 566         bool
 567         help
 568           Processor has the CP15 register.
 569
 570 config CPU_CP15_MMU
 571         bool
 572         select CPU_CP15
 573         help
 574           Processor has the CP15 register, which has MMU related registers.
 575
 576 config CPU_CP15_MPU
 577         bool
 578         select CPU_CP15
 579         help
 580           Processor has the CP15 register, which has MPU related registers.
 581
 582 config CPU_USE_DOMAINS
 583         bool
 584         help
 585           This option enables or disables the use of domain switching
 586           via the set_fs() function.
 587
 588 #
 589 # CPU supports 36-bit I/O
 590 #
 591 config IO_36
 592         bool
 593
 594 comment "Processor Features"
 595
 596 config ARM_LPAE
 597         bool "Support for the Large Physical Address Extension"
 598         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
 599                 !CPU_32v4 && !CPU_32v3
 600         help
 601           Say Y if you have an ARMv7 processor supporting the LPAE page
 602           table format and you would like to access memory beyond the
 603           4GB limit. The resulting kernel image will not run on
 604           processors without the LPA extension.
 605
 606           If unsure, say N.
 607
 608 config ARCH_PHYS_ADDR_T_64BIT
 609         def_bool ARM_LPAE
 610
 611 config ARCH_DMA_ADDR_T_64BIT
 612         bool
 613
 614 config ARM_THUMB
 615         bool "Support Thumb user binaries" if !CPU_THUMBONLY
 616         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
 617         default y
 618         help
 619           Say Y if you want to include kernel support for running user space
 620           Thumb binaries.
 621
 622           The Thumb instruction set is a compressed form of the standard ARM
 623           instruction set resulting in smaller binaries at the expense of
 624           slightly less efficient code.
 625
 626           If you don't know what this all is, saying Y is a safe choice.
 627
 628 config ARM_THUMBEE
 629         bool "Enable ThumbEE CPU extension"
 630         depends on CPU_V7
 631         help
 632           Say Y here if you have a CPU with the ThumbEE extension and code to
 633           make use of it. Say N for code that can run on CPUs without ThumbEE.
 634
 635 config ARM_VIRT_EXT
 636         bool
 637         depends on MMU
 638         default y if CPU_V7
 639         help
 640           Enable the kernel to make use of the ARM Virtualization
 641           Extensions to install hypervisors without run-time firmware
 642           assistance.
 643
 644           A compliant bootloader is required in order to make maximum
 645           use of this feature.  Refer to Documentation/arm/Booting for
 646           details.
 647
 648 config SWP_EMULATE
 649         bool "Emulate SWP/SWPB instructions"
 650         depends on !CPU_USE_DOMAINS && CPU_V7
 651         default y if SMP
 652         select HAVE_PROC_CPU if PROC_FS
 653         help
 654           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
 655           ARMv7 multiprocessing extensions introduce the ability to disable
 656           these instructions, triggering an undefined instruction exception
 657           when executed. Say Y here to enable software emulation of these
 658           instructions for userspace (not kernel) using LDREX/STREX.
 659           Also creates /proc/cpu/swp_emulation for statistics.
 660
 661           In some older versions of glibc [<=2.8] SWP is used during futex
 662           trylock() operations with the assumption that the code will not
 663           be preempted. This invalid assumption may be more likely to fail
 664           with SWP emulation enabled, leading to deadlock of the user
 665           application.
 666
 667           NOTE: when accessing uncached shared regions, LDREX/STREX rely
 668           on an external transaction monitoring block called a global
 669           monitor to maintain update atomicity. If your system does not
 670           implement a global monitor, this option can cause programs that
 671           perform SWP operations to uncached memory to deadlock.
 672
 673           If unsure, say Y.
 674
 675 config CPU_BIG_ENDIAN
 676         bool "Build big-endian kernel"
 677         depends on ARCH_SUPPORTS_BIG_ENDIAN
 678         help
 679           Say Y if you plan on running a kernel in big-endian mode.
 680           Note that your board must be properly built and your board
 681           port must properly enable any big-endian related features
 682           of your chipset/board/processor.
 683
 684 config CPU_ENDIAN_BE8
 685         bool
 686         depends on CPU_BIG_ENDIAN
 687         default CPU_V6 || CPU_V6K || CPU_V7
 688         help
 689           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 690
 691 config CPU_ENDIAN_BE32
 692         bool
 693         depends on CPU_BIG_ENDIAN
 694         default !CPU_ENDIAN_BE8
 695         help
 696           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 697
 698 config CPU_HIGH_VECTOR
 699         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 700         bool "Select the High exception vector"
 701         help
 702           Say Y here to select high exception vector(0xFFFF0000~).
 703           The exception vector can vary depending on the platform
 704           design in nommu mode. If your platform needs to select
 705           high exception vector, say Y.
 706           Otherwise or if you are unsure, say N, and the low exception
 707           vector (0x00000000~) will be used.
 708
 709 config CPU_ICACHE_DISABLE
 710         bool "Disable I-Cache (I-bit)"
 711         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 712         help
 713           Say Y here to disable the processor instruction cache. Unless
 714           you have a reason not to or are unsure, say N.
 715
 716 config CPU_DCACHE_DISABLE
 717         bool "Disable D-Cache (C-bit)"
 718         depends on CPU_CP15
 719         help
 720           Say Y here to disable the processor data cache. Unless
 721           you have a reason not to or are unsure, say N.
 722
 723 config CPU_DCACHE_SIZE
 724         hex
 725         depends on CPU_ARM740T || CPU_ARM946E
 726         default 0x00001000 if CPU_ARM740T
 727         default 0x00002000 # default size for ARM946E-S
 728         help
 729           Some cores are synthesizable to have various sized cache. For
 730           ARM946E-S case, it can vary from 0KB to 1MB.
 731           To support such cache operations, it is efficient to know the size
 732           before compile time.
 733           If your SoC is configured to have a different size, define the value
 734           here with proper conditions.
 735
 736 config CPU_DCACHE_WRITETHROUGH
 737         bool "Force write through D-cache"
 738         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
 739         default y if CPU_ARM925T
 740         help
 741           Say Y here to use the data cache in writethrough mode. Unless you
 742           specifically require this or are unsure, say N.
 743
 744 config CPU_CACHE_ROUND_ROBIN
 745         bool "Round robin I and D cache replacement algorithm"
 746         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 747         help
 748           Say Y here to use the predictable round-robin cache replacement
 749           policy.  Unless you specifically require this or are unsure, say N.
 750
 751 config CPU_BPREDICT_DISABLE
 752         bool "Disable branch prediction"
 753         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
 754         help
 755           Say Y here to disable branch prediction.  If unsure, say N.
 756
 757 config TLS_REG_EMUL
 758         bool
 759         help
 760           An SMP system using a pre-ARMv6 processor (there are apparently
 761           a few prototypes like that in existence) and therefore access to
 762           that required register must be emulated.
 763
 764 config NEEDS_SYSCALL_FOR_CMPXCHG
 765         bool
 766         help
 767           SMP on a pre-ARMv6 processor?  Well OK then.
 768           Forget about fast user space cmpxchg support.
 769           It is just not possible.
 770
 771 config DMA_CACHE_RWFO
 772         bool "Enable read/write for ownership DMA cache maintenance"
 773         depends on CPU_V6K && SMP
 774         default y
 775         help
 776           The Snoop Control Unit on ARM11MPCore does not detect the
 777           cache maintenance operations and the dma_{map,unmap}_area()
 778           functions may leave stale cache entries on other CPUs. By
 779           enabling this option, Read or Write For Ownership in the ARMv6
 780           DMA cache maintenance functions is performed. These LDR/STR
 781           instructions change the cache line state to shared or modified
 782           so that the cache operation has the desired effect.
 783
 784           Note that the workaround is only valid on processors that do
 785           not perform speculative loads into the D-cache. For such
 786           processors, if cache maintenance operations are not broadcast
 787           in hardware, other workarounds are needed (e.g. cache
 788           maintenance broadcasting in software via FIQ).
 789
 790 config OUTER_CACHE
 791         bool
 792
 793 config OUTER_CACHE_SYNC
 794         bool
 795         help
 796           The outer cache has a outer_cache_fns.sync function pointer
 797           that can be used to drain the write buffer of the outer cache.
 798
 799 config CACHE_FEROCEON_L2
 800         bool "Enable the Feroceon L2 cache controller"
 801         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
 802         default y
 803         select OUTER_CACHE
 804         help
 805           This option enables the Feroceon L2 cache controller.
 806
 807 config CACHE_FEROCEON_L2_WRITETHROUGH
 808         bool "Force Feroceon L2 cache write through"
 809         depends on CACHE_FEROCEON_L2
 810         help
 811           Say Y here to use the Feroceon L2 cache in writethrough mode.
 812           Unless you specifically require this, say N for writeback mode.
 813
 814 config MIGHT_HAVE_CACHE_L2X0
 815         bool
 816         help
 817           This option should be selected by machines which have a L2x0
 818           or PL310 cache controller, but where its use is optional.
 819
 820           The only effect of this option is to make CACHE_L2X0 and
 821           related options available to the user for configuration.
 822
 823           Boards or SoCs which always require the cache controller
 824           support to be present should select CACHE_L2X0 directly
 825           instead of this option, thus preventing the user from
 826           inadvertently configuring a broken kernel.
 827
 828 config CACHE_L2X0
 829         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
 830         default MIGHT_HAVE_CACHE_L2X0
 831         select OUTER_CACHE
 832         select OUTER_CACHE_SYNC
 833         help
 834           This option enables the L2x0 PrimeCell.
 835
 836 config CACHE_PL310
 837         bool
 838         depends on CACHE_L2X0
 839         default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
 840         help
 841           This option enables optimisations for the PL310 cache
 842           controller.
 843
 844 config CACHE_TAUROS2
 845         bool "Enable the Tauros2 L2 cache controller"
 846         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
 847         default y
 848         select OUTER_CACHE
 849         help
 850           This option enables the Tauros2 L2 cache controller (as
 851           found on PJ1/PJ4).
 852
 853 config CACHE_XSC3L2
 854         bool "Enable the L2 cache on XScale3"
 855         depends on CPU_XSC3
 856         default y
 857         select OUTER_CACHE
 858         help
 859           This option enables the L2 cache on XScale3.
 860
 861 config ARM_L1_CACHE_SHIFT_6
 862         bool
 863         default y if CPU_V7
 864         help
 865           Setting ARM L1 cache line size to 64 Bytes.
 866
 867 config ARM_L1_CACHE_SHIFT
 868         int
 869         default 6 if ARM_L1_CACHE_SHIFT_6
 870         default 5
 871
 872 config ARM_DMA_MEM_BUFFERABLE
 873         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
 874         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
 875                      MACH_REALVIEW_PB11MP)
 876         default y if CPU_V6 || CPU_V6K || CPU_V7
 877         help
 878           Historically, the kernel has used strongly ordered mappings to
 879           provide DMA coherent memory.  With the advent of ARMv7, mapping
 880           memory with differing types results in unpredictable behaviour,
 881           so on these CPUs, this option is forced on.
 882
 883           Multiple mappings with differing attributes is also unpredictable
 884           on ARMv6 CPUs, but since they do not have aggressive speculative
 885           prefetch, no harm appears to occur.
 886
 887           However, drivers may be missing the necessary barriers for ARMv6,
 888           and therefore turning this on may result in unpredictable driver
 889           behaviour.  Therefore, we offer this as an option.
 890
 891           You are recommended say 'Y' here and debug any affected drivers.
 892
 893 config ARCH_HAS_BARRIERS
 894         bool
 895         help
 896           This option allows the use of custom mandatory barriers
 897           included via the mach/barriers.h file.