arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 config CPU_32
   4         bool
   5         default y
   6
   7 # Select CPU types depending on the architecture selected.  This selects
   8 # which CPUs we support in the kernel image, and the compiler instruction
   9 # optimiser behaviour.
  10
  11 # ARM610
  12 config CPU_ARM610
  13         bool "Support ARM610 processor"
  14         depends on ARCH_RPC
  15         select CPU_32v3
  16         select CPU_CACHE_V3
  17         select CPU_CACHE_VIVT
  18         select CPU_COPY_V3 if MMU
  19         select CPU_TLB_V3 if MMU
  20         help
  21           The ARM610 is the successor to the ARM3 processor
  22           and was produced by VLSI Technology Inc.
  23
  24           Say Y if you want support for the ARM610 processor.
  25           Otherwise, say N.
  26
  27 # ARM710
  28 config CPU_ARM710
  29         bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  30         default y if ARCH_CLPS7500
  31         select CPU_32v3
  32         select CPU_CACHE_V3
  33         select CPU_CACHE_VIVT
  34         select CPU_COPY_V3 if MMU
  35         select CPU_TLB_V3 if MMU
  36         help
  37           A 32-bit RISC microprocessor based on the ARM7 processor core
  38           designed by Advanced RISC Machines Ltd. The ARM710 is the
  39           successor to the ARM610 processor. It was released in
  40           July 1994 by VLSI Technology Inc.
  41
  42           Say Y if you want support for the ARM710 processor.
  43           Otherwise, say N.
  44
  45 # ARM720T
  46 config CPU_ARM720T
  47         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  48         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  49         select CPU_32v4
  50         select CPU_ABRT_LV4T
  51         select CPU_CACHE_V4
  52         select CPU_CACHE_VIVT
  53         select CPU_COPY_V4WT if MMU
  54         select CPU_TLB_V4WT if MMU
  55         help
  56           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  57           MMU built around an ARM7TDMI core.
  58
  59           Say Y if you want support for the ARM720T processor.
  60           Otherwise, say N.
  61
  62 # ARM920T
  63 config CPU_ARM920T
  64         bool "Support ARM920T processor"
  65         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
  66         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
  67         select CPU_32v4
  68         select CPU_ABRT_EV4T
  69         select CPU_CACHE_V4WT
  70         select CPU_CACHE_VIVT
  71         select CPU_COPY_V4WB if MMU
  72         select CPU_TLB_V4WBI if MMU
  73         help
  74           The ARM920T is licensed to be produced by numerous vendors,
  75           and is used in the Maverick EP9312 and the Samsung S3C2410.
  76
  77           More information on the Maverick EP9312 at
  78           <http://linuxdevices.com/products/PD2382866068.html>.
  79
  80           Say Y if you want support for the ARM920T processor.
  81           Otherwise, say N.
  82
  83 # ARM922T
  84 config CPU_ARM922T
  85         bool "Support ARM922T processor" if ARCH_INTEGRATOR
  86         depends on ARCH_LH7A40X || ARCH_INTEGRATOR
  87         default y if ARCH_LH7A40X
  88         select CPU_32v4
  89         select CPU_ABRT_EV4T
  90         select CPU_CACHE_V4WT
  91         select CPU_CACHE_VIVT
  92         select CPU_COPY_V4WB if MMU
  93         select CPU_TLB_V4WBI if MMU
  94         help
  95           The ARM922T is a version of the ARM920T, but with smaller
  96           instruction and data caches. It is used in Altera's
  97           Excalibur XA device family.
  98
  99           Say Y if you want support for the ARM922T processor.
 100           Otherwise, say N.
 101
 102 # ARM925T
 103 config CPU_ARM925T
 104         bool "Support ARM925T processor" if ARCH_OMAP1
 105         depends on ARCH_OMAP15XX
 106         default y if ARCH_OMAP15XX
 107         select CPU_32v4
 108         select CPU_ABRT_EV4T
 109         select CPU_CACHE_V4WT
 110         select CPU_CACHE_VIVT
 111         select CPU_COPY_V4WB if MMU
 112         select CPU_TLB_V4WBI if MMU
 113         help
 114           The ARM925T is a mix between the ARM920T and ARM926T, but with
 115           different instruction and data caches. It is used in TI's OMAP
 116           device family.
 117
 118           Say Y if you want support for the ARM925T processor.
 119           Otherwise, say N.
 120
 121 # ARM926T
 122 config CPU_ARM926T
 123         bool "Support ARM926T processor"
 124         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
 125         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
 126         select CPU_32v5
 127         select CPU_ABRT_EV5TJ
 128         select CPU_CACHE_VIVT
 129         select CPU_COPY_V4WB if MMU
 130         select CPU_TLB_V4WBI if MMU
 131         help
 132           This is a variant of the ARM920.  It has slightly different
 133           instruction sequences for cache and TLB operations.  Curiously,
 134           there is no documentation on it at the ARM corporate website.
 135
 136           Say Y if you want support for the ARM926T processor.
 137           Otherwise, say N.
 138
 139 # ARM1020 - needs validating
 140 config CPU_ARM1020
 141         bool "Support ARM1020T (rev 0) processor"
 142         depends on ARCH_INTEGRATOR
 143         select CPU_32v5
 144         select CPU_ABRT_EV4T
 145         select CPU_CACHE_V4WT
 146         select CPU_CACHE_VIVT
 147         select CPU_COPY_V4WB if MMU
 148         select CPU_TLB_V4WBI if MMU
 149         help
 150           The ARM1020 is the 32K cached version of the ARM10 processor,
 151           with an addition of a floating-point unit.
 152
 153           Say Y if you want support for the ARM1020 processor.
 154           Otherwise, say N.
 155
 156 # ARM1020E - needs validating
 157 config CPU_ARM1020E
 158         bool "Support ARM1020E processor"
 159         depends on ARCH_INTEGRATOR
 160         select CPU_32v5
 161         select CPU_ABRT_EV4T
 162         select CPU_CACHE_V4WT
 163         select CPU_CACHE_VIVT
 164         select CPU_COPY_V4WB if MMU
 165         select CPU_TLB_V4WBI if MMU
 166         depends on n
 167
 168 # ARM1022E
 169 config CPU_ARM1022
 170         bool "Support ARM1022E processor"
 171         depends on ARCH_INTEGRATOR
 172         select CPU_32v5
 173         select CPU_ABRT_EV4T
 174         select CPU_CACHE_VIVT
 175         select CPU_COPY_V4WB if MMU # can probably do better
 176         select CPU_TLB_V4WBI if MMU
 177         help
 178           The ARM1022E is an implementation of the ARMv5TE architecture
 179           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 180           embedded trace macrocell, and a floating-point unit.
 181
 182           Say Y if you want support for the ARM1022E processor.
 183           Otherwise, say N.
 184
 185 # ARM1026EJ-S
 186 config CPU_ARM1026
 187         bool "Support ARM1026EJ-S processor"
 188         depends on ARCH_INTEGRATOR
 189         select CPU_32v5
 190         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 191         select CPU_CACHE_VIVT
 192         select CPU_COPY_V4WB if MMU # can probably do better
 193         select CPU_TLB_V4WBI if MMU
 194         help
 195           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 196           based upon the ARM10 integer core.
 197
 198           Say Y if you want support for the ARM1026EJ-S processor.
 199           Otherwise, say N.
 200
 201 # SA110
 202 config CPU_SA110
 203         bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
 204         default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
 205         select CPU_32v3 if ARCH_RPC
 206         select CPU_32v4 if !ARCH_RPC
 207         select CPU_ABRT_EV4
 208         select CPU_CACHE_V4WB
 209         select CPU_CACHE_VIVT
 210         select CPU_COPY_V4WB if MMU
 211         select CPU_TLB_V4WB if MMU
 212         help
 213           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 214           is available at five speeds ranging from 100 MHz to 233 MHz.
 215           More information is available at
 216           <http://developer.intel.com/design/strong/sa110.htm>.
 217
 218           Say Y if you want support for the SA-110 processor.
 219           Otherwise, say N.
 220
 221 # SA1100
 222 config CPU_SA1100
 223         bool
 224         depends on ARCH_SA1100
 225         default y
 226         select CPU_32v4
 227         select CPU_ABRT_EV4
 228         select CPU_CACHE_V4WB
 229         select CPU_CACHE_VIVT
 230         select CPU_TLB_V4WB if MMU
 231
 232 # XScale
 233 config CPU_XSCALE
 234         bool
 235         depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
 236         default y
 237         select CPU_32v5
 238         select CPU_ABRT_EV5T
 239         select CPU_CACHE_VIVT
 240         select CPU_TLB_V4WBI if MMU
 241
 242 # XScale Core Version 3
 243 config CPU_XSC3
 244         bool
 245         depends on ARCH_IXP23XX
 246         default y
 247         select CPU_32v5
 248         select CPU_ABRT_EV5T
 249         select CPU_CACHE_VIVT
 250         select CPU_TLB_V4WBI if MMU
 251         select IO_36
 252
 253 # ARMv6
 254 config CPU_V6
 255         bool "Support ARM V6 processor"
 256         depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
 257         select CPU_32v6
 258         select CPU_ABRT_EV6
 259         select CPU_CACHE_V6
 260         select CPU_CACHE_VIPT
 261         select CPU_COPY_V6 if MMU
 262         select CPU_TLB_V6 if MMU
 263
 264 # ARMv6k
 265 config CPU_32v6K
 266         bool "Support ARM V6K processor extensions" if !SMP
 267         depends on CPU_V6
 268         default y if SMP
 269         help
 270           Say Y here if your ARMv6 processor supports the 'K' extension.
 271           This enables the kernel to use some instructions not present
 272           on previous processors, and as such a kernel build with this
 273           enabled will not boot on processors with do not support these
 274           instructions.
 275
 276 # Figure out what processor architecture version we should be using.
 277 # This defines the compiler instruction set which depends on the machine type.
 278 config CPU_32v3
 279         bool
 280         select TLS_REG_EMUL if SMP || !MMU
 281         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 282
 283 config CPU_32v4
 284         bool
 285         select TLS_REG_EMUL if SMP || !MMU
 286         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 287
 288 config CPU_32v5
 289         bool
 290         select TLS_REG_EMUL if SMP || !MMU
 291         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 292
 293 config CPU_32v6
 294         bool
 295
 296 # The abort model
 297 config CPU_ABRT_EV4
 298         bool
 299
 300 config CPU_ABRT_EV4T
 301         bool
 302
 303 config CPU_ABRT_LV4T
 304         bool
 305
 306 config CPU_ABRT_EV5T
 307         bool
 308
 309 config CPU_ABRT_EV5TJ
 310         bool
 311
 312 config CPU_ABRT_EV6
 313         bool
 314
 315 # The cache model
 316 config CPU_CACHE_V3
 317         bool
 318
 319 config CPU_CACHE_V4
 320         bool
 321
 322 config CPU_CACHE_V4WT
 323         bool
 324
 325 config CPU_CACHE_V4WB
 326         bool
 327
 328 config CPU_CACHE_V6
 329         bool
 330
 331 config CPU_CACHE_VIVT
 332         bool
 333
 334 config CPU_CACHE_VIPT
 335         bool
 336
 337 if MMU
 338 # The copy-page model
 339 config CPU_COPY_V3
 340         bool
 341
 342 config CPU_COPY_V4WT
 343         bool
 344
 345 config CPU_COPY_V4WB
 346         bool
 347
 348 config CPU_COPY_V6
 349         bool
 350
 351 # This selects the TLB model
 352 config CPU_TLB_V3
 353         bool
 354         help
 355           ARM Architecture Version 3 TLB.
 356
 357 config CPU_TLB_V4WT
 358         bool
 359         help
 360           ARM Architecture Version 4 TLB with writethrough cache.
 361
 362 config CPU_TLB_V4WB
 363         bool
 364         help
 365           ARM Architecture Version 4 TLB with writeback cache.
 366
 367 config CPU_TLB_V4WBI
 368         bool
 369         help
 370           ARM Architecture Version 4 TLB with writeback cache and invalidate
 371           instruction cache entry.
 372
 373 config CPU_TLB_V6
 374         bool
 375
 376 endif
 377
 378 #
 379 # CPU supports 36-bit I/O
 380 #
 381 config IO_36
 382         bool
 383
 384 comment "Processor Features"
 385
 386 config ARM_THUMB
 387         bool "Support Thumb user binaries"
 388         depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
 389         default y
 390         help
 391           Say Y if you want to include kernel support for running user space
 392           Thumb binaries.
 393
 394           The Thumb instruction set is a compressed form of the standard ARM
 395           instruction set resulting in smaller binaries at the expense of
 396           slightly less efficient code.
 397
 398           If you don't know what this all is, saying Y is a safe choice.
 399
 400 config CPU_BIG_ENDIAN
 401         bool "Build big-endian kernel"
 402         depends on ARCH_SUPPORTS_BIG_ENDIAN
 403         help
 404           Say Y if you plan on running a kernel in big-endian mode.
 405           Note that your board must be properly built and your board
 406           port must properly enable any big-endian related features
 407           of your chipset/board/processor.
 408
 409 config CPU_ICACHE_DISABLE
 410         bool "Disable I-Cache"
 411         depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
 412         help
 413           Say Y here to disable the processor instruction cache. Unless
 414           you have a reason not to or are unsure, say N.
 415
 416 config CPU_DCACHE_DISABLE
 417         bool "Disable D-Cache"
 418         depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
 419         help
 420           Say Y here to disable the processor data cache. Unless
 421           you have a reason not to or are unsure, say N.
 422
 423 config CPU_DCACHE_WRITETHROUGH
 424         bool "Force write through D-cache"
 425         depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
 426         default y if CPU_ARM925T
 427         help
 428           Say Y here to use the data cache in writethrough mode. Unless you
 429           specifically require this or are unsure, say N.
 430
 431 config CPU_CACHE_ROUND_ROBIN
 432         bool "Round robin I and D cache replacement algorithm"
 433         depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 434         help
 435           Say Y here to use the predictable round-robin cache replacement
 436           policy.  Unless you specifically require this or are unsure, say N.
 437
 438 config CPU_BPREDICT_DISABLE
 439         bool "Disable branch prediction"
 440         depends on CPU_ARM1020 || CPU_V6
 441         help
 442           Say Y here to disable branch prediction.  If unsure, say N.
 443
 444 config TLS_REG_EMUL
 445         bool
 446         help
 447           An SMP system using a pre-ARMv6 processor (there are apparently
 448           a few prototypes like that in existence) and therefore access to
 449           that required register must be emulated.
 450
 451 config HAS_TLS_REG
 452         bool
 453         depends on !TLS_REG_EMUL
 454         default y if SMP || CPU_32v7
 455         help
 456           This selects support for the CP15 thread register.
 457           It is defined to be available on some ARMv6 processors (including
 458           all SMP capable ARMv6's) or later processors.  User space may
 459           assume directly accessing that register and always obtain the
 460           expected value only on ARMv7 and above.
 461
 462 config NEEDS_SYSCALL_FOR_CMPXCHG
 463         bool
 464         help
 465           SMP on a pre-ARMv6 processor?  Well OK then.
 466           Forget about fast user space cmpxchg support.
 467           It is just not possible.
 468