arch/arm/mm/cache-l2x0.c

   1 /*
   2  * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
   3  *
   4  * Copyright (C) 2007 ARM Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18  */
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25
  26 #define CACHE_LINE_SIZE         32
  27
  28 static void __iomem *l2x0_base;
  29 static DEFINE_SPINLOCK(l2x0_lock);
  30
  31 static inline void cache_wait(void __iomem *reg, unsigned long mask)
  32 {
  33         /* wait for the operation to complete */
  34         while (readl(reg) & mask)
  35                 ;
  36 }
  37
  38 static inline void cache_sync(void)
  39 {
  40         void __iomem *base = l2x0_base;
  41         writel(0, base + L2X0_CACHE_SYNC);
  42         cache_wait(base + L2X0_CACHE_SYNC, 1);
  43 }
  44
  45 static inline void l2x0_clean_line(unsigned long addr)
  46 {
  47         void __iomem *base = l2x0_base;
  48         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  49         writel(addr, base + L2X0_CLEAN_LINE_PA);
  50 }
  51
  52 static inline void l2x0_inv_line(unsigned long addr)
  53 {
  54         void __iomem *base = l2x0_base;
  55         cache_wait(base + L2X0_INV_LINE_PA, 1);
  56         writel(addr, base + L2X0_INV_LINE_PA);
  57 }
  58
  59 #ifdef CONFIG_PL310_ERRATA_588369
  60 static void debug_writel(unsigned long val)
  61 {
  62         extern void omap_smc1(u32 fn, u32 arg);
  63
  64         /*
  65          * Texas Instrument secure monitor api to modify the
  66          * PL310 Debug Control Register.
  67          */
  68         omap_smc1(0x100, val);
  69 }
  70
  71 static inline void l2x0_flush_line(unsigned long addr)
  72 {
  73         void __iomem *base = l2x0_base;
  74
  75         /* Clean by PA followed by Invalidate by PA */
  76         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  77         writel(addr, base + L2X0_CLEAN_LINE_PA);
  78         cache_wait(base + L2X0_INV_LINE_PA, 1);
  79         writel(addr, base + L2X0_INV_LINE_PA);
  80 }
  81 #else
  82
  83 /* Optimised out for non-errata case */
  84 static inline void debug_writel(unsigned long val)
  85 {
  86 }
  87
  88 static inline void l2x0_flush_line(unsigned long addr)
  89 {
  90         void __iomem *base = l2x0_base;
  91         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
  92         writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
  93 }
  94 #endif
  95
  96 static void l2x0_cache_sync(void)
  97 {
  98         unsigned long flags;
  99
 100         spin_lock_irqsave(&l2x0_lock, flags);
 101         cache_sync();
 102         spin_unlock_irqrestore(&l2x0_lock, flags);
 103 }
 104
 105 static inline void l2x0_inv_all(void)
 106 {
 107         unsigned long flags;
 108
 109         /* invalidate all ways */
 110         spin_lock_irqsave(&l2x0_lock, flags);
 111         writel(0xff, l2x0_base + L2X0_INV_WAY);
 112         cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
 113         cache_sync();
 114         spin_unlock_irqrestore(&l2x0_lock, flags);
 115 }
 116
 117 static void l2x0_inv_range(unsigned long start, unsigned long end)
 118 {
 119         void __iomem *base = l2x0_base;
 120         unsigned long flags;
 121
 122         spin_lock_irqsave(&l2x0_lock, flags);
 123         if (start & (CACHE_LINE_SIZE - 1)) {
 124                 start &= ~(CACHE_LINE_SIZE - 1);
 125                 debug_writel(0x03);
 126                 l2x0_flush_line(start);
 127                 debug_writel(0x00);
 128                 start += CACHE_LINE_SIZE;
 129         }
 130
 131         if (end & (CACHE_LINE_SIZE - 1)) {
 132                 end &= ~(CACHE_LINE_SIZE - 1);
 133                 debug_writel(0x03);
 134                 l2x0_flush_line(end);
 135                 debug_writel(0x00);
 136         }
 137
 138         while (start < end) {
 139                 unsigned long blk_end = start + min(end - start, 4096UL);
 140
 141                 while (start < blk_end) {
 142                         l2x0_inv_line(start);
 143                         start += CACHE_LINE_SIZE;
 144                 }
 145
 146                 if (blk_end < end) {
 147                         spin_unlock_irqrestore(&l2x0_lock, flags);
 148                         spin_lock_irqsave(&l2x0_lock, flags);
 149                 }
 150         }
 151         cache_wait(base + L2X0_INV_LINE_PA, 1);
 152         cache_sync();
 153         spin_unlock_irqrestore(&l2x0_lock, flags);
 154 }
 155
 156 static void l2x0_clean_range(unsigned long start, unsigned long end)
 157 {
 158         void __iomem *base = l2x0_base;
 159         unsigned long flags;
 160
 161         spin_lock_irqsave(&l2x0_lock, flags);
 162         start &= ~(CACHE_LINE_SIZE - 1);
 163         while (start < end) {
 164                 unsigned long blk_end = start + min(end - start, 4096UL);
 165
 166                 while (start < blk_end) {
 167                         l2x0_clean_line(start);
 168                         start += CACHE_LINE_SIZE;
 169                 }
 170
 171                 if (blk_end < end) {
 172                         spin_unlock_irqrestore(&l2x0_lock, flags);
 173                         spin_lock_irqsave(&l2x0_lock, flags);
 174                 }
 175         }
 176         cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
 177         cache_sync();
 178         spin_unlock_irqrestore(&l2x0_lock, flags);
 179 }
 180
 181 static void l2x0_flush_range(unsigned long start, unsigned long end)
 182 {
 183         void __iomem *base = l2x0_base;
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&l2x0_lock, flags);
 187         start &= ~(CACHE_LINE_SIZE - 1);
 188         while (start < end) {
 189                 unsigned long blk_end = start + min(end - start, 4096UL);
 190
 191                 debug_writel(0x03);
 192                 while (start < blk_end) {
 193                         l2x0_flush_line(start);
 194                         start += CACHE_LINE_SIZE;
 195                 }
 196                 debug_writel(0x00);
 197
 198                 if (blk_end < end) {
 199                         spin_unlock_irqrestore(&l2x0_lock, flags);
 200                         spin_lock_irqsave(&l2x0_lock, flags);
 201                 }
 202         }
 203         cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
 204         cache_sync();
 205         spin_unlock_irqrestore(&l2x0_lock, flags);
 206 }
 207
 208 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 209 {
 210         __u32 aux;
 211
 212         l2x0_base = base;
 213
 214         /*
 215          * Check if l2x0 controller is already enabled.
 216          * If you are booting from non-secure mode
 217          * accessing the below registers will fault.
 218          */
 219         if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
 220
 221                 /* l2x0 controller is disabled */
 222
 223                 aux = readl(l2x0_base + L2X0_AUX_CTRL);
 224                 aux &= aux_mask;
 225                 aux |= aux_val;
 226                 writel(aux, l2x0_base + L2X0_AUX_CTRL);
 227
 228                 l2x0_inv_all();
 229
 230                 /* enable L2X0 */
 231                 writel(1, l2x0_base + L2X0_CTRL);
 232         }
 233
 234         outer_cache.inv_range = l2x0_inv_range;
 235         outer_cache.clean_range = l2x0_clean_range;
 236         outer_cache.flush_range = l2x0_flush_range;
 237         outer_cache.sync = l2x0_cache_sync;
 238
 239         printk(KERN_INFO "L2X0 cache controller enabled\n");
 240 }