2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
26 #define CACHE_LINE_SIZE 32
28 static void __iomem
*l2x0_base
;
29 static DEFINE_SPINLOCK(l2x0_lock
);
30 static uint32_t l2x0_way_mask
; /* Bitmask of active ways */
32 static inline void cache_wait(void __iomem
*reg
, unsigned long mask
)
34 /* wait for the operation to complete */
35 while (readl(reg
) & mask
)
39 static inline void cache_sync(void)
41 void __iomem
*base
= l2x0_base
;
42 writel(0, base
+ L2X0_CACHE_SYNC
);
43 cache_wait(base
+ L2X0_CACHE_SYNC
, 1);
46 static inline void l2x0_clean_line(unsigned long addr
)
48 void __iomem
*base
= l2x0_base
;
49 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
50 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
53 static inline void l2x0_inv_line(unsigned long addr
)
55 void __iomem
*base
= l2x0_base
;
56 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
57 writel(addr
, base
+ L2X0_INV_LINE_PA
);
60 #ifdef CONFIG_PL310_ERRATA_588369
61 static void debug_writel(unsigned long val
)
63 extern void omap_smc1(u32 fn
, u32 arg
);
66 * Texas Instrument secure monitor api to modify the
67 * PL310 Debug Control Register.
69 omap_smc1(0x100, val
);
72 static inline void l2x0_flush_line(unsigned long addr
)
74 void __iomem
*base
= l2x0_base
;
76 /* Clean by PA followed by Invalidate by PA */
77 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
78 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
79 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
80 writel(addr
, base
+ L2X0_INV_LINE_PA
);
84 /* Optimised out for non-errata case */
85 static inline void debug_writel(unsigned long val
)
89 static inline void l2x0_flush_line(unsigned long addr
)
91 void __iomem
*base
= l2x0_base
;
92 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
93 writel(addr
, base
+ L2X0_CLEAN_INV_LINE_PA
);
97 static inline void l2x0_inv_all(void)
101 /* invalidate all ways */
102 spin_lock_irqsave(&l2x0_lock
, flags
);
103 writel(l2x0_way_mask
, l2x0_base
+ L2X0_INV_WAY
);
104 cache_wait(l2x0_base
+ L2X0_INV_WAY
, l2x0_way_mask
);
106 spin_unlock_irqrestore(&l2x0_lock
, flags
);
109 static void l2x0_inv_range(unsigned long start
, unsigned long end
)
111 void __iomem
*base
= l2x0_base
;
114 spin_lock_irqsave(&l2x0_lock
, flags
);
115 if (start
& (CACHE_LINE_SIZE
- 1)) {
116 start
&= ~(CACHE_LINE_SIZE
- 1);
118 l2x0_flush_line(start
);
120 start
+= CACHE_LINE_SIZE
;
123 if (end
& (CACHE_LINE_SIZE
- 1)) {
124 end
&= ~(CACHE_LINE_SIZE
- 1);
126 l2x0_flush_line(end
);
130 while (start
< end
) {
131 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
133 while (start
< blk_end
) {
134 l2x0_inv_line(start
);
135 start
+= CACHE_LINE_SIZE
;
139 spin_unlock_irqrestore(&l2x0_lock
, flags
);
140 spin_lock_irqsave(&l2x0_lock
, flags
);
143 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
145 spin_unlock_irqrestore(&l2x0_lock
, flags
);
148 static void l2x0_clean_range(unsigned long start
, unsigned long end
)
150 void __iomem
*base
= l2x0_base
;
153 spin_lock_irqsave(&l2x0_lock
, flags
);
154 start
&= ~(CACHE_LINE_SIZE
- 1);
155 while (start
< end
) {
156 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
158 while (start
< blk_end
) {
159 l2x0_clean_line(start
);
160 start
+= CACHE_LINE_SIZE
;
164 spin_unlock_irqrestore(&l2x0_lock
, flags
);
165 spin_lock_irqsave(&l2x0_lock
, flags
);
168 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
170 spin_unlock_irqrestore(&l2x0_lock
, flags
);
173 static void l2x0_flush_range(unsigned long start
, unsigned long end
)
175 void __iomem
*base
= l2x0_base
;
178 spin_lock_irqsave(&l2x0_lock
, flags
);
179 start
&= ~(CACHE_LINE_SIZE
- 1);
180 while (start
< end
) {
181 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
184 while (start
< blk_end
) {
185 l2x0_flush_line(start
);
186 start
+= CACHE_LINE_SIZE
;
191 spin_unlock_irqrestore(&l2x0_lock
, flags
);
192 spin_lock_irqsave(&l2x0_lock
, flags
);
195 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
197 spin_unlock_irqrestore(&l2x0_lock
, flags
);
200 void __init
l2x0_init(void __iomem
*base
, __u32 aux_val
, __u32 aux_mask
)
209 cache_id
= readl(l2x0_base
+ L2X0_CACHE_ID
);
210 aux
= readl(l2x0_base
+ L2X0_AUX_CTRL
);
212 /* Determine the number of ways */
213 switch (cache_id
& L2X0_CACHE_ID_PART_MASK
) {
214 case L2X0_CACHE_ID_PART_L310
:
221 case L2X0_CACHE_ID_PART_L210
:
222 ways
= (aux
>> 13) & 0xf;
226 /* Assume unknown chips have 8 ways */
228 type
= "L2x0 series";
232 l2x0_way_mask
= (1 << ways
) - 1;
235 * Check if l2x0 controller is already enabled.
236 * If you are booting from non-secure mode
237 * accessing the below registers will fault.
239 if (!(readl(l2x0_base
+ L2X0_CTRL
) & 1)) {
241 /* l2x0 controller is disabled */
244 writel(aux
, l2x0_base
+ L2X0_AUX_CTRL
);
249 writel(1, l2x0_base
+ L2X0_CTRL
);
252 outer_cache
.inv_range
= l2x0_inv_range
;
253 outer_cache
.clean_range
= l2x0_clean_range
;
254 outer_cache
.flush_range
= l2x0_flush_range
;
256 printk(KERN_INFO
"%s cache controller enabled\n", type
);
257 printk(KERN_INFO
"l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
258 ways
, cache_id
, aux
);
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