2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
26 #define CACHE_LINE_SIZE 32
28 static void __iomem
*l2x0_base
;
29 static DEFINE_SPINLOCK(l2x0_lock
);
31 static inline void cache_wait(void __iomem
*reg
, unsigned long mask
)
33 /* wait for the operation to complete */
34 while (readl(reg
) & mask
)
38 static inline void cache_sync(void)
40 void __iomem
*base
= l2x0_base
;
41 writel(0, base
+ L2X0_CACHE_SYNC
);
42 cache_wait(base
+ L2X0_CACHE_SYNC
, 1);
45 static inline void l2x0_clean_line(unsigned long addr
)
47 void __iomem
*base
= l2x0_base
;
48 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
49 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
52 static inline void l2x0_inv_line(unsigned long addr
)
54 void __iomem
*base
= l2x0_base
;
55 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
56 writel(addr
, base
+ L2X0_INV_LINE_PA
);
59 #ifdef CONFIG_PL310_ERRATA_588369
60 static void debug_writel(unsigned long val
)
62 extern void omap_smc1(u32 fn
, u32 arg
);
65 * Texas Instrument secure monitor api to modify the
66 * PL310 Debug Control Register.
68 omap_smc1(0x100, val
);
71 static inline void l2x0_flush_line(unsigned long addr
)
73 void __iomem
*base
= l2x0_base
;
75 /* Clean by PA followed by Invalidate by PA */
76 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
77 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
78 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
79 writel(addr
, base
+ L2X0_INV_LINE_PA
);
83 /* Optimised out for non-errata case */
84 static inline void debug_writel(unsigned long val
)
88 static inline void l2x0_flush_line(unsigned long addr
)
90 void __iomem
*base
= l2x0_base
;
91 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
92 writel(addr
, base
+ L2X0_CLEAN_INV_LINE_PA
);
96 static void l2x0_cache_sync(void)
100 spin_lock_irqsave(&l2x0_lock
, flags
);
102 spin_unlock_irqrestore(&l2x0_lock
, flags
);
105 static inline void l2x0_inv_all(void)
109 /* invalidate all ways */
110 spin_lock_irqsave(&l2x0_lock
, flags
);
111 writel(0xff, l2x0_base
+ L2X0_INV_WAY
);
112 cache_wait(l2x0_base
+ L2X0_INV_WAY
, 0xff);
114 spin_unlock_irqrestore(&l2x0_lock
, flags
);
117 static void l2x0_inv_range(unsigned long start
, unsigned long end
)
119 void __iomem
*base
= l2x0_base
;
122 spin_lock_irqsave(&l2x0_lock
, flags
);
123 if (start
& (CACHE_LINE_SIZE
- 1)) {
124 start
&= ~(CACHE_LINE_SIZE
- 1);
126 l2x0_flush_line(start
);
128 start
+= CACHE_LINE_SIZE
;
131 if (end
& (CACHE_LINE_SIZE
- 1)) {
132 end
&= ~(CACHE_LINE_SIZE
- 1);
134 l2x0_flush_line(end
);
138 while (start
< end
) {
139 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
141 while (start
< blk_end
) {
142 l2x0_inv_line(start
);
143 start
+= CACHE_LINE_SIZE
;
147 spin_unlock_irqrestore(&l2x0_lock
, flags
);
148 spin_lock_irqsave(&l2x0_lock
, flags
);
151 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
153 spin_unlock_irqrestore(&l2x0_lock
, flags
);
156 static void l2x0_clean_range(unsigned long start
, unsigned long end
)
158 void __iomem
*base
= l2x0_base
;
161 spin_lock_irqsave(&l2x0_lock
, flags
);
162 start
&= ~(CACHE_LINE_SIZE
- 1);
163 while (start
< end
) {
164 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
166 while (start
< blk_end
) {
167 l2x0_clean_line(start
);
168 start
+= CACHE_LINE_SIZE
;
172 spin_unlock_irqrestore(&l2x0_lock
, flags
);
173 spin_lock_irqsave(&l2x0_lock
, flags
);
176 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
178 spin_unlock_irqrestore(&l2x0_lock
, flags
);
181 static void l2x0_flush_range(unsigned long start
, unsigned long end
)
183 void __iomem
*base
= l2x0_base
;
186 spin_lock_irqsave(&l2x0_lock
, flags
);
187 start
&= ~(CACHE_LINE_SIZE
- 1);
188 while (start
< end
) {
189 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
192 while (start
< blk_end
) {
193 l2x0_flush_line(start
);
194 start
+= CACHE_LINE_SIZE
;
199 spin_unlock_irqrestore(&l2x0_lock
, flags
);
200 spin_lock_irqsave(&l2x0_lock
, flags
);
203 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
205 spin_unlock_irqrestore(&l2x0_lock
, flags
);
208 void __init
l2x0_init(void __iomem
*base
, __u32 aux_val
, __u32 aux_mask
)
215 * Check if l2x0 controller is already enabled.
216 * If you are booting from non-secure mode
217 * accessing the below registers will fault.
219 if (!(readl(l2x0_base
+ L2X0_CTRL
) & 1)) {
221 /* l2x0 controller is disabled */
223 aux
= readl(l2x0_base
+ L2X0_AUX_CTRL
);
226 writel(aux
, l2x0_base
+ L2X0_AUX_CTRL
);
231 writel(1, l2x0_base
+ L2X0_CTRL
);
234 outer_cache
.inv_range
= l2x0_inv_range
;
235 outer_cache
.clean_range
= l2x0_clean_range
;
236 outer_cache
.flush_range
= l2x0_flush_range
;
237 outer_cache
.sync
= l2x0_cache_sync
;
239 printk(KERN_INFO
"L2X0 cache controller enabled\n");
This page took 0.036419 seconds and 6 git commands to generate.