2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
4 * Copyright (C) 2007 ARM Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
26 #define CACHE_LINE_SIZE 32
28 static void __iomem
*l2x0_base
;
29 static DEFINE_SPINLOCK(l2x0_lock
);
31 static inline void cache_wait(void __iomem
*reg
, unsigned long mask
)
33 /* wait for the operation to complete */
34 while (readl(reg
) & mask
)
38 static inline void cache_sync(void)
40 void __iomem
*base
= l2x0_base
;
41 writel(0, base
+ L2X0_CACHE_SYNC
);
42 cache_wait(base
+ L2X0_CACHE_SYNC
, 1);
45 static inline void l2x0_clean_line(unsigned long addr
)
47 void __iomem
*base
= l2x0_base
;
48 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
49 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
52 static inline void l2x0_inv_line(unsigned long addr
)
54 void __iomem
*base
= l2x0_base
;
55 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
56 writel(addr
, base
+ L2X0_INV_LINE_PA
);
59 #ifdef CONFIG_PL310_ERRATA_588369
60 static void debug_writel(unsigned long val
)
62 extern void omap_smc1(u32 fn
, u32 arg
);
65 * Texas Instrument secure monitor api to modify the
66 * PL310 Debug Control Register.
68 omap_smc1(0x100, val
);
71 static inline void l2x0_flush_line(unsigned long addr
)
73 void __iomem
*base
= l2x0_base
;
75 /* Clean by PA followed by Invalidate by PA */
76 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
77 writel(addr
, base
+ L2X0_CLEAN_LINE_PA
);
78 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
79 writel(addr
, base
+ L2X0_INV_LINE_PA
);
83 /* Optimised out for non-errata case */
84 static inline void debug_writel(unsigned long val
)
88 static inline void l2x0_flush_line(unsigned long addr
)
90 void __iomem
*base
= l2x0_base
;
91 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
92 writel(addr
, base
+ L2X0_CLEAN_INV_LINE_PA
);
96 static inline void l2x0_inv_all(void)
100 /* invalidate all ways */
101 spin_lock_irqsave(&l2x0_lock
, flags
);
102 writel(0xff, l2x0_base
+ L2X0_INV_WAY
);
103 cache_wait(l2x0_base
+ L2X0_INV_WAY
, 0xff);
105 spin_unlock_irqrestore(&l2x0_lock
, flags
);
108 static void l2x0_inv_range(unsigned long start
, unsigned long end
)
110 void __iomem
*base
= l2x0_base
;
113 spin_lock_irqsave(&l2x0_lock
, flags
);
114 if (start
& (CACHE_LINE_SIZE
- 1)) {
115 start
&= ~(CACHE_LINE_SIZE
- 1);
117 l2x0_flush_line(start
);
119 start
+= CACHE_LINE_SIZE
;
122 if (end
& (CACHE_LINE_SIZE
- 1)) {
123 end
&= ~(CACHE_LINE_SIZE
- 1);
125 l2x0_flush_line(end
);
129 while (start
< end
) {
130 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
132 while (start
< blk_end
) {
133 l2x0_inv_line(start
);
134 start
+= CACHE_LINE_SIZE
;
138 spin_unlock_irqrestore(&l2x0_lock
, flags
);
139 spin_lock_irqsave(&l2x0_lock
, flags
);
142 cache_wait(base
+ L2X0_INV_LINE_PA
, 1);
144 spin_unlock_irqrestore(&l2x0_lock
, flags
);
147 static void l2x0_clean_range(unsigned long start
, unsigned long end
)
149 void __iomem
*base
= l2x0_base
;
152 spin_lock_irqsave(&l2x0_lock
, flags
);
153 start
&= ~(CACHE_LINE_SIZE
- 1);
154 while (start
< end
) {
155 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
157 while (start
< blk_end
) {
158 l2x0_clean_line(start
);
159 start
+= CACHE_LINE_SIZE
;
163 spin_unlock_irqrestore(&l2x0_lock
, flags
);
164 spin_lock_irqsave(&l2x0_lock
, flags
);
167 cache_wait(base
+ L2X0_CLEAN_LINE_PA
, 1);
169 spin_unlock_irqrestore(&l2x0_lock
, flags
);
172 static void l2x0_flush_range(unsigned long start
, unsigned long end
)
174 void __iomem
*base
= l2x0_base
;
177 spin_lock_irqsave(&l2x0_lock
, flags
);
178 start
&= ~(CACHE_LINE_SIZE
- 1);
179 while (start
< end
) {
180 unsigned long blk_end
= start
+ min(end
- start
, 4096UL);
183 while (start
< blk_end
) {
184 l2x0_flush_line(start
);
185 start
+= CACHE_LINE_SIZE
;
190 spin_unlock_irqrestore(&l2x0_lock
, flags
);
191 spin_lock_irqsave(&l2x0_lock
, flags
);
194 cache_wait(base
+ L2X0_CLEAN_INV_LINE_PA
, 1);
196 spin_unlock_irqrestore(&l2x0_lock
, flags
);
199 void __init
l2x0_init(void __iomem
*base
, __u32 aux_val
, __u32 aux_mask
)
206 * Check if l2x0 controller is already enabled.
207 * If you are booting from non-secure mode
208 * accessing the below registers will fault.
210 if (!(readl(l2x0_base
+ L2X0_CTRL
) & 1)) {
212 /* l2x0 controller is disabled */
214 aux
= readl(l2x0_base
+ L2X0_AUX_CTRL
);
217 writel(aux
, l2x0_base
+ L2X0_AUX_CTRL
);
222 writel(1, l2x0_base
+ L2X0_CTRL
);
225 outer_cache
.inv_range
= l2x0_inv_range
;
226 outer_cache
.clean_range
= l2x0_clean_range
;
227 outer_cache
.flush_range
= l2x0_flush_range
;
229 printk(KERN_INFO
"L2X0 cache controller enabled\n");
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