arch/arm/mm/cache-v6.S

   1 /*
   2  *  linux/arch/arm/mm/cache-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv6 processor support.
  11  */
  12 #include <linux/linkage.h>
  13 #include <linux/init.h>
  14 #include <asm/assembler.h>
  15
  16 #include "proc-macros.S"
  17
  18 #define HARVARD_CACHE
  19 #define CACHE_LINE_SIZE         32
  20 #define D_CACHE_LINE_SIZE       32
  21 #define BTB_FLUSH_SIZE          8
  22
  23 /*
  24  *      v6_flush_cache_all()
  25  *
  26  *      Flush the entire cache.
  27  *
  28  *      It is assumed that:
  29  */
  30 ENTRY(v6_flush_kern_cache_all)
  31         mov     r0, #0
  32 #ifdef HARVARD_CACHE
  33         mcr     p15, 0, r0, c7, c14, 0          @ D cache clean+invalidate
  34         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
  35 #else
  36         mcr     p15, 0, r0, c7, c15, 0          @ Cache clean+invalidate
  37 #endif
  38         mov     pc, lr
  39
  40 /*
  41  *      v6_flush_cache_all()
  42  *
  43  *      Flush all TLB entries in a particular address space
  44  *
  45  *      - mm    - mm_struct describing address space
  46  */
  47 ENTRY(v6_flush_user_cache_all)
  48         /*FALLTHROUGH*/
  49
  50 /*
  51  *      v6_flush_cache_range(start, end, flags)
  52  *
  53  *      Flush a range of TLB entries in the specified address space.
  54  *
  55  *      - start - start address (may not be aligned)
  56  *      - end   - end address (exclusive, may not be aligned)
  57  *      - flags - vm_area_struct flags describing address space
  58  *
  59  *      It is assumed that:
  60  *      - we have a VIPT cache.
  61  */
  62 ENTRY(v6_flush_user_cache_range)
  63         mov     pc, lr
  64
  65 /*
  66  *      v6_coherent_kern_range(start,end)
  67  *
  68  *      Ensure that the I and D caches are coherent within specified
  69  *      region.  This is typically used when code has been written to
  70  *      a memory region, and will be executed.
  71  *
  72  *      - start   - virtual start address of region
  73  *      - end     - virtual end address of region
  74  *
  75  *      It is assumed that:
  76  *      - the Icache does not read data from the write buffer
  77  */
  78 ENTRY(v6_coherent_kern_range)
  79         /* FALLTHROUGH */
  80
  81 /*
  82  *      v6_coherent_user_range(start,end)
  83  *
  84  *      Ensure that the I and D caches are coherent within specified
  85  *      region.  This is typically used when code has been written to
  86  *      a memory region, and will be executed.
  87  *
  88  *      - start   - virtual start address of region
  89  *      - end     - virtual end address of region
  90  *
  91  *      It is assumed that:
  92  *      - the Icache does not read data from the write buffer
  93  */
  94 ENTRY(v6_coherent_user_range)
  95
  96 #ifdef HARVARD_CACHE
  97         bic     r0, r0, #CACHE_LINE_SIZE - 1
  98 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D line
  99         add     r0, r0, #CACHE_LINE_SIZE
 100         cmp     r0, r1
 101         blo     1b
 102 #endif
 103         mov     r0, #0
 104 #ifdef HARVARD_CACHE
 105         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 106         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
 107 #else
 108         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
 109 #endif
 110         mov     pc, lr
 111
 112 /*
 113  *      v6_flush_kern_dcache_page(kaddr)
 114  *
 115  *      Ensure that the data held in the page kaddr is written back
 116  *      to the page in question.
 117  *
 118  *      - kaddr   - kernel address (guaranteed to be page aligned)
 119  */
 120 ENTRY(v6_flush_kern_dcache_page)
 121         add     r1, r0, #PAGE_SZ
 122 1:
 123 #ifdef HARVARD_CACHE
 124         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 125 #else
 126         mcr     p15, 0, r0, c7, c15, 1          @ clean & invalidate unified line
 127 #endif
 128         add     r0, r0, #D_CACHE_LINE_SIZE
 129         cmp     r0, r1
 130         blo     1b
 131 #ifdef HARVARD_CACHE
 132         mov     r0, #0
 133         mcr     p15, 0, r0, c7, c10, 4
 134 #endif
 135         mov     pc, lr
 136
 137
 138 /*
 139  *      v6_dma_inv_range(start,end)
 140  *
 141  *      Invalidate the data cache within the specified region; we will
 142  *      be performing a DMA operation in this region and we want to
 143  *      purge old data in the cache.
 144  *
 145  *      - start   - virtual start address of region
 146  *      - end     - virtual end address of region
 147  */
 148 ENTRY(v6_dma_inv_range)
 149         tst     r0, #D_CACHE_LINE_SIZE - 1
 150         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 151 #ifdef HARVARD_CACHE
 152         mcrne   p15, 0, r0, c7, c10, 1          @ clean D line
 153 #else
 154         mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
 155 #endif
 156         tst     r1, #D_CACHE_LINE_SIZE - 1
 157         bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 158 #ifdef HARVARD_CACHE
 159         mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
 160 #else
 161         mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 162 #endif
 163 1:
 164 #ifdef HARVARD_CACHE
 165         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 166 #else
 167         mcr     p15, 0, r0, c7, c7, 1           @ invalidate unified line
 168 #endif
 169         add     r0, r0, #D_CACHE_LINE_SIZE
 170         cmp     r0, r1
 171         blo     1b
 172         mov     r0, #0
 173         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 174         mov     pc, lr
 175
 176 /*
 177  *      v6_dma_clean_range(start,end)
 178  *      - start   - virtual start address of region
 179  *      - end     - virtual end address of region
 180  */
 181 ENTRY(v6_dma_clean_range)
 182         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 183 1:
 184 #ifdef HARVARD_CACHE
 185         mcr     p15, 0, r0, c7, c10, 1          @ clean D line
 186 #else
 187         mcr     p15, 0, r0, c7, c11, 1          @ clean unified line
 188 #endif
 189         add     r0, r0, #D_CACHE_LINE_SIZE
 190         cmp     r0, r1
 191         blo     1b
 192         mov     r0, #0
 193         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 194         mov     pc, lr
 195
 196 /*
 197  *      v6_dma_flush_range(start,end)
 198  *      - start   - virtual start address of region
 199  *      - end     - virtual end address of region
 200  */
 201 ENTRY(v6_dma_flush_range)
 202         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 203 1:
 204 #ifdef HARVARD_CACHE
 205         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 206 #else
 207         mcr     p15, 0, r0, c7, c15, 1          @ clean & invalidate line
 208 #endif
 209         add     r0, r0, #D_CACHE_LINE_SIZE
 210         cmp     r0, r1
 211         blo     1b
 212         mov     r0, #0
 213         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 214         mov     pc, lr
 215
 216         __INITDATA
 217
 218         .type   v6_cache_fns, #object
 219 ENTRY(v6_cache_fns)
 220         .long   v6_flush_kern_cache_all
 221         .long   v6_flush_user_cache_all
 222         .long   v6_flush_user_cache_range
 223         .long   v6_coherent_kern_range
 224         .long   v6_coherent_user_range
 225         .long   v6_flush_kern_dcache_page
 226         .long   v6_dma_inv_range
 227         .long   v6_dma_clean_range
 228         .long   v6_dma_flush_range
 229         .size   v6_cache_fns, . - v6_cache_fns