arch/arm/mm/cache-v6.S

   1 /*
   2  *  linux/arch/arm/mm/cache-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv6 processor support.
  11  */
  12 #include <linux/linkage.h>
  13 #include <linux/init.h>
  14 #include <asm/assembler.h>
  15
  16 #include "proc-macros.S"
  17
  18 #define HARVARD_CACHE
  19 #define CACHE_LINE_SIZE         32
  20 #define D_CACHE_LINE_SIZE       32
  21 #define BTB_FLUSH_SIZE          8
  22
  23 /*
  24  *      v6_flush_cache_all()
  25  *
  26  *      Flush the entire cache.
  27  *
  28  *      It is assumed that:
  29  */
  30 ENTRY(v6_flush_kern_cache_all)
  31         mov     r0, #0
  32 #ifdef HARVARD_CACHE
  33         mcr     p15, 0, r0, c7, c14, 0          @ D cache clean+invalidate
  34         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
  35 #else
  36         mcr     p15, 0, r0, c7, c15, 0          @ Cache clean+invalidate
  37 #endif
  38         mov     pc, lr
  39
  40 /*
  41  *      v6_flush_cache_all()
  42  *
  43  *      Flush all TLB entries in a particular address space
  44  *
  45  *      - mm    - mm_struct describing address space
  46  */
  47 ENTRY(v6_flush_user_cache_all)
  48         /*FALLTHROUGH*/
  49
  50 /*
  51  *      v6_flush_cache_range(start, end, flags)
  52  *
  53  *      Flush a range of TLB entries in the specified address space.
  54  *
  55  *      - start - start address (may not be aligned)
  56  *      - end   - end address (exclusive, may not be aligned)
  57  *      - flags - vm_area_struct flags describing address space
  58  *
  59  *      It is assumed that:
  60  *      - we have a VIPT cache.
  61  */
  62 ENTRY(v6_flush_user_cache_range)
  63         mov     pc, lr
  64
  65 /*
  66  *      v6_coherent_kern_range(start,end)
  67  *
  68  *      Ensure that the I and D caches are coherent within specified
  69  *      region.  This is typically used when code has been written to
  70  *      a memory region, and will be executed.
  71  *
  72  *      - start   - virtual start address of region
  73  *      - end     - virtual end address of region
  74  *
  75  *      It is assumed that:
  76  *      - the Icache does not read data from the write buffer
  77  */
  78 ENTRY(v6_coherent_kern_range)
  79         /* FALLTHROUGH */
  80
  81 /*
  82  *      v6_coherent_user_range(start,end)
  83  *
  84  *      Ensure that the I and D caches are coherent within specified
  85  *      region.  This is typically used when code has been written to
  86  *      a memory region, and will be executed.
  87  *
  88  *      - start   - virtual start address of region
  89  *      - end     - virtual end address of region
  90  *
  91  *      It is assumed that:
  92  *      - the Icache does not read data from the write buffer
  93  */
  94 ENTRY(v6_coherent_user_range)
  95
  96 #ifdef HARVARD_CACHE
  97         bic     r0, r0, #CACHE_LINE_SIZE - 1
  98 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D line
  99         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
 100         add     r0, r0, #CACHE_LINE_SIZE
 101         cmp     r0, r1
 102         blo     1b
 103 #endif
 104         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
 105 #ifdef HARVARD_CACHE
 106         mov     r0, #0
 107         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 108 #endif
 109         mov     pc, lr
 110
 111 /*
 112  *      v6_flush_kern_dcache_page(kaddr)
 113  *
 114  *      Ensure that the data held in the page kaddr is written back
 115  *      to the page in question.
 116  *
 117  *      - kaddr   - kernel address (guaranteed to be page aligned)
 118  */
 119 ENTRY(v6_flush_kern_dcache_page)
 120         add     r1, r0, #PAGE_SZ
 121 1:
 122 #ifdef HARVARD_CACHE
 123         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 124 #else
 125         mcr     p15, 0, r0, c7, c15, 1          @ clean & invalidate unified line
 126 #endif
 127         add     r0, r0, #D_CACHE_LINE_SIZE
 128         cmp     r0, r1
 129         blo     1b
 130 #ifdef HARVARD_CACHE
 131         mov     r0, #0
 132         mcr     p15, 0, r0, c7, c10, 4
 133 #endif
 134         mov     pc, lr
 135
 136
 137 /*
 138  *      v6_dma_inv_range(start,end)
 139  *
 140  *      Invalidate the data cache within the specified region; we will
 141  *      be performing a DMA operation in this region and we want to
 142  *      purge old data in the cache.
 143  *
 144  *      - start   - virtual start address of region
 145  *      - end     - virtual end address of region
 146  */
 147 ENTRY(v6_dma_inv_range)
 148         tst     r0, #D_CACHE_LINE_SIZE - 1
 149         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 150 #ifdef HARVARD_CACHE
 151         mcrne   p15, 0, r0, c7, c10, 1          @ clean D line
 152 #else
 153         mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
 154 #endif
 155         tst     r1, #D_CACHE_LINE_SIZE - 1
 156         bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 157 #ifdef HARVARD_CACHE
 158         mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
 159 #else
 160         mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 161 #endif
 162 1:
 163 #ifdef HARVARD_CACHE
 164         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 165 #else
 166         mcr     p15, 0, r0, c7, c7, 1           @ invalidate unified line
 167 #endif
 168         add     r0, r0, #D_CACHE_LINE_SIZE
 169         cmp     r0, r1
 170         blo     1b
 171         mov     r0, #0
 172         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 173         mov     pc, lr
 174
 175 /*
 176  *      v6_dma_clean_range(start,end)
 177  *      - start   - virtual start address of region
 178  *      - end     - virtual end address of region
 179  */
 180 ENTRY(v6_dma_clean_range)
 181         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 182 1:
 183 #ifdef HARVARD_CACHE
 184         mcr     p15, 0, r0, c7, c10, 1          @ clean D line
 185 #else
 186         mcr     p15, 0, r0, c7, c11, 1          @ clean unified line
 187 #endif
 188         add     r0, r0, #D_CACHE_LINE_SIZE
 189         cmp     r0, r1
 190         blo     1b
 191         mov     r0, #0
 192         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 193         mov     pc, lr
 194
 195 /*
 196  *      v6_dma_flush_range(start,end)
 197  *      - start   - virtual start address of region
 198  *      - end     - virtual end address of region
 199  */
 200 ENTRY(v6_dma_flush_range)
 201         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 202 1:
 203 #ifdef HARVARD_CACHE
 204         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 205 #else
 206         mcr     p15, 0, r0, c7, c15, 1          @ clean & invalidate line
 207 #endif
 208         add     r0, r0, #D_CACHE_LINE_SIZE
 209         cmp     r0, r1
 210         blo     1b
 211         mov     r0, #0
 212         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 213         mov     pc, lr
 214
 215         __INITDATA
 216
 217         .type   v6_cache_fns, #object
 218 ENTRY(v6_cache_fns)
 219         .long   v6_flush_kern_cache_all
 220         .long   v6_flush_user_cache_all
 221         .long   v6_flush_user_cache_range
 222         .long   v6_coherent_kern_range
 223         .long   v6_coherent_user_range
 224         .long   v6_flush_kern_dcache_page
 225         .long   v6_dma_inv_range
 226         .long   v6_dma_clean_range
 227         .long   v6_dma_flush_range
 228         .size   v6_cache_fns, . - v6_cache_fns