arch/arm/mm/context.c

   1 /*
   2  *  linux/arch/arm/mm/context.c
   3  *
   4  *  Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/sched.h>
  12 #include <linux/mm.h>
  13 #include <linux/smp.h>
  14 #include <linux/percpu.h>
  15
  16 #include <asm/mmu_context.h>
  17 #include <asm/thread_notify.h>
  18 #include <asm/tlbflush.h>
  19
  20 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
  21 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
  22
  23 #ifdef CONFIG_ARM_LPAE
  24 void cpu_set_reserved_ttbr0(void)
  25 {
  26         unsigned long ttbl = __pa(swapper_pg_dir);
  27         unsigned long ttbh = 0;
  28
  29         /*
  30          * Set TTBR0 to swapper_pg_dir which contains only global entries. The
  31          * ASID is set to 0.
  32          */
  33         asm volatile(
  34         "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
  35         :
  36         : "r" (ttbl), "r" (ttbh));
  37         isb();
  38 }
  39 #else
  40 void cpu_set_reserved_ttbr0(void)
  41 {
  42         u32 ttb;
  43         /* Copy TTBR1 into TTBR0 */
  44         asm volatile(
  45         "       mrc     p15, 0, %0, c2, c0, 1           @ read TTBR1\n"
  46         "       mcr     p15, 0, %0, c2, c0, 0           @ set TTBR0\n"
  47         : "=r" (ttb));
  48         isb();
  49 }
  50 #endif
  51
  52 #ifdef CONFIG_PID_IN_CONTEXTIDR
  53 static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
  54                                void *t)
  55 {
  56         u32 contextidr;
  57         pid_t pid;
  58         struct thread_info *thread = t;
  59
  60         if (cmd != THREAD_NOTIFY_SWITCH)
  61                 return NOTIFY_DONE;
  62
  63         pid = task_pid_nr(thread->task) << ASID_BITS;
  64         asm volatile(
  65         "       mrc     p15, 0, %0, c13, c0, 1\n"
  66         "       bfi     %1, %0, #0, %2\n"
  67         "       mcr     p15, 0, %1, c13, c0, 1\n"
  68         : "=r" (contextidr), "+r" (pid)
  69         : "I" (ASID_BITS));
  70         isb();
  71
  72         return NOTIFY_OK;
  73 }
  74
  75 static struct notifier_block contextidr_notifier_block = {
  76         .notifier_call = contextidr_notifier,
  77 };
  78
  79 static int __init contextidr_notifier_init(void)
  80 {
  81         return thread_register_notifier(&contextidr_notifier_block);
  82 }
  83 arch_initcall(contextidr_notifier_init);
  84 #endif
  85
  86 /*
  87  * We fork()ed a process, and we need a new context for the child
  88  * to run in.
  89  */
  90 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
  91 {
  92         mm->context.id = 0;
  93         raw_spin_lock_init(&mm->context.id_lock);
  94 }
  95
  96 static void flush_context(void)
  97 {
  98         cpu_set_reserved_ttbr0();
  99         local_flush_tlb_all();
 100         if (icache_is_vivt_asid_tagged()) {
 101                 __flush_icache_all();
 102                 dsb();
 103         }
 104 }
 105
 106 #ifdef CONFIG_SMP
 107
 108 static void set_mm_context(struct mm_struct *mm, unsigned int asid)
 109 {
 110         unsigned long flags;
 111
 112         /*
 113          * Locking needed for multi-threaded applications where the
 114          * same mm->context.id could be set from different CPUs during
 115          * the broadcast. This function is also called via IPI so the
 116          * mm->context.id_lock has to be IRQ-safe.
 117          */
 118         raw_spin_lock_irqsave(&mm->context.id_lock, flags);
 119         if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
 120                 /*
 121                  * Old version of ASID found. Set the new one and
 122                  * reset mm_cpumask(mm).
 123                  */
 124                 mm->context.id = asid;
 125                 cpumask_clear(mm_cpumask(mm));
 126         }
 127         raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
 128
 129         /*
 130          * Set the mm_cpumask(mm) bit for the current CPU.
 131          */
 132         cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 133 }
 134
 135 /*
 136  * Reset the ASID on the current CPU. This function call is broadcast
 137  * from the CPU handling the ASID rollover and holding cpu_asid_lock.
 138  */
 139 static void reset_context(void *info)
 140 {
 141         unsigned int asid;
 142         unsigned int cpu = smp_processor_id();
 143         struct mm_struct *mm = current->active_mm;
 144
 145         smp_rmb();
 146         asid = cpu_last_asid + cpu + 1;
 147
 148         flush_context();
 149         set_mm_context(mm, asid);
 150
 151         /* set the new ASID */
 152         cpu_switch_mm(mm->pgd, mm);
 153 }
 154
 155 #else
 156
 157 static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
 158 {
 159         mm->context.id = asid;
 160         cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
 161 }
 162
 163 #endif
 164
 165 void __new_context(struct mm_struct *mm)
 166 {
 167         unsigned int asid;
 168
 169         raw_spin_lock(&cpu_asid_lock);
 170 #ifdef CONFIG_SMP
 171         /*
 172          * Check the ASID again, in case the change was broadcast from
 173          * another CPU before we acquired the lock.
 174          */
 175         if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
 176                 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 177                 raw_spin_unlock(&cpu_asid_lock);
 178                 return;
 179         }
 180 #endif
 181         /*
 182          * At this point, it is guaranteed that the current mm (with
 183          * an old ASID) isn't active on any other CPU since the ASIDs
 184          * are changed simultaneously via IPI.
 185          */
 186         asid = ++cpu_last_asid;
 187         if (asid == 0)
 188                 asid = cpu_last_asid = ASID_FIRST_VERSION;
 189
 190         /*
 191          * If we've used up all our ASIDs, we need
 192          * to start a new version and flush the TLB.
 193          */
 194         if (unlikely((asid & ~ASID_MASK) == 0)) {
 195                 asid = cpu_last_asid + smp_processor_id() + 1;
 196                 flush_context();
 197 #ifdef CONFIG_SMP
 198                 smp_wmb();
 199                 smp_call_function(reset_context, NULL, 1);
 200 #endif
 201                 cpu_last_asid += NR_CPUS;
 202         }
 203
 204         set_mm_context(mm, asid);
 205         raw_spin_unlock(&cpu_asid_lock);
 206 }