2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/fixmap.h>
26 #include <asm/sections.h>
27 #include <asm/setup.h>
28 #include <asm/smp_plat.h>
30 #include <asm/highmem.h>
31 #include <asm/system_info.h>
32 #include <asm/traps.h>
33 #include <asm/procinfo.h>
34 #include <asm/memory.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/pci.h>
39 #include <asm/fixmap.h>
46 * empty_zero_page is a special page that is used for
47 * zero-initialized data and COW.
49 struct page
*empty_zero_page
;
50 EXPORT_SYMBOL(empty_zero_page
);
53 * The pmd table for the upper-most set of pages.
57 pmdval_t user_pmd_table
= _PAGE_USER_TABLE
;
59 #define CPOLICY_UNCACHED 0
60 #define CPOLICY_BUFFERED 1
61 #define CPOLICY_WRITETHROUGH 2
62 #define CPOLICY_WRITEBACK 3
63 #define CPOLICY_WRITEALLOC 4
65 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
66 static unsigned int ecc_mask __initdata
= 0;
68 pgprot_t pgprot_kernel
;
69 pgprot_t pgprot_hyp_device
;
71 pgprot_t pgprot_s2_device
;
73 EXPORT_SYMBOL(pgprot_user
);
74 EXPORT_SYMBOL(pgprot_kernel
);
77 const char policy
[16];
84 #ifdef CONFIG_ARM_LPAE
85 #define s2_policy(policy) policy
87 #define s2_policy(policy) 0
90 static struct cachepolicy cache_policies
[] __initdata
= {
94 .pmd
= PMD_SECT_UNCACHED
,
95 .pte
= L_PTE_MT_UNCACHED
,
96 .pte_s2
= s2_policy(L_PTE_S2_MT_UNCACHED
),
100 .pmd
= PMD_SECT_BUFFERED
,
101 .pte
= L_PTE_MT_BUFFERABLE
,
102 .pte_s2
= s2_policy(L_PTE_S2_MT_UNCACHED
),
104 .policy
= "writethrough",
107 .pte
= L_PTE_MT_WRITETHROUGH
,
108 .pte_s2
= s2_policy(L_PTE_S2_MT_WRITETHROUGH
),
110 .policy
= "writeback",
113 .pte
= L_PTE_MT_WRITEBACK
,
114 .pte_s2
= s2_policy(L_PTE_S2_MT_WRITEBACK
),
116 .policy
= "writealloc",
118 .pmd
= PMD_SECT_WBWA
,
119 .pte
= L_PTE_MT_WRITEALLOC
,
120 .pte_s2
= s2_policy(L_PTE_S2_MT_WRITEBACK
),
124 #ifdef CONFIG_CPU_CP15
125 static unsigned long initial_pmd_value __initdata
= 0;
128 * Initialise the cache_policy variable with the initial state specified
129 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
130 * the C code sets the page tables up with the same policy as the head
131 * assembly code, which avoids an illegal state where the TLBs can get
132 * confused. See comments in early_cachepolicy() for more information.
134 void __init
init_default_cache_policy(unsigned long pmd
)
138 initial_pmd_value
= pmd
;
140 pmd
&= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE
| PMD_SECT_CACHEABLE
;
142 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++)
143 if (cache_policies
[i
].pmd
== pmd
) {
148 if (i
== ARRAY_SIZE(cache_policies
))
149 pr_err("ERROR: could not find cache policy\n");
153 * These are useful for identifying cache coherency problems by allowing
154 * the cache or the cache and writebuffer to be turned off. (Note: the
155 * write buffer should not be on and the cache off).
157 static int __init
early_cachepolicy(char *p
)
159 int i
, selected
= -1;
161 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
162 int len
= strlen(cache_policies
[i
].policy
);
164 if (memcmp(p
, cache_policies
[i
].policy
, len
) == 0) {
171 pr_err("ERROR: unknown or unsupported cache policy\n");
174 * This restriction is partly to do with the way we boot; it is
175 * unpredictable to have memory mapped using two different sets of
176 * memory attributes (shared, type, and cache attribs). We can not
177 * change these attributes once the initial assembly has setup the
180 if (cpu_architecture() >= CPU_ARCH_ARMv6
&& selected
!= cachepolicy
) {
181 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
182 cache_policies
[cachepolicy
].policy
);
186 if (selected
!= cachepolicy
) {
187 unsigned long cr
= __clear_cr(cache_policies
[selected
].cr_mask
);
188 cachepolicy
= selected
;
194 early_param("cachepolicy", early_cachepolicy
);
196 static int __init
early_nocache(char *__unused
)
198 char *p
= "buffered";
199 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p
);
200 early_cachepolicy(p
);
203 early_param("nocache", early_nocache
);
205 static int __init
early_nowrite(char *__unused
)
207 char *p
= "uncached";
208 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p
);
209 early_cachepolicy(p
);
212 early_param("nowb", early_nowrite
);
214 #ifndef CONFIG_ARM_LPAE
215 static int __init
early_ecc(char *p
)
217 if (memcmp(p
, "on", 2) == 0)
218 ecc_mask
= PMD_PROTECTION
;
219 else if (memcmp(p
, "off", 3) == 0)
223 early_param("ecc", early_ecc
);
226 #else /* ifdef CONFIG_CPU_CP15 */
228 static int __init
early_cachepolicy(char *p
)
230 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
232 early_param("cachepolicy", early_cachepolicy
);
234 static int __init
noalign_setup(char *__unused
)
236 pr_warn("noalign kernel parameter not supported without cp15\n");
238 __setup("noalign", noalign_setup
);
240 #endif /* ifdef CONFIG_CPU_CP15 / else */
242 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
243 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
244 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
246 static struct mem_type mem_types
[] = {
247 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
248 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_SHARED
|
250 .prot_pte_s2
= s2_policy(PROT_PTE_S2_DEVICE
) |
251 s2_policy(L_PTE_S2_MT_DEV_SHARED
) |
253 .prot_l1
= PMD_TYPE_TABLE
,
254 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_S
,
257 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
258 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_NONSHARED
,
259 .prot_l1
= PMD_TYPE_TABLE
,
260 .prot_sect
= PROT_SECT_DEVICE
,
263 [MT_DEVICE_CACHED
] = { /* ioremap_cached */
264 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_CACHED
,
265 .prot_l1
= PMD_TYPE_TABLE
,
266 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
269 [MT_DEVICE_WC
] = { /* ioremap_wc */
270 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_WC
,
271 .prot_l1
= PMD_TYPE_TABLE
,
272 .prot_sect
= PROT_SECT_DEVICE
,
276 .prot_pte
= PROT_PTE_DEVICE
,
277 .prot_l1
= PMD_TYPE_TABLE
,
278 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
282 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
283 .domain
= DOMAIN_KERNEL
,
285 #ifndef CONFIG_ARM_LPAE
287 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
288 .domain
= DOMAIN_KERNEL
,
292 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
294 .prot_l1
= PMD_TYPE_TABLE
,
295 .domain
= DOMAIN_VECTORS
,
297 [MT_HIGH_VECTORS
] = {
298 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
299 L_PTE_USER
| L_PTE_RDONLY
,
300 .prot_l1
= PMD_TYPE_TABLE
,
301 .domain
= DOMAIN_VECTORS
,
304 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
305 .prot_l1
= PMD_TYPE_TABLE
,
306 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
307 .domain
= DOMAIN_KERNEL
,
310 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
312 .prot_l1
= PMD_TYPE_TABLE
,
313 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
314 .domain
= DOMAIN_KERNEL
,
317 .prot_sect
= PMD_TYPE_SECT
,
318 .domain
= DOMAIN_KERNEL
,
320 [MT_MEMORY_RWX_NONCACHED
] = {
321 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
323 .prot_l1
= PMD_TYPE_TABLE
,
324 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
325 .domain
= DOMAIN_KERNEL
,
327 [MT_MEMORY_RW_DTCM
] = {
328 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
330 .prot_l1
= PMD_TYPE_TABLE
,
331 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
332 .domain
= DOMAIN_KERNEL
,
334 [MT_MEMORY_RWX_ITCM
] = {
335 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
336 .prot_l1
= PMD_TYPE_TABLE
,
337 .domain
= DOMAIN_KERNEL
,
339 [MT_MEMORY_RW_SO
] = {
340 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
341 L_PTE_MT_UNCACHED
| L_PTE_XN
,
342 .prot_l1
= PMD_TYPE_TABLE
,
343 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
| PMD_SECT_S
|
344 PMD_SECT_UNCACHED
| PMD_SECT_XN
,
345 .domain
= DOMAIN_KERNEL
,
347 [MT_MEMORY_DMA_READY
] = {
348 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
350 .prot_l1
= PMD_TYPE_TABLE
,
351 .domain
= DOMAIN_KERNEL
,
355 const struct mem_type
*get_mem_type(unsigned int type
)
357 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
359 EXPORT_SYMBOL(get_mem_type
);
361 static pte_t
*(*pte_offset_fixmap
)(pmd_t
*dir
, unsigned long addr
);
363 static pte_t bm_pte
[PTRS_PER_PTE
+ PTE_HWTABLE_PTRS
]
364 __aligned(PTE_HWTABLE_OFF
+ PTE_HWTABLE_SIZE
) __initdata
;
366 static pte_t
* __init
pte_offset_early_fixmap(pmd_t
*dir
, unsigned long addr
)
368 return &bm_pte
[pte_index(addr
)];
371 static pte_t
*pte_offset_late_fixmap(pmd_t
*dir
, unsigned long addr
)
373 return pte_offset_kernel(dir
, addr
);
376 static inline pmd_t
* __init
fixmap_pmd(unsigned long addr
)
378 pgd_t
*pgd
= pgd_offset_k(addr
);
379 pud_t
*pud
= pud_offset(pgd
, addr
);
380 pmd_t
*pmd
= pmd_offset(pud
, addr
);
385 void __init
early_fixmap_init(void)
390 * The early fixmap range spans multiple pmds, for which
391 * we are not prepared:
393 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region
) >> PMD_SHIFT
)
394 != FIXADDR_TOP
>> PMD_SHIFT
);
396 pmd
= fixmap_pmd(FIXADDR_TOP
);
397 pmd_populate_kernel(&init_mm
, pmd
, bm_pte
);
399 pte_offset_fixmap
= pte_offset_early_fixmap
;
403 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
404 * As a result, this can only be called with preemption disabled, as under
407 void __set_fixmap(enum fixed_addresses idx
, phys_addr_t phys
, pgprot_t prot
)
409 unsigned long vaddr
= __fix_to_virt(idx
);
410 pte_t
*pte
= pte_offset_fixmap(pmd_off_k(vaddr
), vaddr
);
412 /* Make sure fixmap region does not exceed available allocation. */
413 BUILD_BUG_ON(FIXADDR_START
+ (__end_of_fixed_addresses
* PAGE_SIZE
) >
415 BUG_ON(idx
>= __end_of_fixed_addresses
);
417 if (pgprot_val(prot
))
418 set_pte_at(NULL
, vaddr
, pte
,
419 pfn_pte(phys
>> PAGE_SHIFT
, prot
));
421 pte_clear(NULL
, vaddr
, pte
);
422 local_flush_tlb_kernel_range(vaddr
, vaddr
+ PAGE_SIZE
);
426 * Adjust the PMD section entries according to the CPU in use.
428 static void __init
build_mem_type_table(void)
430 struct cachepolicy
*cp
;
431 unsigned int cr
= get_cr();
432 pteval_t user_pgprot
, kern_pgprot
, vecs_pgprot
;
433 pteval_t hyp_device_pgprot
, s2_pgprot
, s2_device_pgprot
;
434 int cpu_arch
= cpu_architecture();
437 if (cpu_arch
< CPU_ARCH_ARMv6
) {
438 #if defined(CONFIG_CPU_DCACHE_DISABLE)
439 if (cachepolicy
> CPOLICY_BUFFERED
)
440 cachepolicy
= CPOLICY_BUFFERED
;
441 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
442 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
443 cachepolicy
= CPOLICY_WRITETHROUGH
;
446 if (cpu_arch
< CPU_ARCH_ARMv5
) {
447 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
448 cachepolicy
= CPOLICY_WRITEBACK
;
453 if (cachepolicy
!= CPOLICY_WRITEALLOC
) {
454 pr_warn("Forcing write-allocate cache policy for SMP\n");
455 cachepolicy
= CPOLICY_WRITEALLOC
;
457 if (!(initial_pmd_value
& PMD_SECT_S
)) {
458 pr_warn("Forcing shared mappings for SMP\n");
459 initial_pmd_value
|= PMD_SECT_S
;
464 * Strip out features not present on earlier architectures.
465 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
466 * without extended page tables don't have the 'Shared' bit.
468 if (cpu_arch
< CPU_ARCH_ARMv5
)
469 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
470 mem_types
[i
].prot_sect
&= ~PMD_SECT_TEX(7);
471 if ((cpu_arch
< CPU_ARCH_ARMv6
|| !(cr
& CR_XP
)) && !cpu_is_xsc3())
472 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
473 mem_types
[i
].prot_sect
&= ~PMD_SECT_S
;
476 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
477 * "update-able on write" bit on ARM610). However, Xscale and
478 * Xscale3 require this bit to be cleared.
480 if (cpu_is_xscale_family()) {
481 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
482 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
483 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
485 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
486 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
487 if (mem_types
[i
].prot_l1
)
488 mem_types
[i
].prot_l1
|= PMD_BIT4
;
489 if (mem_types
[i
].prot_sect
)
490 mem_types
[i
].prot_sect
|= PMD_BIT4
;
495 * Mark the device areas according to the CPU/architecture.
497 if (cpu_is_xsc3() || (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
))) {
498 if (!cpu_is_xsc3()) {
500 * Mark device regions on ARMv6+ as execute-never
501 * to prevent speculative instruction fetches.
503 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_XN
;
504 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_XN
;
505 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_XN
;
506 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_XN
;
508 /* Also setup NX memory mapping */
509 mem_types
[MT_MEMORY_RW
].prot_sect
|= PMD_SECT_XN
;
511 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
513 * For ARMv7 with TEX remapping,
514 * - shared device is SXCB=1100
515 * - nonshared device is SXCB=0100
516 * - write combine device mem is SXCB=0001
517 * (Uncached Normal memory)
519 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1);
520 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(1);
521 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
522 } else if (cpu_is_xsc3()) {
525 * - shared device is TEXCB=00101
526 * - nonshared device is TEXCB=01000
527 * - write combine device mem is TEXCB=00100
528 * (Inner/Outer Uncacheable in xsc3 parlance)
530 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED
;
531 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
532 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
535 * For ARMv6 and ARMv7 without TEX remapping,
536 * - shared device is TEXCB=00001
537 * - nonshared device is TEXCB=01000
538 * - write combine device mem is TEXCB=00100
539 * (Uncached Normal in ARMv6 parlance).
541 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
542 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
543 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
547 * On others, write combining is "Uncached/Buffered"
549 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
553 * Now deal with the memory-type mappings
555 cp
= &cache_policies
[cachepolicy
];
556 vecs_pgprot
= kern_pgprot
= user_pgprot
= cp
->pte
;
557 s2_pgprot
= cp
->pte_s2
;
558 hyp_device_pgprot
= mem_types
[MT_DEVICE
].prot_pte
;
559 s2_device_pgprot
= mem_types
[MT_DEVICE
].prot_pte_s2
;
561 #ifndef CONFIG_ARM_LPAE
563 * We don't use domains on ARMv6 (since this causes problems with
564 * v6/v7 kernels), so we must use a separate memory type for user
565 * r/o, kernel r/w to map the vectors page.
567 if (cpu_arch
== CPU_ARCH_ARMv6
)
568 vecs_pgprot
|= L_PTE_MT_VECTORS
;
571 * Check is it with support for the PXN bit
572 * in the Short-descriptor translation table format descriptors.
574 if (cpu_arch
== CPU_ARCH_ARMv7
&&
575 (read_cpuid_ext(CPUID_EXT_MMFR0
) & 0xF) >= 4) {
576 user_pmd_table
|= PMD_PXNTABLE
;
581 * ARMv6 and above have extended page tables.
583 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
584 #ifndef CONFIG_ARM_LPAE
586 * Mark cache clean areas and XIP ROM read only
587 * from SVC mode and no access from userspace.
589 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
590 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
591 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
595 * If the initial page tables were created with the S bit
596 * set, then we need to do the same here for the same
597 * reasons given in early_cachepolicy().
599 if (initial_pmd_value
& PMD_SECT_S
) {
600 user_pgprot
|= L_PTE_SHARED
;
601 kern_pgprot
|= L_PTE_SHARED
;
602 vecs_pgprot
|= L_PTE_SHARED
;
603 s2_pgprot
|= L_PTE_SHARED
;
604 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_S
;
605 mem_types
[MT_DEVICE_WC
].prot_pte
|= L_PTE_SHARED
;
606 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_S
;
607 mem_types
[MT_DEVICE_CACHED
].prot_pte
|= L_PTE_SHARED
;
608 mem_types
[MT_MEMORY_RWX
].prot_sect
|= PMD_SECT_S
;
609 mem_types
[MT_MEMORY_RWX
].prot_pte
|= L_PTE_SHARED
;
610 mem_types
[MT_MEMORY_RW
].prot_sect
|= PMD_SECT_S
;
611 mem_types
[MT_MEMORY_RW
].prot_pte
|= L_PTE_SHARED
;
612 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= L_PTE_SHARED
;
613 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= PMD_SECT_S
;
614 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_pte
|= L_PTE_SHARED
;
619 * Non-cacheable Normal - intended for memory areas that must
620 * not cause dirty cache line writebacks when used
622 if (cpu_arch
>= CPU_ARCH_ARMv6
) {
623 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
624 /* Non-cacheable Normal is XCB = 001 */
625 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|=
628 /* For both ARMv6 and non-TEX-remapping ARMv7 */
629 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|=
633 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= PMD_SECT_BUFFERABLE
;
636 #ifdef CONFIG_ARM_LPAE
638 * Do not generate access flag faults for the kernel mappings.
640 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
641 mem_types
[i
].prot_pte
|= PTE_EXT_AF
;
642 if (mem_types
[i
].prot_sect
)
643 mem_types
[i
].prot_sect
|= PMD_SECT_AF
;
645 kern_pgprot
|= PTE_EXT_AF
;
646 vecs_pgprot
|= PTE_EXT_AF
;
649 * Set PXN for user mappings
651 user_pgprot
|= PTE_EXT_PXN
;
654 for (i
= 0; i
< 16; i
++) {
655 pteval_t v
= pgprot_val(protection_map
[i
]);
656 protection_map
[i
] = __pgprot(v
| user_pgprot
);
659 mem_types
[MT_LOW_VECTORS
].prot_pte
|= vecs_pgprot
;
660 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= vecs_pgprot
;
662 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
663 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
664 L_PTE_DIRTY
| kern_pgprot
);
665 pgprot_s2
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| s2_pgprot
);
666 pgprot_s2_device
= __pgprot(s2_device_pgprot
);
667 pgprot_hyp_device
= __pgprot(hyp_device_pgprot
);
669 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
670 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
671 mem_types
[MT_MEMORY_RWX
].prot_sect
|= ecc_mask
| cp
->pmd
;
672 mem_types
[MT_MEMORY_RWX
].prot_pte
|= kern_pgprot
;
673 mem_types
[MT_MEMORY_RW
].prot_sect
|= ecc_mask
| cp
->pmd
;
674 mem_types
[MT_MEMORY_RW
].prot_pte
|= kern_pgprot
;
675 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= kern_pgprot
;
676 mem_types
[MT_MEMORY_RWX_NONCACHED
].prot_sect
|= ecc_mask
;
677 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
681 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
685 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
688 pr_info("Memory policy: %sData cache %s\n",
689 ecc_mask
? "ECC enabled, " : "", cp
->policy
);
691 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
692 struct mem_type
*t
= &mem_types
[i
];
694 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
696 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
700 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
701 pgprot_t
phys_mem_access_prot(struct file
*file
, unsigned long pfn
,
702 unsigned long size
, pgprot_t vma_prot
)
705 return pgprot_noncached(vma_prot
);
706 else if (file
->f_flags
& O_SYNC
)
707 return pgprot_writecombine(vma_prot
);
710 EXPORT_SYMBOL(phys_mem_access_prot
);
713 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
715 static void __init
*early_alloc_aligned(unsigned long sz
, unsigned long align
)
717 void *ptr
= __va(memblock_alloc(sz
, align
));
722 static void __init
*early_alloc(unsigned long sz
)
724 return early_alloc_aligned(sz
, sz
);
727 static void *__init
late_alloc(unsigned long sz
)
729 void *ptr
= (void *)__get_free_pages(PGALLOC_GFP
, get_order(sz
));
735 static pte_t
* __init
arm_pte_alloc(pmd_t
*pmd
, unsigned long addr
,
737 void *(*alloc
)(unsigned long sz
))
739 if (pmd_none(*pmd
)) {
740 pte_t
*pte
= alloc(PTE_HWTABLE_OFF
+ PTE_HWTABLE_SIZE
);
741 __pmd_populate(pmd
, __pa(pte
), prot
);
743 BUG_ON(pmd_bad(*pmd
));
744 return pte_offset_kernel(pmd
, addr
);
747 static pte_t
* __init
early_pte_alloc(pmd_t
*pmd
, unsigned long addr
,
750 return arm_pte_alloc(pmd
, addr
, prot
, early_alloc
);
753 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
754 unsigned long end
, unsigned long pfn
,
755 const struct mem_type
*type
,
756 void *(*alloc
)(unsigned long sz
),
759 pte_t
*pte
= arm_pte_alloc(pmd
, addr
, type
->prot_l1
, alloc
);
761 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)),
762 ng
? PTE_EXT_NG
: 0);
764 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
767 static void __init
__map_init_section(pmd_t
*pmd
, unsigned long addr
,
768 unsigned long end
, phys_addr_t phys
,
769 const struct mem_type
*type
, bool ng
)
773 #ifndef CONFIG_ARM_LPAE
775 * In classic MMU format, puds and pmds are folded in to
776 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
777 * group of L1 entries making up one logical pointer to
778 * an L2 table (2MB), where as PMDs refer to the individual
779 * L1 entries (1MB). Hence increment to get the correct
780 * offset for odd 1MB sections.
781 * (See arch/arm/include/asm/pgtable-2level.h)
783 if (addr
& SECTION_SIZE
)
787 *pmd
= __pmd(phys
| type
->prot_sect
| (ng
? PMD_SECT_nG
: 0));
788 phys
+= SECTION_SIZE
;
789 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
794 static void __init
alloc_init_pmd(pud_t
*pud
, unsigned long addr
,
795 unsigned long end
, phys_addr_t phys
,
796 const struct mem_type
*type
,
797 void *(*alloc
)(unsigned long sz
), bool ng
)
799 pmd_t
*pmd
= pmd_offset(pud
, addr
);
804 * With LPAE, we must loop over to map
805 * all the pmds for the given range.
807 next
= pmd_addr_end(addr
, end
);
810 * Try a section mapping - addr, next and phys must all be
811 * aligned to a section boundary.
813 if (type
->prot_sect
&&
814 ((addr
| next
| phys
) & ~SECTION_MASK
) == 0) {
815 __map_init_section(pmd
, addr
, next
, phys
, type
, ng
);
817 alloc_init_pte(pmd
, addr
, next
,
818 __phys_to_pfn(phys
), type
, alloc
, ng
);
823 } while (pmd
++, addr
= next
, addr
!= end
);
826 static void __init
alloc_init_pud(pgd_t
*pgd
, unsigned long addr
,
827 unsigned long end
, phys_addr_t phys
,
828 const struct mem_type
*type
,
829 void *(*alloc
)(unsigned long sz
), bool ng
)
831 pud_t
*pud
= pud_offset(pgd
, addr
);
835 next
= pud_addr_end(addr
, end
);
836 alloc_init_pmd(pud
, addr
, next
, phys
, type
, alloc
, ng
);
838 } while (pud
++, addr
= next
, addr
!= end
);
841 #ifndef CONFIG_ARM_LPAE
842 static void __init
create_36bit_mapping(struct mm_struct
*mm
,
844 const struct mem_type
*type
,
847 unsigned long addr
, length
, end
;
852 phys
= __pfn_to_phys(md
->pfn
);
853 length
= PAGE_ALIGN(md
->length
);
855 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
856 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
857 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
861 /* N.B. ARMv6 supersections are only defined to work with domain 0.
862 * Since domain assignments can in fact be arbitrary, the
863 * 'domain == 0' check below is required to insure that ARMv6
864 * supersections are only allocated for domain 0 regardless
865 * of the actual domain assignments in use.
868 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
869 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
873 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
874 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
875 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
880 * Shift bits [35:32] of address into bits [23:20] of PMD
883 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
885 pgd
= pgd_offset(mm
, addr
);
888 pud_t
*pud
= pud_offset(pgd
, addr
);
889 pmd_t
*pmd
= pmd_offset(pud
, addr
);
892 for (i
= 0; i
< 16; i
++)
893 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
|
894 (ng
? PMD_SECT_nG
: 0));
896 addr
+= SUPERSECTION_SIZE
;
897 phys
+= SUPERSECTION_SIZE
;
898 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
899 } while (addr
!= end
);
901 #endif /* !CONFIG_ARM_LPAE */
903 static void __init
__create_mapping(struct mm_struct
*mm
, struct map_desc
*md
,
904 void *(*alloc
)(unsigned long sz
),
907 unsigned long addr
, length
, end
;
909 const struct mem_type
*type
;
912 type
= &mem_types
[md
->type
];
914 #ifndef CONFIG_ARM_LPAE
916 * Catch 36-bit addresses
918 if (md
->pfn
>= 0x100000) {
919 create_36bit_mapping(mm
, md
, type
, ng
);
924 addr
= md
->virtual & PAGE_MASK
;
925 phys
= __pfn_to_phys(md
->pfn
);
926 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
928 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
929 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
930 (long long)__pfn_to_phys(md
->pfn
), addr
);
934 pgd
= pgd_offset(mm
, addr
);
937 unsigned long next
= pgd_addr_end(addr
, end
);
939 alloc_init_pud(pgd
, addr
, next
, phys
, type
, alloc
, ng
);
943 } while (pgd
++, addr
!= end
);
947 * Create the page directory entries and any necessary
948 * page tables for the mapping specified by `md'. We
949 * are able to cope here with varying sizes and address
950 * offsets, and we take full advantage of sections and
953 static void __init
create_mapping(struct map_desc
*md
)
955 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
956 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
957 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
961 if ((md
->type
== MT_DEVICE
|| md
->type
== MT_ROM
) &&
962 md
->virtual >= PAGE_OFFSET
&& md
->virtual < FIXADDR_START
&&
963 (md
->virtual < VMALLOC_START
|| md
->virtual >= VMALLOC_END
)) {
964 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
965 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
968 __create_mapping(&init_mm
, md
, early_alloc
, false);
971 void __init
create_mapping_late(struct mm_struct
*mm
, struct map_desc
*md
,
974 #ifdef CONFIG_ARM_LPAE
975 pud_t
*pud
= pud_alloc(mm
, pgd_offset(mm
, md
->virtual), md
->virtual);
978 pmd_alloc(mm
, pud
, 0);
980 __create_mapping(mm
, md
, late_alloc
, ng
);
984 * Create the architecture specific mappings
986 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
989 struct vm_struct
*vm
;
990 struct static_vm
*svm
;
995 svm
= early_alloc_aligned(sizeof(*svm
) * nr
, __alignof__(*svm
));
997 for (md
= io_desc
; nr
; md
++, nr
--) {
1001 vm
->addr
= (void *)(md
->virtual & PAGE_MASK
);
1002 vm
->size
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
1003 vm
->phys_addr
= __pfn_to_phys(md
->pfn
);
1004 vm
->flags
= VM_IOREMAP
| VM_ARM_STATIC_MAPPING
;
1005 vm
->flags
|= VM_ARM_MTYPE(md
->type
);
1006 vm
->caller
= iotable_init
;
1007 add_static_vm_early(svm
++);
1011 void __init
vm_reserve_area_early(unsigned long addr
, unsigned long size
,
1014 struct vm_struct
*vm
;
1015 struct static_vm
*svm
;
1017 svm
= early_alloc_aligned(sizeof(*svm
), __alignof__(*svm
));
1020 vm
->addr
= (void *)addr
;
1022 vm
->flags
= VM_IOREMAP
| VM_ARM_EMPTY_MAPPING
;
1023 vm
->caller
= caller
;
1024 add_static_vm_early(svm
);
1027 #ifndef CONFIG_ARM_LPAE
1030 * The Linux PMD is made of two consecutive section entries covering 2MB
1031 * (see definition in include/asm/pgtable-2level.h). However a call to
1032 * create_mapping() may optimize static mappings by using individual
1033 * 1MB section mappings. This leaves the actual PMD potentially half
1034 * initialized if the top or bottom section entry isn't used, leaving it
1035 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1036 * the virtual space left free by that unused section entry.
1038 * Let's avoid the issue by inserting dummy vm entries covering the unused
1039 * PMD halves once the static mappings are in place.
1042 static void __init
pmd_empty_section_gap(unsigned long addr
)
1044 vm_reserve_area_early(addr
, SECTION_SIZE
, pmd_empty_section_gap
);
1047 static void __init
fill_pmd_gaps(void)
1049 struct static_vm
*svm
;
1050 struct vm_struct
*vm
;
1051 unsigned long addr
, next
= 0;
1054 list_for_each_entry(svm
, &static_vmlist
, list
) {
1056 addr
= (unsigned long)vm
->addr
;
1061 * Check if this vm starts on an odd section boundary.
1062 * If so and the first section entry for this PMD is free
1063 * then we block the corresponding virtual address.
1065 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
1066 pmd
= pmd_off_k(addr
);
1068 pmd_empty_section_gap(addr
& PMD_MASK
);
1072 * Then check if this vm ends on an odd section boundary.
1073 * If so and the second section entry for this PMD is empty
1074 * then we block the corresponding virtual address.
1077 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
1078 pmd
= pmd_off_k(addr
) + 1;
1080 pmd_empty_section_gap(addr
);
1083 /* no need to look at any vm entry until we hit the next PMD */
1084 next
= (addr
+ PMD_SIZE
- 1) & PMD_MASK
;
1089 #define fill_pmd_gaps() do { } while (0)
1092 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1093 static void __init
pci_reserve_io(void)
1095 struct static_vm
*svm
;
1097 svm
= find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE
);
1101 vm_reserve_area_early(PCI_IO_VIRT_BASE
, SZ_2M
, pci_reserve_io
);
1104 #define pci_reserve_io() do { } while (0)
1107 #ifdef CONFIG_DEBUG_LL
1108 void __init
debug_ll_io_init(void)
1110 struct map_desc map
;
1112 debug_ll_addr(&map
.pfn
, &map
.virtual);
1113 if (!map
.pfn
|| !map
.virtual)
1115 map
.pfn
= __phys_to_pfn(map
.pfn
);
1116 map
.virtual &= PAGE_MASK
;
1117 map
.length
= PAGE_SIZE
;
1118 map
.type
= MT_DEVICE
;
1119 iotable_init(&map
, 1);
1123 static void * __initdata vmalloc_min
=
1124 (void *)(VMALLOC_END
- (240 << 20) - VMALLOC_OFFSET
);
1127 * vmalloc=size forces the vmalloc area to be exactly 'size'
1128 * bytes. This can be used to increase (or decrease) the vmalloc
1129 * area - the default is 240m.
1131 static int __init
early_vmalloc(char *arg
)
1133 unsigned long vmalloc_reserve
= memparse(arg
, NULL
);
1135 if (vmalloc_reserve
< SZ_16M
) {
1136 vmalloc_reserve
= SZ_16M
;
1137 pr_warn("vmalloc area too small, limiting to %luMB\n",
1138 vmalloc_reserve
>> 20);
1141 if (vmalloc_reserve
> VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
)) {
1142 vmalloc_reserve
= VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
);
1143 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1144 vmalloc_reserve
>> 20);
1147 vmalloc_min
= (void *)(VMALLOC_END
- vmalloc_reserve
);
1150 early_param("vmalloc", early_vmalloc
);
1152 phys_addr_t arm_lowmem_limit __initdata
= 0;
1154 void __init
sanity_check_meminfo(void)
1156 phys_addr_t memblock_limit
= 0;
1158 phys_addr_t vmalloc_limit
= __pa(vmalloc_min
- 1) + 1;
1159 struct memblock_region
*reg
;
1160 bool should_use_highmem
= false;
1162 for_each_memblock(memory
, reg
) {
1163 phys_addr_t block_start
= reg
->base
;
1164 phys_addr_t block_end
= reg
->base
+ reg
->size
;
1165 phys_addr_t size_limit
= reg
->size
;
1167 if (reg
->base
>= vmalloc_limit
)
1170 size_limit
= vmalloc_limit
- reg
->base
;
1173 if (!IS_ENABLED(CONFIG_HIGHMEM
) || cache_is_vipt_aliasing()) {
1176 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1177 &block_start
, &block_end
);
1178 memblock_remove(reg
->base
, reg
->size
);
1179 should_use_highmem
= true;
1183 if (reg
->size
> size_limit
) {
1184 phys_addr_t overlap_size
= reg
->size
- size_limit
;
1186 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1187 &block_start
, &block_end
, &vmalloc_limit
);
1188 memblock_remove(vmalloc_limit
, overlap_size
);
1189 block_end
= vmalloc_limit
;
1190 should_use_highmem
= true;
1195 if (block_end
> arm_lowmem_limit
) {
1196 if (reg
->size
> size_limit
)
1197 arm_lowmem_limit
= vmalloc_limit
;
1199 arm_lowmem_limit
= block_end
;
1203 * Find the first non-pmd-aligned page, and point
1204 * memblock_limit at it. This relies on rounding the
1205 * limit down to be pmd-aligned, which happens at the
1206 * end of this function.
1208 * With this algorithm, the start or end of almost any
1209 * bank can be non-pmd-aligned. The only exception is
1210 * that the start of the bank 0 must be section-
1211 * aligned, since otherwise memory would need to be
1212 * allocated when mapping the start of bank 0, which
1213 * occurs before any free memory is mapped.
1215 if (!memblock_limit
) {
1216 if (!IS_ALIGNED(block_start
, PMD_SIZE
))
1217 memblock_limit
= block_start
;
1218 else if (!IS_ALIGNED(block_end
, PMD_SIZE
))
1219 memblock_limit
= arm_lowmem_limit
;
1225 if (should_use_highmem
)
1226 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1228 high_memory
= __va(arm_lowmem_limit
- 1) + 1;
1231 * Round the memblock limit down to a pmd size. This
1232 * helps to ensure that we will allocate memory from the
1233 * last full pmd, which should be mapped.
1236 memblock_limit
= round_down(memblock_limit
, PMD_SIZE
);
1237 if (!memblock_limit
)
1238 memblock_limit
= arm_lowmem_limit
;
1240 memblock_set_current_limit(memblock_limit
);
1243 static inline void prepare_page_table(void)
1249 * Clear out all the mappings below the kernel image.
1251 for (addr
= 0; addr
< MODULES_VADDR
; addr
+= PMD_SIZE
)
1252 pmd_clear(pmd_off_k(addr
));
1254 #ifdef CONFIG_XIP_KERNEL
1255 /* The XIP kernel is mapped in the module area -- skip over it */
1256 addr
= ((unsigned long)_exiprom
+ PMD_SIZE
- 1) & PMD_MASK
;
1258 for ( ; addr
< PAGE_OFFSET
; addr
+= PMD_SIZE
)
1259 pmd_clear(pmd_off_k(addr
));
1262 * Find the end of the first block of lowmem.
1264 end
= memblock
.memory
.regions
[0].base
+ memblock
.memory
.regions
[0].size
;
1265 if (end
>= arm_lowmem_limit
)
1266 end
= arm_lowmem_limit
;
1269 * Clear out all the kernel space mappings, except for the first
1270 * memory bank, up to the vmalloc region.
1272 for (addr
= __phys_to_virt(end
);
1273 addr
< VMALLOC_START
; addr
+= PMD_SIZE
)
1274 pmd_clear(pmd_off_k(addr
));
1277 #ifdef CONFIG_ARM_LPAE
1278 /* the first page is reserved for pgd */
1279 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1280 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1282 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1286 * Reserve the special regions of memory
1288 void __init
arm_mm_memblock_reserve(void)
1291 * Reserve the page tables. These are already in use,
1292 * and can only be in node 0.
1294 memblock_reserve(__pa(swapper_pg_dir
), SWAPPER_PG_DIR_SIZE
);
1296 #ifdef CONFIG_SA1111
1298 * Because of the SA1111 DMA bug, we want to preserve our
1299 * precious DMA-able memory...
1301 memblock_reserve(PHYS_OFFSET
, __pa(swapper_pg_dir
) - PHYS_OFFSET
);
1306 * Set up the device mappings. Since we clear out the page tables for all
1307 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1308 * device mappings. This means earlycon can be used to debug this function
1309 * Any other function or debugging method which may touch any device _will_
1312 static void __init
devicemaps_init(const struct machine_desc
*mdesc
)
1314 struct map_desc map
;
1319 * Allocate the vector page early.
1321 vectors
= early_alloc(PAGE_SIZE
* 2);
1323 early_trap_init(vectors
);
1326 * Clear page table except top pmd used by early fixmaps
1328 for (addr
= VMALLOC_START
; addr
< (FIXADDR_TOP
& PMD_MASK
); addr
+= PMD_SIZE
)
1329 pmd_clear(pmd_off_k(addr
));
1332 * Map the kernel if it is XIP.
1333 * It is always first in the modulearea.
1335 #ifdef CONFIG_XIP_KERNEL
1336 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
1337 map
.virtual = MODULES_VADDR
;
1338 map
.length
= ((unsigned long)_exiprom
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
1340 create_mapping(&map
);
1344 * Map the cache flushing regions.
1347 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
1348 map
.virtual = FLUSH_BASE
;
1350 map
.type
= MT_CACHECLEAN
;
1351 create_mapping(&map
);
1353 #ifdef FLUSH_BASE_MINICACHE
1354 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
1355 map
.virtual = FLUSH_BASE_MINICACHE
;
1357 map
.type
= MT_MINICLEAN
;
1358 create_mapping(&map
);
1362 * Create a mapping for the machine vectors at the high-vectors
1363 * location (0xffff0000). If we aren't using high-vectors, also
1364 * create a mapping at the low-vectors virtual address.
1366 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
1367 map
.virtual = 0xffff0000;
1368 map
.length
= PAGE_SIZE
;
1369 #ifdef CONFIG_KUSER_HELPERS
1370 map
.type
= MT_HIGH_VECTORS
;
1372 map
.type
= MT_LOW_VECTORS
;
1374 create_mapping(&map
);
1376 if (!vectors_high()) {
1378 map
.length
= PAGE_SIZE
* 2;
1379 map
.type
= MT_LOW_VECTORS
;
1380 create_mapping(&map
);
1383 /* Now create a kernel read-only mapping */
1385 map
.virtual = 0xffff0000 + PAGE_SIZE
;
1386 map
.length
= PAGE_SIZE
;
1387 map
.type
= MT_LOW_VECTORS
;
1388 create_mapping(&map
);
1391 * Ask the machine support to map in the statically mapped devices.
1399 /* Reserve fixed i/o space in VMALLOC region */
1403 * Finally flush the caches and tlb to ensure that we're in a
1404 * consistent state wrt the writebuffer. This also ensures that
1405 * any write-allocated cache lines in the vector page are written
1406 * back. After this point, we can start to touch devices again.
1408 local_flush_tlb_all();
1411 /* Enable asynchronous aborts */
1415 static void __init
kmap_init(void)
1417 #ifdef CONFIG_HIGHMEM
1418 pkmap_page_table
= early_pte_alloc(pmd_off_k(PKMAP_BASE
),
1419 PKMAP_BASE
, _PAGE_KERNEL_TABLE
);
1422 early_pte_alloc(pmd_off_k(FIXADDR_START
), FIXADDR_START
,
1423 _PAGE_KERNEL_TABLE
);
1426 static void __init
map_lowmem(void)
1428 struct memblock_region
*reg
;
1429 #ifdef CONFIG_XIP_KERNEL
1430 phys_addr_t kernel_x_start
= round_down(__pa(_sdata
), SECTION_SIZE
);
1432 phys_addr_t kernel_x_start
= round_down(__pa(_stext
), SECTION_SIZE
);
1434 phys_addr_t kernel_x_end
= round_up(__pa(__init_end
), SECTION_SIZE
);
1436 /* Map all the lowmem memory banks. */
1437 for_each_memblock(memory
, reg
) {
1438 phys_addr_t start
= reg
->base
;
1439 phys_addr_t end
= start
+ reg
->size
;
1440 struct map_desc map
;
1442 if (memblock_is_nomap(reg
))
1445 if (end
> arm_lowmem_limit
)
1446 end
= arm_lowmem_limit
;
1450 if (end
< kernel_x_start
) {
1451 map
.pfn
= __phys_to_pfn(start
);
1452 map
.virtual = __phys_to_virt(start
);
1453 map
.length
= end
- start
;
1454 map
.type
= MT_MEMORY_RWX
;
1456 create_mapping(&map
);
1457 } else if (start
>= kernel_x_end
) {
1458 map
.pfn
= __phys_to_pfn(start
);
1459 map
.virtual = __phys_to_virt(start
);
1460 map
.length
= end
- start
;
1461 map
.type
= MT_MEMORY_RW
;
1463 create_mapping(&map
);
1465 /* This better cover the entire kernel */
1466 if (start
< kernel_x_start
) {
1467 map
.pfn
= __phys_to_pfn(start
);
1468 map
.virtual = __phys_to_virt(start
);
1469 map
.length
= kernel_x_start
- start
;
1470 map
.type
= MT_MEMORY_RW
;
1472 create_mapping(&map
);
1475 map
.pfn
= __phys_to_pfn(kernel_x_start
);
1476 map
.virtual = __phys_to_virt(kernel_x_start
);
1477 map
.length
= kernel_x_end
- kernel_x_start
;
1478 map
.type
= MT_MEMORY_RWX
;
1480 create_mapping(&map
);
1482 if (kernel_x_end
< end
) {
1483 map
.pfn
= __phys_to_pfn(kernel_x_end
);
1484 map
.virtual = __phys_to_virt(kernel_x_end
);
1485 map
.length
= end
- kernel_x_end
;
1486 map
.type
= MT_MEMORY_RW
;
1488 create_mapping(&map
);
1494 #ifdef CONFIG_ARM_PV_FIXUP
1495 extern unsigned long __atags_pointer
;
1496 typedef void pgtables_remap(long long offset
, unsigned long pgd
, void *bdata
);
1497 pgtables_remap lpae_pgtables_remap_asm
;
1500 * early_paging_init() recreates boot time page table setup, allowing machines
1501 * to switch over to a high (>4G) address space on LPAE systems
1503 void __init
early_paging_init(const struct machine_desc
*mdesc
)
1505 pgtables_remap
*lpae_pgtables_remap
;
1506 unsigned long pa_pgd
;
1507 unsigned int cr
, ttbcr
;
1511 if (!mdesc
->pv_fixup
)
1514 offset
= mdesc
->pv_fixup();
1519 * Get the address of the remap function in the 1:1 identity
1520 * mapping setup by the early page table assembly code. We
1521 * must get this prior to the pv update. The following barrier
1522 * ensures that this is complete before we fixup any P:V offsets.
1524 lpae_pgtables_remap
= (pgtables_remap
*)(unsigned long)__pa(lpae_pgtables_remap_asm
);
1525 pa_pgd
= __pa(swapper_pg_dir
);
1526 boot_data
= __va(__atags_pointer
);
1529 pr_info("Switching physical address space to 0x%08llx\n",
1530 (u64
)PHYS_OFFSET
+ offset
);
1532 /* Re-set the phys pfn offset, and the pv offset */
1533 __pv_offset
+= offset
;
1534 __pv_phys_pfn_offset
+= PFN_DOWN(offset
);
1536 /* Run the patch stub to update the constants */
1537 fixup_pv_table(&__pv_table_begin
,
1538 (&__pv_table_end
- &__pv_table_begin
) << 2);
1541 * We changing not only the virtual to physical mapping, but also
1542 * the physical addresses used to access memory. We need to flush
1543 * all levels of cache in the system with caching disabled to
1544 * ensure that all data is written back, and nothing is prefetched
1545 * into the caches. We also need to prevent the TLB walkers
1546 * allocating into the caches too. Note that this is ARMv7 LPAE
1550 set_cr(cr
& ~(CR_I
| CR_C
));
1551 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr
));
1552 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1553 : : "r" (ttbcr
& ~(3 << 8 | 3 << 10)));
1557 * Fixup the page tables - this must be in the idmap region as
1558 * we need to disable the MMU to do this safely, and hence it
1559 * needs to be assembly. It's fairly simple, as we're using the
1560 * temporary tables setup by the initial assembly code.
1562 lpae_pgtables_remap(offset
, pa_pgd
, boot_data
);
1564 /* Re-enable the caches and cacheable TLB walks */
1565 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr
));
1571 void __init
early_paging_init(const struct machine_desc
*mdesc
)
1575 if (!mdesc
->pv_fixup
)
1578 offset
= mdesc
->pv_fixup();
1582 pr_crit("Physical address space modification is only to support Keystone2.\n");
1583 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1584 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1585 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
1590 static void __init
early_fixmap_shutdown(void)
1593 unsigned long va
= fix_to_virt(__end_of_permanent_fixed_addresses
- 1);
1595 pte_offset_fixmap
= pte_offset_late_fixmap
;
1596 pmd_clear(fixmap_pmd(va
));
1597 local_flush_tlb_kernel_page(va
);
1599 for (i
= 0; i
< __end_of_permanent_fixed_addresses
; i
++) {
1601 struct map_desc map
;
1603 map
.virtual = fix_to_virt(i
);
1604 pte
= pte_offset_early_fixmap(pmd_off_k(map
.virtual), map
.virtual);
1606 /* Only i/o device mappings are supported ATM */
1607 if (pte_none(*pte
) ||
1608 (pte_val(*pte
) & L_PTE_MT_MASK
) != L_PTE_MT_DEV_SHARED
)
1611 map
.pfn
= pte_pfn(*pte
);
1612 map
.type
= MT_DEVICE
;
1613 map
.length
= PAGE_SIZE
;
1615 create_mapping(&map
);
1620 * paging_init() sets up the page tables, initialises the zone memory
1621 * maps, and sets up the zero page, bad page and bad page tables.
1623 void __init
paging_init(const struct machine_desc
*mdesc
)
1627 build_mem_type_table();
1628 prepare_page_table();
1630 memblock_set_current_limit(arm_lowmem_limit
);
1631 dma_contiguous_remap();
1632 early_fixmap_shutdown();
1633 devicemaps_init(mdesc
);
1637 top_pmd
= pmd_off_k(0xffff0000);
1639 /* allocate the zero page. */
1640 zero_page
= early_alloc(PAGE_SIZE
);
1644 empty_zero_page
= virt_to_page(zero_page
);
1645 __flush_dcache_page(NULL
, empty_zero_page
);