2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sizes.h>
22 #include <asm/cputype.h>
23 #include <asm/sections.h>
24 #include <asm/cachetype.h>
25 #include <asm/setup.h>
26 #include <asm/smp_plat.h>
28 #include <asm/highmem.h>
29 #include <asm/system_info.h>
30 #include <asm/traps.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
38 * empty_zero_page is a special page that is used for
39 * zero-initialized data and COW.
41 struct page
*empty_zero_page
;
42 EXPORT_SYMBOL(empty_zero_page
);
45 * The pmd table for the upper-most set of pages.
49 #define CPOLICY_UNCACHED 0
50 #define CPOLICY_BUFFERED 1
51 #define CPOLICY_WRITETHROUGH 2
52 #define CPOLICY_WRITEBACK 3
53 #define CPOLICY_WRITEALLOC 4
55 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
56 static unsigned int ecc_mask __initdata
= 0;
58 pgprot_t pgprot_kernel
;
60 EXPORT_SYMBOL(pgprot_user
);
61 EXPORT_SYMBOL(pgprot_kernel
);
64 const char policy
[16];
70 static struct cachepolicy cache_policies
[] __initdata
= {
74 .pmd
= PMD_SECT_UNCACHED
,
75 .pte
= L_PTE_MT_UNCACHED
,
79 .pmd
= PMD_SECT_BUFFERED
,
80 .pte
= L_PTE_MT_BUFFERABLE
,
82 .policy
= "writethrough",
85 .pte
= L_PTE_MT_WRITETHROUGH
,
87 .policy
= "writeback",
90 .pte
= L_PTE_MT_WRITEBACK
,
92 .policy
= "writealloc",
95 .pte
= L_PTE_MT_WRITEALLOC
,
100 * These are useful for identifying cache coherency
101 * problems by allowing the cache or the cache and
102 * writebuffer to be turned off. (Note: the write
103 * buffer should not be on and the cache off).
105 static int __init
early_cachepolicy(char *p
)
109 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
110 int len
= strlen(cache_policies
[i
].policy
);
112 if (memcmp(p
, cache_policies
[i
].policy
, len
) == 0) {
114 cr_alignment
&= ~cache_policies
[i
].cr_mask
;
115 cr_no_alignment
&= ~cache_policies
[i
].cr_mask
;
119 if (i
== ARRAY_SIZE(cache_policies
))
120 printk(KERN_ERR
"ERROR: unknown or unsupported cache policy\n");
122 * This restriction is partly to do with the way we boot; it is
123 * unpredictable to have memory mapped using two different sets of
124 * memory attributes (shared, type, and cache attribs). We can not
125 * change these attributes once the initial assembly has setup the
128 if (cpu_architecture() >= CPU_ARCH_ARMv6
) {
129 printk(KERN_WARNING
"Only cachepolicy=writeback supported on ARMv6 and later\n");
130 cachepolicy
= CPOLICY_WRITEBACK
;
133 set_cr(cr_alignment
);
136 early_param("cachepolicy", early_cachepolicy
);
138 static int __init
early_nocache(char *__unused
)
140 char *p
= "buffered";
141 printk(KERN_WARNING
"nocache is deprecated; use cachepolicy=%s\n", p
);
142 early_cachepolicy(p
);
145 early_param("nocache", early_nocache
);
147 static int __init
early_nowrite(char *__unused
)
149 char *p
= "uncached";
150 printk(KERN_WARNING
"nowb is deprecated; use cachepolicy=%s\n", p
);
151 early_cachepolicy(p
);
154 early_param("nowb", early_nowrite
);
156 #ifndef CONFIG_ARM_LPAE
157 static int __init
early_ecc(char *p
)
159 if (memcmp(p
, "on", 2) == 0)
160 ecc_mask
= PMD_PROTECTION
;
161 else if (memcmp(p
, "off", 3) == 0)
165 early_param("ecc", early_ecc
);
168 static int __init
noalign_setup(char *__unused
)
170 cr_alignment
&= ~CR_A
;
171 cr_no_alignment
&= ~CR_A
;
172 set_cr(cr_alignment
);
175 __setup("noalign", noalign_setup
);
178 void adjust_cr(unsigned long mask
, unsigned long set
)
186 local_irq_save(flags
);
188 cr_no_alignment
= (cr_no_alignment
& ~mask
) | set
;
189 cr_alignment
= (cr_alignment
& ~mask
) | set
;
191 set_cr((get_cr() & ~mask
) | set
);
193 local_irq_restore(flags
);
197 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
198 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
200 static struct mem_type mem_types
[] = {
201 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
202 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_SHARED
|
204 .prot_l1
= PMD_TYPE_TABLE
,
205 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_S
,
208 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
209 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_NONSHARED
,
210 .prot_l1
= PMD_TYPE_TABLE
,
211 .prot_sect
= PROT_SECT_DEVICE
,
214 [MT_DEVICE_CACHED
] = { /* ioremap_cached */
215 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_CACHED
,
216 .prot_l1
= PMD_TYPE_TABLE
,
217 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
220 [MT_DEVICE_WC
] = { /* ioremap_wc */
221 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_WC
,
222 .prot_l1
= PMD_TYPE_TABLE
,
223 .prot_sect
= PROT_SECT_DEVICE
,
227 .prot_pte
= PROT_PTE_DEVICE
,
228 .prot_l1
= PMD_TYPE_TABLE
,
229 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
233 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
234 .domain
= DOMAIN_KERNEL
,
236 #ifndef CONFIG_ARM_LPAE
238 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
239 .domain
= DOMAIN_KERNEL
,
243 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
245 .prot_l1
= PMD_TYPE_TABLE
,
246 .domain
= DOMAIN_USER
,
248 [MT_HIGH_VECTORS
] = {
249 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
250 L_PTE_USER
| L_PTE_RDONLY
,
251 .prot_l1
= PMD_TYPE_TABLE
,
252 .domain
= DOMAIN_USER
,
255 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
256 .prot_l1
= PMD_TYPE_TABLE
,
257 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
258 .domain
= DOMAIN_KERNEL
,
261 .prot_sect
= PMD_TYPE_SECT
,
262 .domain
= DOMAIN_KERNEL
,
264 [MT_MEMORY_NONCACHED
] = {
265 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
267 .prot_l1
= PMD_TYPE_TABLE
,
268 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
269 .domain
= DOMAIN_KERNEL
,
272 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
274 .prot_l1
= PMD_TYPE_TABLE
,
275 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
276 .domain
= DOMAIN_KERNEL
,
279 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
280 .prot_l1
= PMD_TYPE_TABLE
,
281 .domain
= DOMAIN_KERNEL
,
284 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
286 .prot_l1
= PMD_TYPE_TABLE
,
287 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
| PMD_SECT_S
|
288 PMD_SECT_UNCACHED
| PMD_SECT_XN
,
289 .domain
= DOMAIN_KERNEL
,
291 [MT_MEMORY_DMA_READY
] = {
292 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
,
293 .prot_l1
= PMD_TYPE_TABLE
,
294 .domain
= DOMAIN_KERNEL
,
298 const struct mem_type
*get_mem_type(unsigned int type
)
300 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
302 EXPORT_SYMBOL(get_mem_type
);
305 * Adjust the PMD section entries according to the CPU in use.
307 static void __init
build_mem_type_table(void)
309 struct cachepolicy
*cp
;
310 unsigned int cr
= get_cr();
311 pteval_t user_pgprot
, kern_pgprot
, vecs_pgprot
;
312 int cpu_arch
= cpu_architecture();
315 if (cpu_arch
< CPU_ARCH_ARMv6
) {
316 #if defined(CONFIG_CPU_DCACHE_DISABLE)
317 if (cachepolicy
> CPOLICY_BUFFERED
)
318 cachepolicy
= CPOLICY_BUFFERED
;
319 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
320 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
321 cachepolicy
= CPOLICY_WRITETHROUGH
;
324 if (cpu_arch
< CPU_ARCH_ARMv5
) {
325 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
326 cachepolicy
= CPOLICY_WRITEBACK
;
330 cachepolicy
= CPOLICY_WRITEALLOC
;
333 * Strip out features not present on earlier architectures.
334 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
335 * without extended page tables don't have the 'Shared' bit.
337 if (cpu_arch
< CPU_ARCH_ARMv5
)
338 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
339 mem_types
[i
].prot_sect
&= ~PMD_SECT_TEX(7);
340 if ((cpu_arch
< CPU_ARCH_ARMv6
|| !(cr
& CR_XP
)) && !cpu_is_xsc3())
341 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
342 mem_types
[i
].prot_sect
&= ~PMD_SECT_S
;
345 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
346 * "update-able on write" bit on ARM610). However, Xscale and
347 * Xscale3 require this bit to be cleared.
349 if (cpu_is_xscale() || cpu_is_xsc3()) {
350 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
351 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
352 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
354 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
355 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
356 if (mem_types
[i
].prot_l1
)
357 mem_types
[i
].prot_l1
|= PMD_BIT4
;
358 if (mem_types
[i
].prot_sect
)
359 mem_types
[i
].prot_sect
|= PMD_BIT4
;
364 * Mark the device areas according to the CPU/architecture.
366 if (cpu_is_xsc3() || (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
))) {
367 if (!cpu_is_xsc3()) {
369 * Mark device regions on ARMv6+ as execute-never
370 * to prevent speculative instruction fetches.
372 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_XN
;
373 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_XN
;
374 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_XN
;
375 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_XN
;
377 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
379 * For ARMv7 with TEX remapping,
380 * - shared device is SXCB=1100
381 * - nonshared device is SXCB=0100
382 * - write combine device mem is SXCB=0001
383 * (Uncached Normal memory)
385 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1);
386 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(1);
387 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
388 } else if (cpu_is_xsc3()) {
391 * - shared device is TEXCB=00101
392 * - nonshared device is TEXCB=01000
393 * - write combine device mem is TEXCB=00100
394 * (Inner/Outer Uncacheable in xsc3 parlance)
396 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED
;
397 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
398 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
401 * For ARMv6 and ARMv7 without TEX remapping,
402 * - shared device is TEXCB=00001
403 * - nonshared device is TEXCB=01000
404 * - write combine device mem is TEXCB=00100
405 * (Uncached Normal in ARMv6 parlance).
407 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
408 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
409 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
413 * On others, write combining is "Uncached/Buffered"
415 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
419 * Now deal with the memory-type mappings
421 cp
= &cache_policies
[cachepolicy
];
422 vecs_pgprot
= kern_pgprot
= user_pgprot
= cp
->pte
;
425 * Enable CPU-specific coherency if supported.
426 * (Only available on XSC3 at the moment.)
428 if (arch_is_coherent() && cpu_is_xsc3()) {
429 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
430 mem_types
[MT_MEMORY
].prot_pte
|= L_PTE_SHARED
;
431 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= L_PTE_SHARED
;
432 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= PMD_SECT_S
;
433 mem_types
[MT_MEMORY_NONCACHED
].prot_pte
|= L_PTE_SHARED
;
436 * ARMv6 and above have extended page tables.
438 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
439 #ifndef CONFIG_ARM_LPAE
441 * Mark cache clean areas and XIP ROM read only
442 * from SVC mode and no access from userspace.
444 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
445 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
446 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
451 * Mark memory with the "shared" attribute
454 user_pgprot
|= L_PTE_SHARED
;
455 kern_pgprot
|= L_PTE_SHARED
;
456 vecs_pgprot
|= L_PTE_SHARED
;
457 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_S
;
458 mem_types
[MT_DEVICE_WC
].prot_pte
|= L_PTE_SHARED
;
459 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_S
;
460 mem_types
[MT_DEVICE_CACHED
].prot_pte
|= L_PTE_SHARED
;
461 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
462 mem_types
[MT_MEMORY
].prot_pte
|= L_PTE_SHARED
;
463 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= L_PTE_SHARED
;
464 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= PMD_SECT_S
;
465 mem_types
[MT_MEMORY_NONCACHED
].prot_pte
|= L_PTE_SHARED
;
470 * Non-cacheable Normal - intended for memory areas that must
471 * not cause dirty cache line writebacks when used
473 if (cpu_arch
>= CPU_ARCH_ARMv6
) {
474 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
475 /* Non-cacheable Normal is XCB = 001 */
476 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|=
479 /* For both ARMv6 and non-TEX-remapping ARMv7 */
480 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|=
484 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= PMD_SECT_BUFFERABLE
;
487 #ifdef CONFIG_ARM_LPAE
489 * Do not generate access flag faults for the kernel mappings.
491 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
492 mem_types
[i
].prot_pte
|= PTE_EXT_AF
;
493 if (mem_types
[i
].prot_sect
)
494 mem_types
[i
].prot_sect
|= PMD_SECT_AF
;
496 kern_pgprot
|= PTE_EXT_AF
;
497 vecs_pgprot
|= PTE_EXT_AF
;
500 for (i
= 0; i
< 16; i
++) {
501 unsigned long v
= pgprot_val(protection_map
[i
]);
502 protection_map
[i
] = __pgprot(v
| user_pgprot
);
505 mem_types
[MT_LOW_VECTORS
].prot_pte
|= vecs_pgprot
;
506 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= vecs_pgprot
;
508 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
509 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
510 L_PTE_DIRTY
| kern_pgprot
);
512 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
513 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
514 mem_types
[MT_MEMORY
].prot_sect
|= ecc_mask
| cp
->pmd
;
515 mem_types
[MT_MEMORY
].prot_pte
|= kern_pgprot
;
516 mem_types
[MT_MEMORY_DMA_READY
].prot_pte
|= kern_pgprot
;
517 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= ecc_mask
;
518 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
522 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
526 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
529 printk("Memory policy: ECC %sabled, Data cache %s\n",
530 ecc_mask
? "en" : "dis", cp
->policy
);
532 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
533 struct mem_type
*t
= &mem_types
[i
];
535 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
537 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
541 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
542 pgprot_t
phys_mem_access_prot(struct file
*file
, unsigned long pfn
,
543 unsigned long size
, pgprot_t vma_prot
)
546 return pgprot_noncached(vma_prot
);
547 else if (file
->f_flags
& O_SYNC
)
548 return pgprot_writecombine(vma_prot
);
551 EXPORT_SYMBOL(phys_mem_access_prot
);
554 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
556 static void __init
*early_alloc_aligned(unsigned long sz
, unsigned long align
)
558 void *ptr
= __va(memblock_alloc(sz
, align
));
563 static void __init
*early_alloc(unsigned long sz
)
565 return early_alloc_aligned(sz
, sz
);
568 static pte_t
* __init
early_pte_alloc(pmd_t
*pmd
, unsigned long addr
, unsigned long prot
)
570 if (pmd_none(*pmd
)) {
571 pte_t
*pte
= early_alloc(PTE_HWTABLE_OFF
+ PTE_HWTABLE_SIZE
);
572 __pmd_populate(pmd
, __pa(pte
), prot
);
574 BUG_ON(pmd_bad(*pmd
));
575 return pte_offset_kernel(pmd
, addr
);
578 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
579 unsigned long end
, unsigned long pfn
,
580 const struct mem_type
*type
)
582 pte_t
*pte
= early_pte_alloc(pmd
, addr
, type
->prot_l1
);
584 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)), 0);
586 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
589 static void __init
alloc_init_section(pud_t
*pud
, unsigned long addr
,
590 unsigned long end
, phys_addr_t phys
,
591 const struct mem_type
*type
)
593 pmd_t
*pmd
= pmd_offset(pud
, addr
);
596 * Try a section mapping - end, addr and phys must all be aligned
597 * to a section boundary. Note that PMDs refer to the individual
598 * L1 entries, whereas PGDs refer to a group of L1 entries making
599 * up one logical pointer to an L2 table.
601 if (type
->prot_sect
&& ((addr
| end
| phys
) & ~SECTION_MASK
) == 0) {
604 #ifndef CONFIG_ARM_LPAE
605 if (addr
& SECTION_SIZE
)
610 *pmd
= __pmd(phys
| type
->prot_sect
);
611 phys
+= SECTION_SIZE
;
612 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
617 * No need to loop; pte's aren't interested in the
618 * individual L1 entries.
620 alloc_init_pte(pmd
, addr
, end
, __phys_to_pfn(phys
), type
);
624 static void __init
alloc_init_pud(pgd_t
*pgd
, unsigned long addr
,
625 unsigned long end
, unsigned long phys
, const struct mem_type
*type
)
627 pud_t
*pud
= pud_offset(pgd
, addr
);
631 next
= pud_addr_end(addr
, end
);
632 alloc_init_section(pud
, addr
, next
, phys
, type
);
634 } while (pud
++, addr
= next
, addr
!= end
);
637 #ifndef CONFIG_ARM_LPAE
638 static void __init
create_36bit_mapping(struct map_desc
*md
,
639 const struct mem_type
*type
)
641 unsigned long addr
, length
, end
;
646 phys
= __pfn_to_phys(md
->pfn
);
647 length
= PAGE_ALIGN(md
->length
);
649 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
650 printk(KERN_ERR
"MM: CPU does not support supersection "
651 "mapping for 0x%08llx at 0x%08lx\n",
652 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
656 /* N.B. ARMv6 supersections are only defined to work with domain 0.
657 * Since domain assignments can in fact be arbitrary, the
658 * 'domain == 0' check below is required to insure that ARMv6
659 * supersections are only allocated for domain 0 regardless
660 * of the actual domain assignments in use.
663 printk(KERN_ERR
"MM: invalid domain in supersection "
664 "mapping for 0x%08llx at 0x%08lx\n",
665 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
669 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
670 printk(KERN_ERR
"MM: cannot create mapping for 0x%08llx"
671 " at 0x%08lx invalid alignment\n",
672 (long long)__pfn_to_phys((u64
)md
->pfn
), addr
);
677 * Shift bits [35:32] of address into bits [23:20] of PMD
680 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
682 pgd
= pgd_offset_k(addr
);
685 pud_t
*pud
= pud_offset(pgd
, addr
);
686 pmd_t
*pmd
= pmd_offset(pud
, addr
);
689 for (i
= 0; i
< 16; i
++)
690 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
);
692 addr
+= SUPERSECTION_SIZE
;
693 phys
+= SUPERSECTION_SIZE
;
694 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
695 } while (addr
!= end
);
697 #endif /* !CONFIG_ARM_LPAE */
700 * Create the page directory entries and any necessary
701 * page tables for the mapping specified by `md'. We
702 * are able to cope here with varying sizes and address
703 * offsets, and we take full advantage of sections and
706 static void __init
create_mapping(struct map_desc
*md
)
708 unsigned long addr
, length
, end
;
710 const struct mem_type
*type
;
713 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
714 printk(KERN_WARNING
"BUG: not creating mapping for 0x%08llx"
715 " at 0x%08lx in user region\n",
716 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
720 if ((md
->type
== MT_DEVICE
|| md
->type
== MT_ROM
) &&
721 md
->virtual >= PAGE_OFFSET
&&
722 (md
->virtual < VMALLOC_START
|| md
->virtual >= VMALLOC_END
)) {
723 printk(KERN_WARNING
"BUG: mapping for 0x%08llx"
724 " at 0x%08lx out of vmalloc space\n",
725 (long long)__pfn_to_phys((u64
)md
->pfn
), md
->virtual);
728 type
= &mem_types
[md
->type
];
730 #ifndef CONFIG_ARM_LPAE
732 * Catch 36-bit addresses
734 if (md
->pfn
>= 0x100000) {
735 create_36bit_mapping(md
, type
);
740 addr
= md
->virtual & PAGE_MASK
;
741 phys
= __pfn_to_phys(md
->pfn
);
742 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
744 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
745 printk(KERN_WARNING
"BUG: map for 0x%08llx at 0x%08lx can not "
746 "be mapped using pages, ignoring.\n",
747 (long long)__pfn_to_phys(md
->pfn
), addr
);
751 pgd
= pgd_offset_k(addr
);
754 unsigned long next
= pgd_addr_end(addr
, end
);
756 alloc_init_pud(pgd
, addr
, next
, phys
, type
);
760 } while (pgd
++, addr
!= end
);
764 * Create the architecture specific mappings
766 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
769 struct vm_struct
*vm
;
774 vm
= early_alloc_aligned(sizeof(*vm
) * nr
, __alignof__(*vm
));
776 for (md
= io_desc
; nr
; md
++, nr
--) {
778 vm
->addr
= (void *)(md
->virtual & PAGE_MASK
);
779 vm
->size
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
780 vm
->phys_addr
= __pfn_to_phys(md
->pfn
);
781 vm
->flags
= VM_IOREMAP
| VM_ARM_STATIC_MAPPING
;
782 vm
->flags
|= VM_ARM_MTYPE(md
->type
);
783 vm
->caller
= iotable_init
;
784 vm_area_add_early(vm
++);
788 #ifndef CONFIG_ARM_LPAE
791 * The Linux PMD is made of two consecutive section entries covering 2MB
792 * (see definition in include/asm/pgtable-2level.h). However a call to
793 * create_mapping() may optimize static mappings by using individual
794 * 1MB section mappings. This leaves the actual PMD potentially half
795 * initialized if the top or bottom section entry isn't used, leaving it
796 * open to problems if a subsequent ioremap() or vmalloc() tries to use
797 * the virtual space left free by that unused section entry.
799 * Let's avoid the issue by inserting dummy vm entries covering the unused
800 * PMD halves once the static mappings are in place.
803 static void __init
pmd_empty_section_gap(unsigned long addr
)
805 struct vm_struct
*vm
;
807 vm
= early_alloc_aligned(sizeof(*vm
), __alignof__(*vm
));
808 vm
->addr
= (void *)addr
;
809 vm
->size
= SECTION_SIZE
;
810 vm
->flags
= VM_IOREMAP
| VM_ARM_EMPTY_MAPPING
;
811 vm
->caller
= pmd_empty_section_gap
;
812 vm_area_add_early(vm
);
815 static void __init
fill_pmd_gaps(void)
817 struct vm_struct
*vm
;
818 unsigned long addr
, next
= 0;
821 /* we're still single threaded hence no lock needed here */
822 for (vm
= vmlist
; vm
; vm
= vm
->next
) {
823 if (!(vm
->flags
& (VM_ARM_STATIC_MAPPING
| VM_ARM_EMPTY_MAPPING
)))
825 addr
= (unsigned long)vm
->addr
;
830 * Check if this vm starts on an odd section boundary.
831 * If so and the first section entry for this PMD is free
832 * then we block the corresponding virtual address.
834 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
835 pmd
= pmd_off_k(addr
);
837 pmd_empty_section_gap(addr
& PMD_MASK
);
841 * Then check if this vm ends on an odd section boundary.
842 * If so and the second section entry for this PMD is empty
843 * then we block the corresponding virtual address.
846 if ((addr
& ~PMD_MASK
) == SECTION_SIZE
) {
847 pmd
= pmd_off_k(addr
) + 1;
849 pmd_empty_section_gap(addr
);
852 /* no need to look at any vm entry until we hit the next PMD */
853 next
= (addr
+ PMD_SIZE
- 1) & PMD_MASK
;
858 #define fill_pmd_gaps() do { } while (0)
861 static void * __initdata vmalloc_min
=
862 (void *)(VMALLOC_END
- (240 << 20) - VMALLOC_OFFSET
);
865 * vmalloc=size forces the vmalloc area to be exactly 'size'
866 * bytes. This can be used to increase (or decrease) the vmalloc
867 * area - the default is 240m.
869 static int __init
early_vmalloc(char *arg
)
871 unsigned long vmalloc_reserve
= memparse(arg
, NULL
);
873 if (vmalloc_reserve
< SZ_16M
) {
874 vmalloc_reserve
= SZ_16M
;
876 "vmalloc area too small, limiting to %luMB\n",
877 vmalloc_reserve
>> 20);
880 if (vmalloc_reserve
> VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
)) {
881 vmalloc_reserve
= VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
);
883 "vmalloc area is too big, limiting to %luMB\n",
884 vmalloc_reserve
>> 20);
887 vmalloc_min
= (void *)(VMALLOC_END
- vmalloc_reserve
);
890 early_param("vmalloc", early_vmalloc
);
892 phys_addr_t arm_lowmem_limit __initdata
= 0;
894 void __init
sanity_check_meminfo(void)
896 int i
, j
, highmem
= 0;
898 for (i
= 0, j
= 0; i
< meminfo
.nr_banks
; i
++) {
899 struct membank
*bank
= &meminfo
.bank
[j
];
900 *bank
= meminfo
.bank
[i
];
902 if (bank
->start
> ULONG_MAX
)
905 #ifdef CONFIG_HIGHMEM
906 if (__va(bank
->start
) >= vmalloc_min
||
907 __va(bank
->start
) < (void *)PAGE_OFFSET
)
910 bank
->highmem
= highmem
;
913 * Split those memory banks which are partially overlapping
914 * the vmalloc area greatly simplifying things later.
916 if (!highmem
&& __va(bank
->start
) < vmalloc_min
&&
917 bank
->size
> vmalloc_min
- __va(bank
->start
)) {
918 if (meminfo
.nr_banks
>= NR_BANKS
) {
919 printk(KERN_CRIT
"NR_BANKS too low, "
920 "ignoring high memory\n");
922 memmove(bank
+ 1, bank
,
923 (meminfo
.nr_banks
- i
) * sizeof(*bank
));
926 bank
[1].size
-= vmalloc_min
- __va(bank
->start
);
927 bank
[1].start
= __pa(vmalloc_min
- 1) + 1;
928 bank
[1].highmem
= highmem
= 1;
931 bank
->size
= vmalloc_min
- __va(bank
->start
);
934 bank
->highmem
= highmem
;
937 * Highmem banks not allowed with !CONFIG_HIGHMEM.
940 printk(KERN_NOTICE
"Ignoring RAM at %.8llx-%.8llx "
941 "(!CONFIG_HIGHMEM).\n",
942 (unsigned long long)bank
->start
,
943 (unsigned long long)bank
->start
+ bank
->size
- 1);
948 * Check whether this memory bank would entirely overlap
951 if (__va(bank
->start
) >= vmalloc_min
||
952 __va(bank
->start
) < (void *)PAGE_OFFSET
) {
953 printk(KERN_NOTICE
"Ignoring RAM at %.8llx-%.8llx "
954 "(vmalloc region overlap).\n",
955 (unsigned long long)bank
->start
,
956 (unsigned long long)bank
->start
+ bank
->size
- 1);
961 * Check whether this memory bank would partially overlap
964 if (__va(bank
->start
+ bank
->size
- 1) >= vmalloc_min
||
965 __va(bank
->start
+ bank
->size
- 1) <= __va(bank
->start
)) {
966 unsigned long newsize
= vmalloc_min
- __va(bank
->start
);
967 printk(KERN_NOTICE
"Truncating RAM at %.8llx-%.8llx "
968 "to -%.8llx (vmalloc region overlap).\n",
969 (unsigned long long)bank
->start
,
970 (unsigned long long)bank
->start
+ bank
->size
- 1,
971 (unsigned long long)bank
->start
+ newsize
- 1);
972 bank
->size
= newsize
;
975 if (!bank
->highmem
&& bank
->start
+ bank
->size
> arm_lowmem_limit
)
976 arm_lowmem_limit
= bank
->start
+ bank
->size
;
980 #ifdef CONFIG_HIGHMEM
982 const char *reason
= NULL
;
984 if (cache_is_vipt_aliasing()) {
986 * Interactions between kmap and other mappings
987 * make highmem support with aliasing VIPT caches
990 reason
= "with VIPT aliasing cache";
993 printk(KERN_CRIT
"HIGHMEM is not supported %s, ignoring high memory\n",
995 while (j
> 0 && meminfo
.bank
[j
- 1].highmem
)
1000 meminfo
.nr_banks
= j
;
1001 high_memory
= __va(arm_lowmem_limit
- 1) + 1;
1002 memblock_set_current_limit(arm_lowmem_limit
);
1005 static inline void prepare_page_table(void)
1011 * Clear out all the mappings below the kernel image.
1013 for (addr
= 0; addr
< MODULES_VADDR
; addr
+= PMD_SIZE
)
1014 pmd_clear(pmd_off_k(addr
));
1016 #ifdef CONFIG_XIP_KERNEL
1017 /* The XIP kernel is mapped in the module area -- skip over it */
1018 addr
= ((unsigned long)_etext
+ PMD_SIZE
- 1) & PMD_MASK
;
1020 for ( ; addr
< PAGE_OFFSET
; addr
+= PMD_SIZE
)
1021 pmd_clear(pmd_off_k(addr
));
1024 * Find the end of the first block of lowmem.
1026 end
= memblock
.memory
.regions
[0].base
+ memblock
.memory
.regions
[0].size
;
1027 if (end
>= arm_lowmem_limit
)
1028 end
= arm_lowmem_limit
;
1031 * Clear out all the kernel space mappings, except for the first
1032 * memory bank, up to the vmalloc region.
1034 for (addr
= __phys_to_virt(end
);
1035 addr
< VMALLOC_START
; addr
+= PMD_SIZE
)
1036 pmd_clear(pmd_off_k(addr
));
1039 #ifdef CONFIG_ARM_LPAE
1040 /* the first page is reserved for pgd */
1041 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1042 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1044 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1048 * Reserve the special regions of memory
1050 void __init
arm_mm_memblock_reserve(void)
1053 * Reserve the page tables. These are already in use,
1054 * and can only be in node 0.
1056 memblock_reserve(__pa(swapper_pg_dir
), SWAPPER_PG_DIR_SIZE
);
1058 #ifdef CONFIG_SA1111
1060 * Because of the SA1111 DMA bug, we want to preserve our
1061 * precious DMA-able memory...
1063 memblock_reserve(PHYS_OFFSET
, __pa(swapper_pg_dir
) - PHYS_OFFSET
);
1068 * Set up the device mappings. Since we clear out the page tables for all
1069 * mappings above VMALLOC_START, we will remove any debug device mappings.
1070 * This means you have to be careful how you debug this function, or any
1071 * called function. This means you can't use any function or debugging
1072 * method which may touch any device, otherwise the kernel _will_ crash.
1074 static void __init
devicemaps_init(struct machine_desc
*mdesc
)
1076 struct map_desc map
;
1081 * Allocate the vector page early.
1083 vectors
= early_alloc(PAGE_SIZE
);
1085 early_trap_init(vectors
);
1087 for (addr
= VMALLOC_START
; addr
; addr
+= PMD_SIZE
)
1088 pmd_clear(pmd_off_k(addr
));
1091 * Map the kernel if it is XIP.
1092 * It is always first in the modulearea.
1094 #ifdef CONFIG_XIP_KERNEL
1095 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
1096 map
.virtual = MODULES_VADDR
;
1097 map
.length
= ((unsigned long)_etext
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
1099 create_mapping(&map
);
1103 * Map the cache flushing regions.
1106 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
1107 map
.virtual = FLUSH_BASE
;
1109 map
.type
= MT_CACHECLEAN
;
1110 create_mapping(&map
);
1112 #ifdef FLUSH_BASE_MINICACHE
1113 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
1114 map
.virtual = FLUSH_BASE_MINICACHE
;
1116 map
.type
= MT_MINICLEAN
;
1117 create_mapping(&map
);
1121 * Create a mapping for the machine vectors at the high-vectors
1122 * location (0xffff0000). If we aren't using high-vectors, also
1123 * create a mapping at the low-vectors virtual address.
1125 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
1126 map
.virtual = 0xffff0000;
1127 map
.length
= PAGE_SIZE
;
1128 map
.type
= MT_HIGH_VECTORS
;
1129 create_mapping(&map
);
1131 if (!vectors_high()) {
1133 map
.type
= MT_LOW_VECTORS
;
1134 create_mapping(&map
);
1138 * Ask the machine support to map in the statically mapped devices.
1145 * Finally flush the caches and tlb to ensure that we're in a
1146 * consistent state wrt the writebuffer. This also ensures that
1147 * any write-allocated cache lines in the vector page are written
1148 * back. After this point, we can start to touch devices again.
1150 local_flush_tlb_all();
1154 static void __init
kmap_init(void)
1156 #ifdef CONFIG_HIGHMEM
1157 pkmap_page_table
= early_pte_alloc(pmd_off_k(PKMAP_BASE
),
1158 PKMAP_BASE
, _PAGE_KERNEL_TABLE
);
1162 static void __init
map_lowmem(void)
1164 struct memblock_region
*reg
;
1166 /* Map all the lowmem memory banks. */
1167 for_each_memblock(memory
, reg
) {
1168 phys_addr_t start
= reg
->base
;
1169 phys_addr_t end
= start
+ reg
->size
;
1170 struct map_desc map
;
1172 if (end
> arm_lowmem_limit
)
1173 end
= arm_lowmem_limit
;
1177 map
.pfn
= __phys_to_pfn(start
);
1178 map
.virtual = __phys_to_virt(start
);
1179 map
.length
= end
- start
;
1180 map
.type
= MT_MEMORY
;
1182 create_mapping(&map
);
1187 * paging_init() sets up the page tables, initialises the zone memory
1188 * maps, and sets up the zero page, bad page and bad page tables.
1190 void __init
paging_init(struct machine_desc
*mdesc
)
1194 memblock_set_current_limit(arm_lowmem_limit
);
1196 build_mem_type_table();
1197 prepare_page_table();
1199 dma_contiguous_remap();
1200 devicemaps_init(mdesc
);
1203 top_pmd
= pmd_off_k(0xffff0000);
1205 /* allocate the zero page. */
1206 zero_page
= early_alloc(PAGE_SIZE
);
1210 empty_zero_page
= virt_to_page(zero_page
);
1211 __flush_dcache_page(NULL
, empty_zero_page
);