2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
17 #include <linux/sort.h>
19 #include <asm/cputype.h>
20 #include <asm/mach-types.h>
21 #include <asm/sections.h>
22 #include <asm/cachetype.h>
23 #include <asm/setup.h>
24 #include <asm/sizes.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
34 DEFINE_PER_CPU(struct mmu_gather
, mmu_gathers
);
37 * empty_zero_page is a special page that is used for
38 * zero-initialized data and COW.
40 struct page
*empty_zero_page
;
41 EXPORT_SYMBOL(empty_zero_page
);
44 * The pmd table for the upper-most set of pages.
48 #define CPOLICY_UNCACHED 0
49 #define CPOLICY_BUFFERED 1
50 #define CPOLICY_WRITETHROUGH 2
51 #define CPOLICY_WRITEBACK 3
52 #define CPOLICY_WRITEALLOC 4
54 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
55 static unsigned int ecc_mask __initdata
= 0;
57 pgprot_t pgprot_kernel
;
59 EXPORT_SYMBOL(pgprot_user
);
60 EXPORT_SYMBOL(pgprot_kernel
);
63 const char policy
[16];
69 static struct cachepolicy cache_policies
[] __initdata
= {
73 .pmd
= PMD_SECT_UNCACHED
,
74 .pte
= L_PTE_MT_UNCACHED
,
78 .pmd
= PMD_SECT_BUFFERED
,
79 .pte
= L_PTE_MT_BUFFERABLE
,
81 .policy
= "writethrough",
84 .pte
= L_PTE_MT_WRITETHROUGH
,
86 .policy
= "writeback",
89 .pte
= L_PTE_MT_WRITEBACK
,
91 .policy
= "writealloc",
94 .pte
= L_PTE_MT_WRITEALLOC
,
99 * These are useful for identifying cache coherency
100 * problems by allowing the cache or the cache and
101 * writebuffer to be turned off. (Note: the write
102 * buffer should not be on and the cache off).
104 static int __init
early_cachepolicy(char *p
)
108 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
109 int len
= strlen(cache_policies
[i
].policy
);
111 if (memcmp(p
, cache_policies
[i
].policy
, len
) == 0) {
113 cr_alignment
&= ~cache_policies
[i
].cr_mask
;
114 cr_no_alignment
&= ~cache_policies
[i
].cr_mask
;
118 if (i
== ARRAY_SIZE(cache_policies
))
119 printk(KERN_ERR
"ERROR: unknown or unsupported cache policy\n");
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
127 if (cpu_architecture() >= CPU_ARCH_ARMv6
) {
128 printk(KERN_WARNING
"Only cachepolicy=writeback supported on ARMv6 and later\n");
129 cachepolicy
= CPOLICY_WRITEBACK
;
132 set_cr(cr_alignment
);
135 early_param("cachepolicy", early_cachepolicy
);
137 static int __init
early_nocache(char *__unused
)
139 char *p
= "buffered";
140 printk(KERN_WARNING
"nocache is deprecated; use cachepolicy=%s\n", p
);
141 early_cachepolicy(p
);
144 early_param("nocache", early_nocache
);
146 static int __init
early_nowrite(char *__unused
)
148 char *p
= "uncached";
149 printk(KERN_WARNING
"nowb is deprecated; use cachepolicy=%s\n", p
);
150 early_cachepolicy(p
);
153 early_param("nowb", early_nowrite
);
155 static int __init
early_ecc(char *p
)
157 if (memcmp(p
, "on", 2) == 0)
158 ecc_mask
= PMD_PROTECTION
;
159 else if (memcmp(p
, "off", 3) == 0)
163 early_param("ecc", early_ecc
);
165 static int __init
noalign_setup(char *__unused
)
167 cr_alignment
&= ~CR_A
;
168 cr_no_alignment
&= ~CR_A
;
169 set_cr(cr_alignment
);
172 __setup("noalign", noalign_setup
);
175 void adjust_cr(unsigned long mask
, unsigned long set
)
183 local_irq_save(flags
);
185 cr_no_alignment
= (cr_no_alignment
& ~mask
) | set
;
186 cr_alignment
= (cr_alignment
& ~mask
) | set
;
188 set_cr((get_cr() & ~mask
) | set
);
190 local_irq_restore(flags
);
194 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
195 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
197 static struct mem_type mem_types
[] = {
198 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
199 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_SHARED
|
201 .prot_l1
= PMD_TYPE_TABLE
,
202 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_S
,
205 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
206 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_NONSHARED
,
207 .prot_l1
= PMD_TYPE_TABLE
,
208 .prot_sect
= PROT_SECT_DEVICE
,
211 [MT_DEVICE_CACHED
] = { /* ioremap_cached */
212 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_CACHED
,
213 .prot_l1
= PMD_TYPE_TABLE
,
214 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
217 [MT_DEVICE_WC
] = { /* ioremap_wc */
218 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_MT_DEV_WC
,
219 .prot_l1
= PMD_TYPE_TABLE
,
220 .prot_sect
= PROT_SECT_DEVICE
,
224 .prot_pte
= PROT_PTE_DEVICE
,
225 .prot_l1
= PMD_TYPE_TABLE
,
226 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
230 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
231 .domain
= DOMAIN_KERNEL
,
234 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
235 .domain
= DOMAIN_KERNEL
,
238 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
240 .prot_l1
= PMD_TYPE_TABLE
,
241 .domain
= DOMAIN_USER
,
243 [MT_HIGH_VECTORS
] = {
244 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
245 L_PTE_USER
| L_PTE_EXEC
,
246 .prot_l1
= PMD_TYPE_TABLE
,
247 .domain
= DOMAIN_USER
,
250 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
251 .domain
= DOMAIN_KERNEL
,
254 .prot_sect
= PMD_TYPE_SECT
,
255 .domain
= DOMAIN_KERNEL
,
257 [MT_MEMORY_NONCACHED
] = {
258 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
259 .domain
= DOMAIN_KERNEL
,
262 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
|
263 L_PTE_DIRTY
| L_PTE_WRITE
,
264 .prot_l1
= PMD_TYPE_TABLE
,
265 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
266 .domain
= DOMAIN_KERNEL
,
269 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
270 L_PTE_USER
| L_PTE_EXEC
,
271 .prot_l1
= PMD_TYPE_TABLE
,
276 const struct mem_type
*get_mem_type(unsigned int type
)
278 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
280 EXPORT_SYMBOL(get_mem_type
);
283 * Adjust the PMD section entries according to the CPU in use.
285 static void __init
build_mem_type_table(void)
287 struct cachepolicy
*cp
;
288 unsigned int cr
= get_cr();
289 unsigned int user_pgprot
, kern_pgprot
, vecs_pgprot
;
290 int cpu_arch
= cpu_architecture();
293 if (cpu_arch
< CPU_ARCH_ARMv6
) {
294 #if defined(CONFIG_CPU_DCACHE_DISABLE)
295 if (cachepolicy
> CPOLICY_BUFFERED
)
296 cachepolicy
= CPOLICY_BUFFERED
;
297 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
298 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
299 cachepolicy
= CPOLICY_WRITETHROUGH
;
302 if (cpu_arch
< CPU_ARCH_ARMv5
) {
303 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
304 cachepolicy
= CPOLICY_WRITEBACK
;
308 cachepolicy
= CPOLICY_WRITEALLOC
;
312 * Strip out features not present on earlier architectures.
313 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
314 * without extended page tables don't have the 'Shared' bit.
316 if (cpu_arch
< CPU_ARCH_ARMv5
)
317 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
318 mem_types
[i
].prot_sect
&= ~PMD_SECT_TEX(7);
319 if ((cpu_arch
< CPU_ARCH_ARMv6
|| !(cr
& CR_XP
)) && !cpu_is_xsc3())
320 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++)
321 mem_types
[i
].prot_sect
&= ~PMD_SECT_S
;
324 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
325 * "update-able on write" bit on ARM610). However, Xscale and
326 * Xscale3 require this bit to be cleared.
328 if (cpu_is_xscale() || cpu_is_xsc3()) {
329 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
330 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
331 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
333 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
334 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
335 if (mem_types
[i
].prot_l1
)
336 mem_types
[i
].prot_l1
|= PMD_BIT4
;
337 if (mem_types
[i
].prot_sect
)
338 mem_types
[i
].prot_sect
|= PMD_BIT4
;
343 * Mark the device areas according to the CPU/architecture.
345 if (cpu_is_xsc3() || (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
))) {
346 if (!cpu_is_xsc3()) {
348 * Mark device regions on ARMv6+ as execute-never
349 * to prevent speculative instruction fetches.
351 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_XN
;
352 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_XN
;
353 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_XN
;
354 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_XN
;
356 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
358 * For ARMv7 with TEX remapping,
359 * - shared device is SXCB=1100
360 * - nonshared device is SXCB=0100
361 * - write combine device mem is SXCB=0001
362 * (Uncached Normal memory)
364 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1);
365 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(1);
366 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
367 } else if (cpu_is_xsc3()) {
370 * - shared device is TEXCB=00101
371 * - nonshared device is TEXCB=01000
372 * - write combine device mem is TEXCB=00100
373 * (Inner/Outer Uncacheable in xsc3 parlance)
375 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED
;
376 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
377 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
380 * For ARMv6 and ARMv7 without TEX remapping,
381 * - shared device is TEXCB=00001
382 * - nonshared device is TEXCB=01000
383 * - write combine device mem is TEXCB=00100
384 * (Uncached Normal in ARMv6 parlance).
386 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
387 mem_types
[MT_DEVICE_NONSHARED
].prot_sect
|= PMD_SECT_TEX(2);
388 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_TEX(1);
392 * On others, write combining is "Uncached/Buffered"
394 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_BUFFERABLE
;
398 * Now deal with the memory-type mappings
400 cp
= &cache_policies
[cachepolicy
];
401 vecs_pgprot
= kern_pgprot
= user_pgprot
= cp
->pte
;
405 * Only use write-through for non-SMP systems
407 if (cpu_arch
>= CPU_ARCH_ARMv5
&& cachepolicy
> CPOLICY_WRITETHROUGH
)
408 vecs_pgprot
= cache_policies
[CPOLICY_WRITETHROUGH
].pte
;
412 * Enable CPU-specific coherency if supported.
413 * (Only available on XSC3 at the moment.)
415 if (arch_is_coherent() && cpu_is_xsc3())
416 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
419 * ARMv6 and above have extended page tables.
421 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
423 * Mark cache clean areas and XIP ROM read only
424 * from SVC mode and no access from userspace.
426 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
427 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
428 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
432 * Mark memory with the "shared" attribute for SMP systems
434 user_pgprot
|= L_PTE_SHARED
;
435 kern_pgprot
|= L_PTE_SHARED
;
436 vecs_pgprot
|= L_PTE_SHARED
;
437 mem_types
[MT_DEVICE_WC
].prot_sect
|= PMD_SECT_S
;
438 mem_types
[MT_DEVICE_WC
].prot_pte
|= L_PTE_SHARED
;
439 mem_types
[MT_DEVICE_CACHED
].prot_sect
|= PMD_SECT_S
;
440 mem_types
[MT_DEVICE_CACHED
].prot_pte
|= L_PTE_SHARED
;
441 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
442 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= PMD_SECT_S
;
447 * Non-cacheable Normal - intended for memory areas that must
448 * not cause dirty cache line writebacks when used
450 if (cpu_arch
>= CPU_ARCH_ARMv6
) {
451 if (cpu_arch
>= CPU_ARCH_ARMv7
&& (cr
& CR_TRE
)) {
452 /* Non-cacheable Normal is XCB = 001 */
453 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|=
456 /* For both ARMv6 and non-TEX-remapping ARMv7 */
457 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|=
461 mem_types
[MT_MEMORY_NONCACHED
].prot_sect
|= PMD_SECT_BUFFERABLE
;
464 for (i
= 0; i
< 16; i
++) {
465 unsigned long v
= pgprot_val(protection_map
[i
]);
466 protection_map
[i
] = __pgprot(v
| user_pgprot
);
469 mem_types
[MT_LOW_VECTORS
].prot_pte
|= vecs_pgprot
;
470 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= vecs_pgprot
;
472 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
473 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
474 L_PTE_DIRTY
| L_PTE_WRITE
| kern_pgprot
);
476 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
477 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
478 mem_types
[MT_MEMORY
].prot_sect
|= ecc_mask
| cp
->pmd
;
479 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
483 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
487 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
490 printk("Memory policy: ECC %sabled, Data cache %s\n",
491 ecc_mask
? "en" : "dis", cp
->policy
);
493 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
494 struct mem_type
*t
= &mem_types
[i
];
496 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
498 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
502 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
504 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
505 unsigned long end
, unsigned long pfn
,
506 const struct mem_type
*type
)
510 if (pmd_none(*pmd
)) {
511 pte
= alloc_bootmem_low_pages(2 * PTRS_PER_PTE
* sizeof(pte_t
));
512 __pmd_populate(pmd
, __pa(pte
) | type
->prot_l1
);
515 pte
= pte_offset_kernel(pmd
, addr
);
517 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)), 0);
519 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
522 static void __init
alloc_init_section(pgd_t
*pgd
, unsigned long addr
,
523 unsigned long end
, unsigned long phys
,
524 const struct mem_type
*type
)
526 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
529 * Try a section mapping - end, addr and phys must all be aligned
530 * to a section boundary. Note that PMDs refer to the individual
531 * L1 entries, whereas PGDs refer to a group of L1 entries making
532 * up one logical pointer to an L2 table.
534 if (((addr
| end
| phys
) & ~SECTION_MASK
) == 0) {
537 if (addr
& SECTION_SIZE
)
541 *pmd
= __pmd(phys
| type
->prot_sect
);
542 phys
+= SECTION_SIZE
;
543 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
548 * No need to loop; pte's aren't interested in the
549 * individual L1 entries.
551 alloc_init_pte(pmd
, addr
, end
, __phys_to_pfn(phys
), type
);
555 static void __init
create_36bit_mapping(struct map_desc
*md
,
556 const struct mem_type
*type
)
558 unsigned long phys
, addr
, length
, end
;
562 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
563 length
= PAGE_ALIGN(md
->length
);
565 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
566 printk(KERN_ERR
"MM: CPU does not support supersection "
567 "mapping for 0x%08llx at 0x%08lx\n",
568 __pfn_to_phys((u64
)md
->pfn
), addr
);
572 /* N.B. ARMv6 supersections are only defined to work with domain 0.
573 * Since domain assignments can in fact be arbitrary, the
574 * 'domain == 0' check below is required to insure that ARMv6
575 * supersections are only allocated for domain 0 regardless
576 * of the actual domain assignments in use.
579 printk(KERN_ERR
"MM: invalid domain in supersection "
580 "mapping for 0x%08llx at 0x%08lx\n",
581 __pfn_to_phys((u64
)md
->pfn
), addr
);
585 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
586 printk(KERN_ERR
"MM: cannot create mapping for "
587 "0x%08llx at 0x%08lx invalid alignment\n",
588 __pfn_to_phys((u64
)md
->pfn
), addr
);
593 * Shift bits [35:32] of address into bits [23:20] of PMD
596 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
598 pgd
= pgd_offset_k(addr
);
601 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
604 for (i
= 0; i
< 16; i
++)
605 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
);
607 addr
+= SUPERSECTION_SIZE
;
608 phys
+= SUPERSECTION_SIZE
;
609 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
610 } while (addr
!= end
);
614 * Create the page directory entries and any necessary
615 * page tables for the mapping specified by `md'. We
616 * are able to cope here with varying sizes and address
617 * offsets, and we take full advantage of sections and
620 static void __init
create_mapping(struct map_desc
*md
)
622 unsigned long phys
, addr
, length
, end
;
623 const struct mem_type
*type
;
626 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
627 printk(KERN_WARNING
"BUG: not creating mapping for "
628 "0x%08llx at 0x%08lx in user region\n",
629 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
633 if ((md
->type
== MT_DEVICE
|| md
->type
== MT_ROM
) &&
634 md
->virtual >= PAGE_OFFSET
&& md
->virtual < VMALLOC_END
) {
635 printk(KERN_WARNING
"BUG: mapping for 0x%08llx at 0x%08lx "
636 "overlaps vmalloc space\n",
637 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
640 type
= &mem_types
[md
->type
];
643 * Catch 36-bit addresses
645 if (md
->pfn
>= 0x100000) {
646 create_36bit_mapping(md
, type
);
650 addr
= md
->virtual & PAGE_MASK
;
651 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
652 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
654 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
655 printk(KERN_WARNING
"BUG: map for 0x%08lx at 0x%08lx can not "
656 "be mapped using pages, ignoring.\n",
657 __pfn_to_phys(md
->pfn
), addr
);
661 pgd
= pgd_offset_k(addr
);
664 unsigned long next
= pgd_addr_end(addr
, end
);
666 alloc_init_section(pgd
, addr
, next
, phys
, type
);
670 } while (pgd
++, addr
!= end
);
674 * Create the architecture specific mappings
676 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
680 for (i
= 0; i
< nr
; i
++)
681 create_mapping(io_desc
+ i
);
684 static unsigned long __initdata vmalloc_reserve
= SZ_128M
;
687 * vmalloc=size forces the vmalloc area to be exactly 'size'
688 * bytes. This can be used to increase (or decrease) the vmalloc
689 * area - the default is 128m.
691 static int __init
early_vmalloc(char *arg
)
693 vmalloc_reserve
= memparse(arg
, NULL
);
695 if (vmalloc_reserve
< SZ_16M
) {
696 vmalloc_reserve
= SZ_16M
;
698 "vmalloc area too small, limiting to %luMB\n",
699 vmalloc_reserve
>> 20);
702 if (vmalloc_reserve
> VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
)) {
703 vmalloc_reserve
= VMALLOC_END
- (PAGE_OFFSET
+ SZ_32M
);
705 "vmalloc area is too big, limiting to %luMB\n",
706 vmalloc_reserve
>> 20);
710 early_param("vmalloc", early_vmalloc
);
712 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
714 static void __init
sanity_check_meminfo(void)
716 int i
, j
, highmem
= 0;
718 for (i
= 0, j
= 0; i
< meminfo
.nr_banks
; i
++) {
719 struct membank
*bank
= &meminfo
.bank
[j
];
720 *bank
= meminfo
.bank
[i
];
722 #ifdef CONFIG_HIGHMEM
723 if (__va(bank
->start
) > VMALLOC_MIN
||
724 __va(bank
->start
) < (void *)PAGE_OFFSET
)
727 bank
->highmem
= highmem
;
730 * Split those memory banks which are partially overlapping
731 * the vmalloc area greatly simplifying things later.
733 if (__va(bank
->start
) < VMALLOC_MIN
&&
734 bank
->size
> VMALLOC_MIN
- __va(bank
->start
)) {
735 if (meminfo
.nr_banks
>= NR_BANKS
) {
736 printk(KERN_CRIT
"NR_BANKS too low, "
737 "ignoring high memory\n");
739 memmove(bank
+ 1, bank
,
740 (meminfo
.nr_banks
- i
) * sizeof(*bank
));
743 bank
[1].size
-= VMALLOC_MIN
- __va(bank
->start
);
744 bank
[1].start
= __pa(VMALLOC_MIN
- 1) + 1;
745 bank
[1].highmem
= highmem
= 1;
748 bank
->size
= VMALLOC_MIN
- __va(bank
->start
);
751 bank
->highmem
= highmem
;
754 * Check whether this memory bank would entirely overlap
757 if (__va(bank
->start
) >= VMALLOC_MIN
||
758 __va(bank
->start
) < (void *)PAGE_OFFSET
) {
759 printk(KERN_NOTICE
"Ignoring RAM at %.8lx-%.8lx "
760 "(vmalloc region overlap).\n",
761 bank
->start
, bank
->start
+ bank
->size
- 1);
766 * Check whether this memory bank would partially overlap
769 if (__va(bank
->start
+ bank
->size
) > VMALLOC_MIN
||
770 __va(bank
->start
+ bank
->size
) < __va(bank
->start
)) {
771 unsigned long newsize
= VMALLOC_MIN
- __va(bank
->start
);
772 printk(KERN_NOTICE
"Truncating RAM at %.8lx-%.8lx "
773 "to -%.8lx (vmalloc region overlap).\n",
774 bank
->start
, bank
->start
+ bank
->size
- 1,
775 bank
->start
+ newsize
- 1);
776 bank
->size
= newsize
;
781 #ifdef CONFIG_HIGHMEM
783 const char *reason
= NULL
;
785 if (cache_is_vipt_aliasing()) {
787 * Interactions between kmap and other mappings
788 * make highmem support with aliasing VIPT caches
791 reason
= "with VIPT aliasing cache";
793 } else if (tlb_ops_need_broadcast()) {
795 * kmap_high needs to occasionally flush TLB entries,
796 * however, if the TLB entries need to be broadcast
798 * kmap_high(irqs off)->flush_all_zero_pkmaps->
799 * flush_tlb_kernel_range->smp_call_function_many
800 * (must not be called with irqs off)
802 reason
= "without hardware TLB ops broadcasting";
806 printk(KERN_CRIT
"HIGHMEM is not supported %s, ignoring high memory\n",
808 while (j
> 0 && meminfo
.bank
[j
- 1].highmem
)
813 meminfo
.nr_banks
= j
;
816 static inline void prepare_page_table(void)
821 * Clear out all the mappings below the kernel image.
823 for (addr
= 0; addr
< MODULES_VADDR
; addr
+= PGDIR_SIZE
)
824 pmd_clear(pmd_off_k(addr
));
826 #ifdef CONFIG_XIP_KERNEL
827 /* The XIP kernel is mapped in the module area -- skip over it */
828 addr
= ((unsigned long)_etext
+ PGDIR_SIZE
- 1) & PGDIR_MASK
;
830 for ( ; addr
< PAGE_OFFSET
; addr
+= PGDIR_SIZE
)
831 pmd_clear(pmd_off_k(addr
));
834 * Clear out all the kernel space mappings, except for the first
835 * memory bank, up to the end of the vmalloc region.
837 for (addr
= __phys_to_virt(bank_phys_end(&meminfo
.bank
[0]));
838 addr
< VMALLOC_END
; addr
+= PGDIR_SIZE
)
839 pmd_clear(pmd_off_k(addr
));
843 * Reserve the various regions of node 0
845 void __init
reserve_node_zero(pg_data_t
*pgdat
)
847 unsigned long res_size
= 0;
850 * Register the kernel text and data with bootmem.
851 * Note that this can only be in node 0.
853 #ifdef CONFIG_XIP_KERNEL
854 reserve_bootmem_node(pgdat
, __pa(_data
), _end
- _data
,
857 reserve_bootmem_node(pgdat
, __pa(_stext
), _end
- _stext
,
862 * Reserve the page tables. These are already in use,
863 * and can only be in node 0.
865 reserve_bootmem_node(pgdat
, __pa(swapper_pg_dir
),
866 PTRS_PER_PGD
* sizeof(pgd_t
), BOOTMEM_DEFAULT
);
869 * Hmm... This should go elsewhere, but we really really need to
870 * stop things allocating the low memory; ideally we need a better
871 * implementation of GFP_DMA which does not assume that DMA-able
872 * memory starts at zero.
874 if (machine_is_integrator() || machine_is_cintegrator())
875 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
878 * These should likewise go elsewhere. They pre-reserve the
879 * screen memory region at the start of main system memory.
881 if (machine_is_edb7211())
882 res_size
= 0x00020000;
883 if (machine_is_p720t())
884 res_size
= 0x00014000;
886 /* H1940, RX3715 and RX1950 need to reserve this for suspend */
888 if (machine_is_h1940() || machine_is_rx3715()
889 || machine_is_rx1950()) {
890 reserve_bootmem_node(pgdat
, 0x30003000, 0x1000,
892 reserve_bootmem_node(pgdat
, 0x30081000, 0x1000,
896 if (machine_is_palmld() || machine_is_palmtx()) {
897 reserve_bootmem_node(pgdat
, 0xa0000000, 0x1000,
899 reserve_bootmem_node(pgdat
, 0xa0200000, 0x1000,
903 if (machine_is_treo680() || machine_is_centro()) {
904 reserve_bootmem_node(pgdat
, 0xa0000000, 0x1000,
906 reserve_bootmem_node(pgdat
, 0xa2000000, 0x1000,
910 if (machine_is_palmt5())
911 reserve_bootmem_node(pgdat
, 0xa0200000, 0x1000,
915 * U300 - This platform family can share physical memory
916 * between two ARM cpus, one running Linux and the other
917 * running another OS.
919 if (machine_is_u300()) {
920 #ifdef CONFIG_MACH_U300_SINGLE_RAM
921 #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \
922 CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
923 res_size
= 0x00100000;
930 * Because of the SA1111 DMA bug, we want to preserve our
931 * precious DMA-able memory...
933 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
936 reserve_bootmem_node(pgdat
, PHYS_OFFSET
, res_size
,
941 * Set up device the mappings. Since we clear out the page tables for all
942 * mappings above VMALLOC_END, we will remove any debug device mappings.
943 * This means you have to be careful how you debug this function, or any
944 * called function. This means you can't use any function or debugging
945 * method which may touch any device, otherwise the kernel _will_ crash.
947 static void __init
devicemaps_init(struct machine_desc
*mdesc
)
954 * Allocate the vector page early.
956 vectors
= alloc_bootmem_low_pages(PAGE_SIZE
);
958 for (addr
= VMALLOC_END
; addr
; addr
+= PGDIR_SIZE
)
959 pmd_clear(pmd_off_k(addr
));
962 * Map the kernel if it is XIP.
963 * It is always first in the modulearea.
965 #ifdef CONFIG_XIP_KERNEL
966 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
967 map
.virtual = MODULES_VADDR
;
968 map
.length
= ((unsigned long)_etext
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
970 create_mapping(&map
);
974 * Map the cache flushing regions.
977 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
978 map
.virtual = FLUSH_BASE
;
980 map
.type
= MT_CACHECLEAN
;
981 create_mapping(&map
);
983 #ifdef FLUSH_BASE_MINICACHE
984 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
985 map
.virtual = FLUSH_BASE_MINICACHE
;
987 map
.type
= MT_MINICLEAN
;
988 create_mapping(&map
);
992 * Create a mapping for the machine vectors at the high-vectors
993 * location (0xffff0000). If we aren't using high-vectors, also
994 * create a mapping at the low-vectors virtual address.
996 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
997 map
.virtual = 0xffff0000;
998 map
.length
= PAGE_SIZE
;
999 map
.type
= MT_HIGH_VECTORS
;
1000 create_mapping(&map
);
1002 if (!vectors_high()) {
1004 map
.type
= MT_LOW_VECTORS
;
1005 create_mapping(&map
);
1009 * Ask the machine support to map in the statically mapped devices.
1015 * Finally flush the caches and tlb to ensure that we're in a
1016 * consistent state wrt the writebuffer. This also ensures that
1017 * any write-allocated cache lines in the vector page are written
1018 * back. After this point, we can start to touch devices again.
1020 local_flush_tlb_all();
1024 static void __init
kmap_init(void)
1026 #ifdef CONFIG_HIGHMEM
1027 pmd_t
*pmd
= pmd_off_k(PKMAP_BASE
);
1028 pte_t
*pte
= alloc_bootmem_low_pages(2 * PTRS_PER_PTE
* sizeof(pte_t
));
1029 BUG_ON(!pmd_none(*pmd
) || !pte
);
1030 __pmd_populate(pmd
, __pa(pte
) | _PAGE_KERNEL_TABLE
);
1031 pkmap_page_table
= pte
+ PTRS_PER_PTE
;
1035 static inline void map_memory_bank(struct membank
*bank
)
1037 struct map_desc map
;
1039 map
.pfn
= bank_pfn_start(bank
);
1040 map
.virtual = __phys_to_virt(bank_phys_start(bank
));
1041 map
.length
= bank_phys_size(bank
);
1042 map
.type
= MT_MEMORY
;
1044 create_mapping(&map
);
1047 static void __init
map_lowmem(void)
1049 struct meminfo
*mi
= &meminfo
;
1052 /* Map all the lowmem memory banks. */
1053 for (i
= 0; i
< mi
->nr_banks
; i
++) {
1054 struct membank
*bank
= &mi
->bank
[i
];
1057 map_memory_bank(bank
);
1061 static int __init
meminfo_cmp(const void *_a
, const void *_b
)
1063 const struct membank
*a
= _a
, *b
= _b
;
1064 long cmp
= bank_pfn_start(a
) - bank_pfn_start(b
);
1065 return cmp
< 0 ? -1 : cmp
> 0 ? 1 : 0;
1069 * paging_init() sets up the page tables, initialises the zone memory
1070 * maps, and sets up the zero page, bad page and bad page tables.
1072 void __init
paging_init(struct machine_desc
*mdesc
)
1076 sort(&meminfo
.bank
, meminfo
.nr_banks
, sizeof(meminfo
.bank
[0]), meminfo_cmp
, NULL
);
1078 build_mem_type_table();
1079 sanity_check_meminfo();
1080 prepare_page_table();
1083 devicemaps_init(mdesc
);
1086 top_pmd
= pmd_off_k(0xffff0000);
1089 * allocate the zero page. Note that this always succeeds and
1090 * returns a zeroed result.
1092 zero_page
= alloc_bootmem_low_pages(PAGE_SIZE
);
1093 empty_zero_page
= virt_to_page(zero_page
);
1094 __flush_dcache_page(NULL
, empty_zero_page
);
1098 * In order to soft-boot, we need to insert a 1:1 mapping in place of
1099 * the user-mode pages. This will then ensure that we have predictable
1100 * results when turning the mmu off
1102 void setup_mm_for_reboot(char mode
)
1104 unsigned long base_pmdval
;
1109 * We need to access to user-mode page tables here. For kernel threads
1110 * we don't have any user-mode mappings so we use the context that we
1113 pgd
= current
->active_mm
->pgd
;
1115 base_pmdval
= PMD_SECT_AP_WRITE
| PMD_SECT_AP_READ
| PMD_TYPE_SECT
;
1116 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ
&& !cpu_is_xscale())
1117 base_pmdval
|= PMD_BIT4
;
1119 for (i
= 0; i
< FIRST_USER_PGD_NR
+ USER_PTRS_PER_PGD
; i
++, pgd
++) {
1120 unsigned long pmdval
= (i
<< PGDIR_SHIFT
) | base_pmdval
;
1123 pmd
= pmd_off(pgd
, i
<< PGDIR_SHIFT
);
1124 pmd
[0] = __pmd(pmdval
);
1125 pmd
[1] = __pmd(pmdval
+ (1 << (PGDIR_SHIFT
- 1)));
1126 flush_pmd_entry(pmd
);
1129 local_flush_tlb_all();