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Merge branch 'x86/numa' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux...
[deliverable/linux.git] / arch / arm / mm / mmu.c
1 /*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
17
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/setup.h>
21 #include <asm/sizes.h>
22 #include <asm/tlb.h>
23
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
26
27 #include "mm.h"
28
29 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
30
31 /*
32 * empty_zero_page is a special page that is used for
33 * zero-initialized data and COW.
34 */
35 struct page *empty_zero_page;
36 EXPORT_SYMBOL(empty_zero_page);
37
38 /*
39 * The pmd table for the upper-most set of pages.
40 */
41 pmd_t *top_pmd;
42
43 #define CPOLICY_UNCACHED 0
44 #define CPOLICY_BUFFERED 1
45 #define CPOLICY_WRITETHROUGH 2
46 #define CPOLICY_WRITEBACK 3
47 #define CPOLICY_WRITEALLOC 4
48
49 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
50 static unsigned int ecc_mask __initdata = 0;
51 pgprot_t pgprot_user;
52 pgprot_t pgprot_kernel;
53
54 EXPORT_SYMBOL(pgprot_user);
55 EXPORT_SYMBOL(pgprot_kernel);
56
57 struct cachepolicy {
58 const char policy[16];
59 unsigned int cr_mask;
60 unsigned int pmd;
61 unsigned int pte;
62 };
63
64 static struct cachepolicy cache_policies[] __initdata = {
65 {
66 .policy = "uncached",
67 .cr_mask = CR_W|CR_C,
68 .pmd = PMD_SECT_UNCACHED,
69 .pte = L_PTE_MT_UNCACHED,
70 }, {
71 .policy = "buffered",
72 .cr_mask = CR_C,
73 .pmd = PMD_SECT_BUFFERED,
74 .pte = L_PTE_MT_BUFFERABLE,
75 }, {
76 .policy = "writethrough",
77 .cr_mask = 0,
78 .pmd = PMD_SECT_WT,
79 .pte = L_PTE_MT_WRITETHROUGH,
80 }, {
81 .policy = "writeback",
82 .cr_mask = 0,
83 .pmd = PMD_SECT_WB,
84 .pte = L_PTE_MT_WRITEBACK,
85 }, {
86 .policy = "writealloc",
87 .cr_mask = 0,
88 .pmd = PMD_SECT_WBWA,
89 .pte = L_PTE_MT_WRITEALLOC,
90 }
91 };
92
93 /*
94 * These are useful for identifying cache coherency
95 * problems by allowing the cache or the cache and
96 * writebuffer to be turned off. (Note: the write
97 * buffer should not be on and the cache off).
98 */
99 static void __init early_cachepolicy(char **p)
100 {
101 int i;
102
103 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
104 int len = strlen(cache_policies[i].policy);
105
106 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
107 cachepolicy = i;
108 cr_alignment &= ~cache_policies[i].cr_mask;
109 cr_no_alignment &= ~cache_policies[i].cr_mask;
110 *p += len;
111 break;
112 }
113 }
114 if (i == ARRAY_SIZE(cache_policies))
115 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
116 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
117 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
118 cachepolicy = CPOLICY_WRITEBACK;
119 }
120 flush_cache_all();
121 set_cr(cr_alignment);
122 }
123 __early_param("cachepolicy=", early_cachepolicy);
124
125 static void __init early_nocache(char **__unused)
126 {
127 char *p = "buffered";
128 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
129 early_cachepolicy(&p);
130 }
131 __early_param("nocache", early_nocache);
132
133 static void __init early_nowrite(char **__unused)
134 {
135 char *p = "uncached";
136 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
137 early_cachepolicy(&p);
138 }
139 __early_param("nowb", early_nowrite);
140
141 static void __init early_ecc(char **p)
142 {
143 if (memcmp(*p, "on", 2) == 0) {
144 ecc_mask = PMD_PROTECTION;
145 *p += 2;
146 } else if (memcmp(*p, "off", 3) == 0) {
147 ecc_mask = 0;
148 *p += 3;
149 }
150 }
151 __early_param("ecc=", early_ecc);
152
153 static int __init noalign_setup(char *__unused)
154 {
155 cr_alignment &= ~CR_A;
156 cr_no_alignment &= ~CR_A;
157 set_cr(cr_alignment);
158 return 1;
159 }
160 __setup("noalign", noalign_setup);
161
162 #ifndef CONFIG_SMP
163 void adjust_cr(unsigned long mask, unsigned long set)
164 {
165 unsigned long flags;
166
167 mask &= ~CR_A;
168
169 set &= mask;
170
171 local_irq_save(flags);
172
173 cr_no_alignment = (cr_no_alignment & ~mask) | set;
174 cr_alignment = (cr_alignment & ~mask) | set;
175
176 set_cr((get_cr() & ~mask) | set);
177
178 local_irq_restore(flags);
179 }
180 #endif
181
182 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
183 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
184
185 static struct mem_type mem_types[] = {
186 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
187 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
188 L_PTE_SHARED,
189 .prot_l1 = PMD_TYPE_TABLE,
190 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
191 .domain = DOMAIN_IO,
192 },
193 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
194 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
195 .prot_l1 = PMD_TYPE_TABLE,
196 .prot_sect = PROT_SECT_DEVICE,
197 .domain = DOMAIN_IO,
198 },
199 [MT_DEVICE_CACHED] = { /* ioremap_cached */
200 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
201 .prot_l1 = PMD_TYPE_TABLE,
202 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
203 .domain = DOMAIN_IO,
204 },
205 [MT_DEVICE_WC] = { /* ioremap_wc */
206 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
207 .prot_l1 = PMD_TYPE_TABLE,
208 .prot_sect = PROT_SECT_DEVICE,
209 .domain = DOMAIN_IO,
210 },
211 [MT_UNCACHED] = {
212 .prot_pte = PROT_PTE_DEVICE,
213 .prot_l1 = PMD_TYPE_TABLE,
214 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
215 .domain = DOMAIN_IO,
216 },
217 [MT_CACHECLEAN] = {
218 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
219 .domain = DOMAIN_KERNEL,
220 },
221 [MT_MINICLEAN] = {
222 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
223 .domain = DOMAIN_KERNEL,
224 },
225 [MT_LOW_VECTORS] = {
226 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
227 L_PTE_EXEC,
228 .prot_l1 = PMD_TYPE_TABLE,
229 .domain = DOMAIN_USER,
230 },
231 [MT_HIGH_VECTORS] = {
232 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
233 L_PTE_USER | L_PTE_EXEC,
234 .prot_l1 = PMD_TYPE_TABLE,
235 .domain = DOMAIN_USER,
236 },
237 [MT_MEMORY] = {
238 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
239 .domain = DOMAIN_KERNEL,
240 },
241 [MT_ROM] = {
242 .prot_sect = PMD_TYPE_SECT,
243 .domain = DOMAIN_KERNEL,
244 },
245 };
246
247 const struct mem_type *get_mem_type(unsigned int type)
248 {
249 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
250 }
251
252 /*
253 * Adjust the PMD section entries according to the CPU in use.
254 */
255 static void __init build_mem_type_table(void)
256 {
257 struct cachepolicy *cp;
258 unsigned int cr = get_cr();
259 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
260 int cpu_arch = cpu_architecture();
261 int i;
262
263 if (cpu_arch < CPU_ARCH_ARMv6) {
264 #if defined(CONFIG_CPU_DCACHE_DISABLE)
265 if (cachepolicy > CPOLICY_BUFFERED)
266 cachepolicy = CPOLICY_BUFFERED;
267 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
268 if (cachepolicy > CPOLICY_WRITETHROUGH)
269 cachepolicy = CPOLICY_WRITETHROUGH;
270 #endif
271 }
272 if (cpu_arch < CPU_ARCH_ARMv5) {
273 if (cachepolicy >= CPOLICY_WRITEALLOC)
274 cachepolicy = CPOLICY_WRITEBACK;
275 ecc_mask = 0;
276 }
277 #ifdef CONFIG_SMP
278 cachepolicy = CPOLICY_WRITEALLOC;
279 #endif
280
281 /*
282 * Strip out features not present on earlier architectures.
283 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
284 * without extended page tables don't have the 'Shared' bit.
285 */
286 if (cpu_arch < CPU_ARCH_ARMv5)
287 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
288 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
289 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
290 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
291 mem_types[i].prot_sect &= ~PMD_SECT_S;
292
293 /*
294 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
295 * "update-able on write" bit on ARM610). However, Xscale and
296 * Xscale3 require this bit to be cleared.
297 */
298 if (cpu_is_xscale() || cpu_is_xsc3()) {
299 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
300 mem_types[i].prot_sect &= ~PMD_BIT4;
301 mem_types[i].prot_l1 &= ~PMD_BIT4;
302 }
303 } else if (cpu_arch < CPU_ARCH_ARMv6) {
304 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
305 if (mem_types[i].prot_l1)
306 mem_types[i].prot_l1 |= PMD_BIT4;
307 if (mem_types[i].prot_sect)
308 mem_types[i].prot_sect |= PMD_BIT4;
309 }
310 }
311
312 /*
313 * Mark the device areas according to the CPU/architecture.
314 */
315 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
316 if (!cpu_is_xsc3()) {
317 /*
318 * Mark device regions on ARMv6+ as execute-never
319 * to prevent speculative instruction fetches.
320 */
321 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
322 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
323 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
324 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
325 }
326 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
327 /*
328 * For ARMv7 with TEX remapping,
329 * - shared device is SXCB=1100
330 * - nonshared device is SXCB=0100
331 * - write combine device mem is SXCB=0001
332 * (Uncached Normal memory)
333 */
334 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
335 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
336 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
337 } else if (cpu_is_xsc3()) {
338 /*
339 * For Xscale3,
340 * - shared device is TEXCB=00101
341 * - nonshared device is TEXCB=01000
342 * - write combine device mem is TEXCB=00100
343 * (Inner/Outer Uncacheable in xsc3 parlance)
344 */
345 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
346 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
347 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
348 } else {
349 /*
350 * For ARMv6 and ARMv7 without TEX remapping,
351 * - shared device is TEXCB=00001
352 * - nonshared device is TEXCB=01000
353 * - write combine device mem is TEXCB=00100
354 * (Uncached Normal in ARMv6 parlance).
355 */
356 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
357 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
358 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
359 }
360 } else {
361 /*
362 * On others, write combining is "Uncached/Buffered"
363 */
364 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
365 }
366
367 /*
368 * Now deal with the memory-type mappings
369 */
370 cp = &cache_policies[cachepolicy];
371 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
372
373 #ifndef CONFIG_SMP
374 /*
375 * Only use write-through for non-SMP systems
376 */
377 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
378 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
379 #endif
380
381 /*
382 * Enable CPU-specific coherency if supported.
383 * (Only available on XSC3 at the moment.)
384 */
385 if (arch_is_coherent() && cpu_is_xsc3())
386 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
387
388 /*
389 * ARMv6 and above have extended page tables.
390 */
391 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
392 /*
393 * Mark cache clean areas and XIP ROM read only
394 * from SVC mode and no access from userspace.
395 */
396 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
397 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
398 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
399
400 #ifdef CONFIG_SMP
401 /*
402 * Mark memory with the "shared" attribute for SMP systems
403 */
404 user_pgprot |= L_PTE_SHARED;
405 kern_pgprot |= L_PTE_SHARED;
406 vecs_pgprot |= L_PTE_SHARED;
407 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
408 #endif
409 }
410
411 for (i = 0; i < 16; i++) {
412 unsigned long v = pgprot_val(protection_map[i]);
413 protection_map[i] = __pgprot(v | user_pgprot);
414 }
415
416 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
417 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
418
419 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
420 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
421 L_PTE_DIRTY | L_PTE_WRITE |
422 L_PTE_EXEC | kern_pgprot);
423
424 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
425 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
426 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
427 mem_types[MT_ROM].prot_sect |= cp->pmd;
428
429 switch (cp->pmd) {
430 case PMD_SECT_WT:
431 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
432 break;
433 case PMD_SECT_WB:
434 case PMD_SECT_WBWA:
435 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
436 break;
437 }
438 printk("Memory policy: ECC %sabled, Data cache %s\n",
439 ecc_mask ? "en" : "dis", cp->policy);
440
441 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
442 struct mem_type *t = &mem_types[i];
443 if (t->prot_l1)
444 t->prot_l1 |= PMD_DOMAIN(t->domain);
445 if (t->prot_sect)
446 t->prot_sect |= PMD_DOMAIN(t->domain);
447 }
448 }
449
450 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
451
452 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
453 unsigned long end, unsigned long pfn,
454 const struct mem_type *type)
455 {
456 pte_t *pte;
457
458 if (pmd_none(*pmd)) {
459 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
460 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
461 }
462
463 pte = pte_offset_kernel(pmd, addr);
464 do {
465 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
466 pfn++;
467 } while (pte++, addr += PAGE_SIZE, addr != end);
468 }
469
470 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
471 unsigned long end, unsigned long phys,
472 const struct mem_type *type)
473 {
474 pmd_t *pmd = pmd_offset(pgd, addr);
475
476 /*
477 * Try a section mapping - end, addr and phys must all be aligned
478 * to a section boundary. Note that PMDs refer to the individual
479 * L1 entries, whereas PGDs refer to a group of L1 entries making
480 * up one logical pointer to an L2 table.
481 */
482 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
483 pmd_t *p = pmd;
484
485 if (addr & SECTION_SIZE)
486 pmd++;
487
488 do {
489 *pmd = __pmd(phys | type->prot_sect);
490 phys += SECTION_SIZE;
491 } while (pmd++, addr += SECTION_SIZE, addr != end);
492
493 flush_pmd_entry(p);
494 } else {
495 /*
496 * No need to loop; pte's aren't interested in the
497 * individual L1 entries.
498 */
499 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
500 }
501 }
502
503 static void __init create_36bit_mapping(struct map_desc *md,
504 const struct mem_type *type)
505 {
506 unsigned long phys, addr, length, end;
507 pgd_t *pgd;
508
509 addr = md->virtual;
510 phys = (unsigned long)__pfn_to_phys(md->pfn);
511 length = PAGE_ALIGN(md->length);
512
513 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
514 printk(KERN_ERR "MM: CPU does not support supersection "
515 "mapping for 0x%08llx at 0x%08lx\n",
516 __pfn_to_phys((u64)md->pfn), addr);
517 return;
518 }
519
520 /* N.B. ARMv6 supersections are only defined to work with domain 0.
521 * Since domain assignments can in fact be arbitrary, the
522 * 'domain == 0' check below is required to insure that ARMv6
523 * supersections are only allocated for domain 0 regardless
524 * of the actual domain assignments in use.
525 */
526 if (type->domain) {
527 printk(KERN_ERR "MM: invalid domain in supersection "
528 "mapping for 0x%08llx at 0x%08lx\n",
529 __pfn_to_phys((u64)md->pfn), addr);
530 return;
531 }
532
533 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
534 printk(KERN_ERR "MM: cannot create mapping for "
535 "0x%08llx at 0x%08lx invalid alignment\n",
536 __pfn_to_phys((u64)md->pfn), addr);
537 return;
538 }
539
540 /*
541 * Shift bits [35:32] of address into bits [23:20] of PMD
542 * (See ARMv6 spec).
543 */
544 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
545
546 pgd = pgd_offset_k(addr);
547 end = addr + length;
548 do {
549 pmd_t *pmd = pmd_offset(pgd, addr);
550 int i;
551
552 for (i = 0; i < 16; i++)
553 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
554
555 addr += SUPERSECTION_SIZE;
556 phys += SUPERSECTION_SIZE;
557 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
558 } while (addr != end);
559 }
560
561 /*
562 * Create the page directory entries and any necessary
563 * page tables for the mapping specified by `md'. We
564 * are able to cope here with varying sizes and address
565 * offsets, and we take full advantage of sections and
566 * supersections.
567 */
568 void __init create_mapping(struct map_desc *md)
569 {
570 unsigned long phys, addr, length, end;
571 const struct mem_type *type;
572 pgd_t *pgd;
573
574 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
575 printk(KERN_WARNING "BUG: not creating mapping for "
576 "0x%08llx at 0x%08lx in user region\n",
577 __pfn_to_phys((u64)md->pfn), md->virtual);
578 return;
579 }
580
581 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
582 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
583 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
584 "overlaps vmalloc space\n",
585 __pfn_to_phys((u64)md->pfn), md->virtual);
586 }
587
588 type = &mem_types[md->type];
589
590 /*
591 * Catch 36-bit addresses
592 */
593 if (md->pfn >= 0x100000) {
594 create_36bit_mapping(md, type);
595 return;
596 }
597
598 addr = md->virtual & PAGE_MASK;
599 phys = (unsigned long)__pfn_to_phys(md->pfn);
600 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
601
602 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
603 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
604 "be mapped using pages, ignoring.\n",
605 __pfn_to_phys(md->pfn), addr);
606 return;
607 }
608
609 pgd = pgd_offset_k(addr);
610 end = addr + length;
611 do {
612 unsigned long next = pgd_addr_end(addr, end);
613
614 alloc_init_section(pgd, addr, next, phys, type);
615
616 phys += next - addr;
617 addr = next;
618 } while (pgd++, addr != end);
619 }
620
621 /*
622 * Create the architecture specific mappings
623 */
624 void __init iotable_init(struct map_desc *io_desc, int nr)
625 {
626 int i;
627
628 for (i = 0; i < nr; i++)
629 create_mapping(io_desc + i);
630 }
631
632 static unsigned long __initdata vmalloc_reserve = SZ_128M;
633
634 /*
635 * vmalloc=size forces the vmalloc area to be exactly 'size'
636 * bytes. This can be used to increase (or decrease) the vmalloc
637 * area - the default is 128m.
638 */
639 static void __init early_vmalloc(char **arg)
640 {
641 vmalloc_reserve = memparse(*arg, arg);
642
643 if (vmalloc_reserve < SZ_16M) {
644 vmalloc_reserve = SZ_16M;
645 printk(KERN_WARNING
646 "vmalloc area too small, limiting to %luMB\n",
647 vmalloc_reserve >> 20);
648 }
649 }
650 __early_param("vmalloc=", early_vmalloc);
651
652 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
653
654 static int __init check_membank_valid(struct membank *mb)
655 {
656 /*
657 * Check whether this memory region has non-zero size or
658 * invalid node number.
659 */
660 if (mb->size == 0 || mb->node >= MAX_NUMNODES)
661 return 0;
662
663 /*
664 * Check whether this memory region would entirely overlap
665 * the vmalloc area.
666 */
667 if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
668 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
669 "(vmalloc region overlap).\n",
670 mb->start, mb->start + mb->size - 1);
671 return 0;
672 }
673
674 /*
675 * Check whether this memory region would partially overlap
676 * the vmalloc area.
677 */
678 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
679 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
680 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
681
682 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
683 "to -%.8lx (vmalloc region overlap).\n",
684 mb->start, mb->start + mb->size - 1,
685 mb->start + newsize - 1);
686 mb->size = newsize;
687 }
688
689 return 1;
690 }
691
692 static void __init sanity_check_meminfo(struct meminfo *mi)
693 {
694 int i, j;
695
696 for (i = 0, j = 0; i < mi->nr_banks; i++) {
697 if (check_membank_valid(&mi->bank[i]))
698 mi->bank[j++] = mi->bank[i];
699 }
700 mi->nr_banks = j;
701 }
702
703 static inline void prepare_page_table(struct meminfo *mi)
704 {
705 unsigned long addr;
706
707 /*
708 * Clear out all the mappings below the kernel image.
709 */
710 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
711 pmd_clear(pmd_off_k(addr));
712
713 #ifdef CONFIG_XIP_KERNEL
714 /* The XIP kernel is mapped in the module area -- skip over it */
715 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
716 #endif
717 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
718 pmd_clear(pmd_off_k(addr));
719
720 /*
721 * Clear out all the kernel space mappings, except for the first
722 * memory bank, up to the end of the vmalloc region.
723 */
724 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
725 addr < VMALLOC_END; addr += PGDIR_SIZE)
726 pmd_clear(pmd_off_k(addr));
727 }
728
729 /*
730 * Reserve the various regions of node 0
731 */
732 void __init reserve_node_zero(pg_data_t *pgdat)
733 {
734 unsigned long res_size = 0;
735
736 /*
737 * Register the kernel text and data with bootmem.
738 * Note that this can only be in node 0.
739 */
740 #ifdef CONFIG_XIP_KERNEL
741 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
742 BOOTMEM_DEFAULT);
743 #else
744 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
745 BOOTMEM_DEFAULT);
746 #endif
747
748 /*
749 * Reserve the page tables. These are already in use,
750 * and can only be in node 0.
751 */
752 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
753 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
754
755 /*
756 * Hmm... This should go elsewhere, but we really really need to
757 * stop things allocating the low memory; ideally we need a better
758 * implementation of GFP_DMA which does not assume that DMA-able
759 * memory starts at zero.
760 */
761 if (machine_is_integrator() || machine_is_cintegrator())
762 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
763
764 /*
765 * These should likewise go elsewhere. They pre-reserve the
766 * screen memory region at the start of main system memory.
767 */
768 if (machine_is_edb7211())
769 res_size = 0x00020000;
770 if (machine_is_p720t())
771 res_size = 0x00014000;
772
773 /* H1940 and RX3715 need to reserve this for suspend */
774
775 if (machine_is_h1940() || machine_is_rx3715()) {
776 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
777 BOOTMEM_DEFAULT);
778 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
779 BOOTMEM_DEFAULT);
780 }
781
782 #ifdef CONFIG_SA1111
783 /*
784 * Because of the SA1111 DMA bug, we want to preserve our
785 * precious DMA-able memory...
786 */
787 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
788 #endif
789 if (res_size)
790 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
791 BOOTMEM_DEFAULT);
792 }
793
794 /*
795 * Set up device the mappings. Since we clear out the page tables for all
796 * mappings above VMALLOC_END, we will remove any debug device mappings.
797 * This means you have to be careful how you debug this function, or any
798 * called function. This means you can't use any function or debugging
799 * method which may touch any device, otherwise the kernel _will_ crash.
800 */
801 static void __init devicemaps_init(struct machine_desc *mdesc)
802 {
803 struct map_desc map;
804 unsigned long addr;
805 void *vectors;
806
807 /*
808 * Allocate the vector page early.
809 */
810 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
811 BUG_ON(!vectors);
812
813 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
814 pmd_clear(pmd_off_k(addr));
815
816 /*
817 * Map the kernel if it is XIP.
818 * It is always first in the modulearea.
819 */
820 #ifdef CONFIG_XIP_KERNEL
821 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
822 map.virtual = MODULES_VADDR;
823 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
824 map.type = MT_ROM;
825 create_mapping(&map);
826 #endif
827
828 /*
829 * Map the cache flushing regions.
830 */
831 #ifdef FLUSH_BASE
832 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
833 map.virtual = FLUSH_BASE;
834 map.length = SZ_1M;
835 map.type = MT_CACHECLEAN;
836 create_mapping(&map);
837 #endif
838 #ifdef FLUSH_BASE_MINICACHE
839 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
840 map.virtual = FLUSH_BASE_MINICACHE;
841 map.length = SZ_1M;
842 map.type = MT_MINICLEAN;
843 create_mapping(&map);
844 #endif
845
846 /*
847 * Create a mapping for the machine vectors at the high-vectors
848 * location (0xffff0000). If we aren't using high-vectors, also
849 * create a mapping at the low-vectors virtual address.
850 */
851 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
852 map.virtual = 0xffff0000;
853 map.length = PAGE_SIZE;
854 map.type = MT_HIGH_VECTORS;
855 create_mapping(&map);
856
857 if (!vectors_high()) {
858 map.virtual = 0;
859 map.type = MT_LOW_VECTORS;
860 create_mapping(&map);
861 }
862
863 /*
864 * Ask the machine support to map in the statically mapped devices.
865 */
866 if (mdesc->map_io)
867 mdesc->map_io();
868
869 /*
870 * Finally flush the caches and tlb to ensure that we're in a
871 * consistent state wrt the writebuffer. This also ensures that
872 * any write-allocated cache lines in the vector page are written
873 * back. After this point, we can start to touch devices again.
874 */
875 local_flush_tlb_all();
876 flush_cache_all();
877 }
878
879 /*
880 * paging_init() sets up the page tables, initialises the zone memory
881 * maps, and sets up the zero page, bad page and bad page tables.
882 */
883 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
884 {
885 void *zero_page;
886
887 build_mem_type_table();
888 sanity_check_meminfo(mi);
889 prepare_page_table(mi);
890 bootmem_init(mi);
891 devicemaps_init(mdesc);
892
893 top_pmd = pmd_off_k(0xffff0000);
894
895 /*
896 * allocate the zero page. Note that we count on this going ok.
897 */
898 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
899 memzero(zero_page, PAGE_SIZE);
900 empty_zero_page = virt_to_page(zero_page);
901 flush_dcache_page(empty_zero_page);
902 }
903
904 /*
905 * In order to soft-boot, we need to insert a 1:1 mapping in place of
906 * the user-mode pages. This will then ensure that we have predictable
907 * results when turning the mmu off
908 */
909 void setup_mm_for_reboot(char mode)
910 {
911 unsigned long base_pmdval;
912 pgd_t *pgd;
913 int i;
914
915 if (current->mm && current->mm->pgd)
916 pgd = current->mm->pgd;
917 else
918 pgd = init_mm.pgd;
919
920 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
921 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
922 base_pmdval |= PMD_BIT4;
923
924 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
925 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
926 pmd_t *pmd;
927
928 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
929 pmd[0] = __pmd(pmdval);
930 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
931 flush_pmd_entry(pmd);
932 }
933 }
Linux kernel - Deliverables
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