arch/arm/mm/proc-arm1020e.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
   3  *
   4  *  Copyright (C) 2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  *
  22  * These are the low level assembler for performing cache and TLB
  23  * functions on the arm1020e.
  24  *
  25  *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
  26  */
  27 #include <linux/linkage.h>
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <asm/assembler.h>
  31 #include <asm/asm-offsets.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/procinfo.h>
  34 #include <asm/ptrace.h>
  35
  36 /*
  37  * This is the maximum size of an area which will be invalidated
  38  * using the single invalidate entry instructions.  Anything larger
  39  * than this, and we go for the whole cache.
  40  *
  41  * This value should be chosen such that we choose the cheapest
  42  * alternative.
  43  */
  44 #define MAX_AREA_SIZE   32768
  45
  46 /*
  47  * The size of one data cache line.
  48  */
  49 #define CACHE_DLINESIZE 32
  50
  51 /*
  52  * The number of data cache segments.
  53  */
  54 #define CACHE_DSEGMENTS 16
  55
  56 /*
  57  * The number of lines in a cache segment.
  58  */
  59 #define CACHE_DENTRIES  64
  60
  61 /*
  62  * This is the size at which it becomes more efficient to
  63  * clean the whole cache, rather than using the individual
  64  * cache line maintainence instructions.
  65  */
  66 #define CACHE_DLIMIT    32768
  67
  68         .text
  69 /*
  70  * cpu_arm1020e_proc_init()
  71  */
  72 ENTRY(cpu_arm1020e_proc_init)
  73         mov     pc, lr
  74
  75 /*
  76  * cpu_arm1020e_proc_fin()
  77  */
  78 ENTRY(cpu_arm1020e_proc_fin)
  79         stmfd   sp!, {lr}
  80         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  81         msr     cpsr_c, ip
  82         bl      arm1020e_flush_kern_cache_all
  83         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  84         bic     r0, r0, #0x1000                 @ ...i............
  85         bic     r0, r0, #0x000e                 @ ............wca.
  86         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  87         ldmfd   sp!, {pc}
  88
  89 /*
  90  * cpu_arm1020e_reset(loc)
  91  *
  92  * Perform a soft reset of the system.  Put the CPU into the
  93  * same state as it would be if it had been reset, and branch
  94  * to what would be the reset vector.
  95  *
  96  * loc: location to jump to for soft reset
  97  */
  98         .align  5
  99 ENTRY(cpu_arm1020e_reset)
 100         mov     ip, #0
 101         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
 102         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 103         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 104         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
 105         bic     ip, ip, #0x000f                 @ ............wcam
 106         bic     ip, ip, #0x1100                 @ ...i...s........
 107         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 108         mov     pc, r0
 109
 110 /*
 111  * cpu_arm1020e_do_idle()
 112  */
 113         .align  5
 114 ENTRY(cpu_arm1020e_do_idle)
 115         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 116         mov     pc, lr
 117
 118 /* ================================= CACHE ================================ */
 119
 120         .align  5
 121 /*
 122  *      flush_user_cache_all()
 123  *
 124  *      Invalidate all cache entries in a particular address
 125  *      space.
 126  */
 127 ENTRY(arm1020e_flush_user_cache_all)
 128         /* FALLTHROUGH */
 129 /*
 130  *      flush_kern_cache_all()
 131  *
 132  *      Clean and invalidate the entire cache.
 133  */
 134 ENTRY(arm1020e_flush_kern_cache_all)
 135         mov     r2, #VM_EXEC
 136         mov     ip, #0
 137 __flush_whole_cache:
 138 #ifndef CONFIG_CPU_DCACHE_DISABLE
 139         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 140         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
 141 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 142 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 143         subs    r3, r3, #1 << 26
 144         bcs     2b                              @ entries 63 to 0
 145         subs    r1, r1, #1 << 5
 146         bcs     1b                              @ segments 15 to 0
 147 #endif
 148         tst     r2, #VM_EXEC
 149 #ifndef CONFIG_CPU_ICACHE_DISABLE
 150         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 151 #endif
 152         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 153         mov     pc, lr
 154
 155 /*
 156  *      flush_user_cache_range(start, end, flags)
 157  *
 158  *      Invalidate a range of cache entries in the specified
 159  *      address space.
 160  *
 161  *      - start - start address (inclusive)
 162  *      - end   - end address (exclusive)
 163  *      - flags - vm_flags for this space
 164  */
 165 ENTRY(arm1020e_flush_user_cache_range)
 166         mov     ip, #0
 167         sub     r3, r1, r0                      @ calculate total size
 168         cmp     r3, #CACHE_DLIMIT
 169         bhs     __flush_whole_cache
 170
 171 #ifndef CONFIG_CPU_DCACHE_DISABLE
 172 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 173         add     r0, r0, #CACHE_DLINESIZE
 174         cmp     r0, r1
 175         blo     1b
 176 #endif
 177         tst     r2, #VM_EXEC
 178 #ifndef CONFIG_CPU_ICACHE_DISABLE
 179         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 180 #endif
 181         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 182         mov     pc, lr
 183
 184 /*
 185  *      coherent_kern_range(start, end)
 186  *
 187  *      Ensure coherency between the Icache and the Dcache in the
 188  *      region described by start.  If you have non-snooping
 189  *      Harvard caches, you need to implement this function.
 190  *
 191  *      - start - virtual start address
 192  *      - end   - virtual end address
 193  */
 194 ENTRY(arm1020e_coherent_kern_range)
 195         /* FALLTHROUGH */
 196 /*
 197  *      coherent_user_range(start, end)
 198  *
 199  *      Ensure coherency between the Icache and the Dcache in the
 200  *      region described by start.  If you have non-snooping
 201  *      Harvard caches, you need to implement this function.
 202  *
 203  *      - start - virtual start address
 204  *      - end   - virtual end address
 205  */
 206 ENTRY(arm1020e_coherent_user_range)
 207         mov     ip, #0
 208         bic     r0, r0, #CACHE_DLINESIZE - 1
 209 1:
 210 #ifndef CONFIG_CPU_DCACHE_DISABLE
 211         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 212 #endif
 213 #ifndef CONFIG_CPU_ICACHE_DISABLE
 214         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 215 #endif
 216         add     r0, r0, #CACHE_DLINESIZE
 217         cmp     r0, r1
 218         blo     1b
 219         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 220         mov     pc, lr
 221
 222 /*
 223  *      flush_kern_dcache_page(void *page)
 224  *
 225  *      Ensure no D cache aliasing occurs, either with itself or
 226  *      the I cache
 227  *
 228  *      - page  - page aligned address
 229  */
 230 ENTRY(arm1020e_flush_kern_dcache_page)
 231         mov     ip, #0
 232 #ifndef CONFIG_CPU_DCACHE_DISABLE
 233         add     r1, r0, #PAGE_SZ
 234 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 235         add     r0, r0, #CACHE_DLINESIZE
 236         cmp     r0, r1
 237         blo     1b
 238 #endif
 239         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 240         mov     pc, lr
 241
 242 /*
 243  *      dma_inv_range(start, end)
 244  *
 245  *      Invalidate (discard) the specified virtual address range.
 246  *      May not write back any entries.  If 'start' or 'end'
 247  *      are not cache line aligned, those lines must be written
 248  *      back.
 249  *
 250  *      - start - virtual start address
 251  *      - end   - virtual end address
 252  *
 253  * (same as v4wb)
 254  */
 255 ENTRY(arm1020e_dma_inv_range)
 256         mov     ip, #0
 257 #ifndef CONFIG_CPU_DCACHE_DISABLE
 258         tst     r0, #CACHE_DLINESIZE - 1
 259         bic     r0, r0, #CACHE_DLINESIZE - 1
 260         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 261         tst     r1, #CACHE_DLINESIZE - 1
 262         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 263 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 264         add     r0, r0, #CACHE_DLINESIZE
 265         cmp     r0, r1
 266         blo     1b
 267 #endif
 268         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 269         mov     pc, lr
 270
 271 /*
 272  *      dma_clean_range(start, end)
 273  *
 274  *      Clean the specified virtual address range.
 275  *
 276  *      - start - virtual start address
 277  *      - end   - virtual end address
 278  *
 279  * (same as v4wb)
 280  */
 281 ENTRY(arm1020e_dma_clean_range)
 282         mov     ip, #0
 283 #ifndef CONFIG_CPU_DCACHE_DISABLE
 284         bic     r0, r0, #CACHE_DLINESIZE - 1
 285 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 286         add     r0, r0, #CACHE_DLINESIZE
 287         cmp     r0, r1
 288         blo     1b
 289 #endif
 290         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 291         mov     pc, lr
 292
 293 /*
 294  *      dma_flush_range(start, end)
 295  *
 296  *      Clean and invalidate the specified virtual address range.
 297  *
 298  *      - start - virtual start address
 299  *      - end   - virtual end address
 300  */
 301 ENTRY(arm1020e_dma_flush_range)
 302         mov     ip, #0
 303 #ifndef CONFIG_CPU_DCACHE_DISABLE
 304         bic     r0, r0, #CACHE_DLINESIZE - 1
 305 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 306         add     r0, r0, #CACHE_DLINESIZE
 307         cmp     r0, r1
 308         blo     1b
 309 #endif
 310         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 311         mov     pc, lr
 312
 313 ENTRY(arm1020e_cache_fns)
 314         .long   arm1020e_flush_kern_cache_all
 315         .long   arm1020e_flush_user_cache_all
 316         .long   arm1020e_flush_user_cache_range
 317         .long   arm1020e_coherent_kern_range
 318         .long   arm1020e_coherent_user_range
 319         .long   arm1020e_flush_kern_dcache_page
 320         .long   arm1020e_dma_inv_range
 321         .long   arm1020e_dma_clean_range
 322         .long   arm1020e_dma_flush_range
 323
 324         .align  5
 325 ENTRY(cpu_arm1020e_dcache_clean_area)
 326 #ifndef CONFIG_CPU_DCACHE_DISABLE
 327         mov     ip, #0
 328 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 329         add     r0, r0, #CACHE_DLINESIZE
 330         subs    r1, r1, #CACHE_DLINESIZE
 331         bhi     1b
 332 #endif
 333         mov     pc, lr
 334
 335 /* =============================== PageTable ============================== */
 336
 337 /*
 338  * cpu_arm1020e_switch_mm(pgd)
 339  *
 340  * Set the translation base pointer to be as described by pgd.
 341  *
 342  * pgd: new page tables
 343  */
 344         .align  5
 345 ENTRY(cpu_arm1020e_switch_mm)
 346 #ifndef CONFIG_CPU_DCACHE_DISABLE
 347         mcr     p15, 0, r3, c7, c10, 4
 348         mov     r1, #0xF                        @ 16 segments
 349 1:      mov     r3, #0x3F                       @ 64 entries
 350 2:      mov     ip, r3, LSL #26                 @ shift up entry
 351         orr     ip, ip, r1, LSL #5              @ shift in/up index
 352         mcr     p15, 0, ip, c7, c14, 2          @ Clean & Inval DCache entry
 353         mov     ip, #0
 354         subs    r3, r3, #1
 355         cmp     r3, #0
 356         bge     2b                              @ entries 3F to 0
 357         subs    r1, r1, #1
 358         cmp     r1, #0
 359         bge     1b                              @ segments 15 to 0
 360
 361 #endif
 362         mov     r1, #0
 363 #ifndef CONFIG_CPU_ICACHE_DISABLE
 364         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 365 #endif
 366         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 367         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 368         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 369         mov     pc, lr
 370
 371 /*
 372  * cpu_arm1020e_set_pte(ptep, pte)
 373  *
 374  * Set a PTE and flush it out
 375  */
 376         .align  5
 377 ENTRY(cpu_arm1020e_set_pte)
 378         str     r1, [r0], #-2048                @ linux version
 379
 380         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 381
 382         bic     r2, r1, #PTE_SMALL_AP_MASK
 383         bic     r2, r2, #PTE_TYPE_MASK
 384         orr     r2, r2, #PTE_TYPE_SMALL
 385
 386         tst     r1, #L_PTE_USER                 @ User?
 387         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 388
 389         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 390         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 391
 392         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 393         movne   r2, #0
 394
 395 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 396         eor     r3, r1, #0x0a                   @ C & small page?
 397         tst     r3, #0x0b
 398         biceq   r2, r2, #4
 399 #endif
 400         str     r2, [r0]                        @ hardware version
 401         mov     r0, r0
 402 #ifndef CONFIG_CPU_DCACHE_DISABLE
 403         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 404 #endif
 405         mov     pc, lr
 406
 407         __INIT
 408
 409         .type   __arm1020e_setup, #function
 410 __arm1020e_setup:
 411         mov     r0, #0
 412         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 413         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 414         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 415         mrc     p15, 0, r0, c1, c0              @ get control register v4
 416         ldr     r5, arm1020e_cr1_clear
 417         bic     r0, r0, r5
 418         ldr     r5, arm1020e_cr1_set
 419         orr     r0, r0, r5
 420 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 421         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 422 #endif
 423         mov     pc, lr
 424         .size   __arm1020e_setup, . - __arm1020e_setup
 425
 426         /*
 427          *  R
 428          * .RVI ZFRS BLDP WCAM
 429          * .011 1001 ..11 0101
 430          */
 431         .type   arm1020e_cr1_clear, #object
 432         .type   arm1020e_cr1_set, #object
 433 arm1020e_cr1_clear:
 434         .word   0x5f3f
 435 arm1020e_cr1_set:
 436         .word   0x3935
 437
 438         __INITDATA
 439
 440 /*
 441  * Purpose : Function pointers used to access above functions - all calls
 442  *           come through these
 443  */
 444         .type   arm1020e_processor_functions, #object
 445 arm1020e_processor_functions:
 446         .word   v4t_early_abort
 447         .word   cpu_arm1020e_proc_init
 448         .word   cpu_arm1020e_proc_fin
 449         .word   cpu_arm1020e_reset
 450         .word   cpu_arm1020e_do_idle
 451         .word   cpu_arm1020e_dcache_clean_area
 452         .word   cpu_arm1020e_switch_mm
 453         .word   cpu_arm1020e_set_pte
 454         .size   arm1020e_processor_functions, . - arm1020e_processor_functions
 455
 456         .section ".rodata"
 457
 458         .type   cpu_arch_name, #object
 459 cpu_arch_name:
 460         .asciz  "armv5te"
 461         .size   cpu_arch_name, . - cpu_arch_name
 462
 463         .type   cpu_elf_name, #object
 464 cpu_elf_name:
 465         .asciz  "v5"
 466         .size   cpu_elf_name, . - cpu_elf_name
 467
 468         .type   cpu_arm1020e_name, #object
 469 cpu_arm1020e_name:
 470         .ascii  "ARM1020E"
 471 #ifndef CONFIG_CPU_ICACHE_DISABLE
 472         .ascii  "i"
 473 #endif
 474 #ifndef CONFIG_CPU_DCACHE_DISABLE
 475         .ascii  "d"
 476 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 477         .ascii  "(wt)"
 478 #else
 479         .ascii  "(wb)"
 480 #endif
 481 #endif
 482 #ifndef CONFIG_CPU_BPREDICT_DISABLE
 483         .ascii  "B"
 484 #endif
 485 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 486         .ascii  "RR"
 487 #endif
 488         .ascii  "\0"
 489         .size   cpu_arm1020e_name, . - cpu_arm1020e_name
 490
 491         .align
 492
 493         .section ".proc.info.init", #alloc, #execinstr
 494
 495         .type   __arm1020e_proc_info,#object
 496 __arm1020e_proc_info:
 497         .long   0x4105a200                      @ ARM 1020TE (Architecture v5TE)
 498         .long   0xff0ffff0
 499         .long   PMD_TYPE_SECT | \
 500                 PMD_BIT4 | \
 501                 PMD_SECT_AP_WRITE | \
 502                 PMD_SECT_AP_READ
 503         b       __arm1020e_setup
 504         .long   cpu_arch_name
 505         .long   cpu_elf_name
 506         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
 507         .long   cpu_arm1020e_name
 508         .long   arm1020e_processor_functions
 509         .long   v4wbi_tlb_fns
 510         .long   v4wb_user_fns
 511         .long   arm1020e_cache_fns
 512         .size   __arm1020e_proc_info, . - __arm1020e_proc_info