arch/arm/mm/proc-arm1026.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
   3  *
   4  *  Copyright (C) 2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  *
  14  * These are the low level assembler for performing cache and TLB
  15  * functions on the ARM1026EJ-S.
  16  */
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/pgtable-hwdef.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/procinfo.h>
  24 #include <asm/ptrace.h>
  25
  26 /*
  27  * This is the maximum size of an area which will be invalidated
  28  * using the single invalidate entry instructions.  Anything larger
  29  * than this, and we go for the whole cache.
  30  *
  31  * This value should be chosen such that we choose the cheapest
  32  * alternative.
  33  */
  34 #define MAX_AREA_SIZE   32768
  35
  36 /*
  37  * The size of one data cache line.
  38  */
  39 #define CACHE_DLINESIZE 32
  40
  41 /*
  42  * The number of data cache segments.
  43  */
  44 #define CACHE_DSEGMENTS 16
  45
  46 /*
  47  * The number of lines in a cache segment.
  48  */
  49 #define CACHE_DENTRIES  64
  50
  51 /*
  52  * This is the size at which it becomes more efficient to
  53  * clean the whole cache, rather than using the individual
  54  * cache line maintainence instructions.
  55  */
  56 #define CACHE_DLIMIT    32768
  57
  58         .text
  59 /*
  60  * cpu_arm1026_proc_init()
  61  */
  62 ENTRY(cpu_arm1026_proc_init)
  63         mov     pc, lr
  64
  65 /*
  66  * cpu_arm1026_proc_fin()
  67  */
  68 ENTRY(cpu_arm1026_proc_fin)
  69         stmfd   sp!, {lr}
  70         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  71         msr     cpsr_c, ip
  72         bl      arm1026_flush_kern_cache_all
  73         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  74         bic     r0, r0, #0x1000                 @ ...i............
  75         bic     r0, r0, #0x000e                 @ ............wca.
  76         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  77         ldmfd   sp!, {pc}
  78
  79 /*
  80  * cpu_arm1026_reset(loc)
  81  *
  82  * Perform a soft reset of the system.  Put the CPU into the
  83  * same state as it would be if it had been reset, and branch
  84  * to what would be the reset vector.
  85  *
  86  * loc: location to jump to for soft reset
  87  */
  88         .align  5
  89 ENTRY(cpu_arm1026_reset)
  90         mov     ip, #0
  91         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  92         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  93 #ifdef CONFIG_MMU
  94         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  95 #endif
  96         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  97         bic     ip, ip, #0x000f                 @ ............wcam
  98         bic     ip, ip, #0x1100                 @ ...i...s........
  99         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 100         mov     pc, r0
 101
 102 /*
 103  * cpu_arm1026_do_idle()
 104  */
 105         .align  5
 106 ENTRY(cpu_arm1026_do_idle)
 107         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 108         mov     pc, lr
 109
 110 /* ================================= CACHE ================================ */
 111
 112         .align  5
 113 /*
 114  *      flush_user_cache_all()
 115  *
 116  *      Invalidate all cache entries in a particular address
 117  *      space.
 118  */
 119 ENTRY(arm1026_flush_user_cache_all)
 120         /* FALLTHROUGH */
 121 /*
 122  *      flush_kern_cache_all()
 123  *
 124  *      Clean and invalidate the entire cache.
 125  */
 126 ENTRY(arm1026_flush_kern_cache_all)
 127         mov     r2, #VM_EXEC
 128         mov     ip, #0
 129 __flush_whole_cache:
 130 #ifndef CONFIG_CPU_DCACHE_DISABLE
 131 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 132         bne     1b
 133 #endif
 134         tst     r2, #VM_EXEC
 135 #ifndef CONFIG_CPU_ICACHE_DISABLE
 136         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 137 #endif
 138         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 139         mov     pc, lr
 140
 141 /*
 142  *      flush_user_cache_range(start, end, flags)
 143  *
 144  *      Invalidate a range of cache entries in the specified
 145  *      address space.
 146  *
 147  *      - start - start address (inclusive)
 148  *      - end   - end address (exclusive)
 149  *      - flags - vm_flags for this space
 150  */
 151 ENTRY(arm1026_flush_user_cache_range)
 152         mov     ip, #0
 153         sub     r3, r1, r0                      @ calculate total size
 154         cmp     r3, #CACHE_DLIMIT
 155         bhs     __flush_whole_cache
 156
 157 #ifndef CONFIG_CPU_DCACHE_DISABLE
 158 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 159         add     r0, r0, #CACHE_DLINESIZE
 160         cmp     r0, r1
 161         blo     1b
 162 #endif
 163         tst     r2, #VM_EXEC
 164 #ifndef CONFIG_CPU_ICACHE_DISABLE
 165         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 166 #endif
 167         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 168         mov     pc, lr
 169
 170 /*
 171  *      coherent_kern_range(start, end)
 172  *
 173  *      Ensure coherency between the Icache and the Dcache in the
 174  *      region described by start.  If you have non-snooping
 175  *      Harvard caches, you need to implement this function.
 176  *
 177  *      - start - virtual start address
 178  *      - end   - virtual end address
 179  */
 180 ENTRY(arm1026_coherent_kern_range)
 181         /* FALLTHROUGH */
 182 /*
 183  *      coherent_user_range(start, end)
 184  *
 185  *      Ensure coherency between the Icache and the Dcache in the
 186  *      region described by start.  If you have non-snooping
 187  *      Harvard caches, you need to implement this function.
 188  *
 189  *      - start - virtual start address
 190  *      - end   - virtual end address
 191  */
 192 ENTRY(arm1026_coherent_user_range)
 193         mov     ip, #0
 194         bic     r0, r0, #CACHE_DLINESIZE - 1
 195 1:
 196 #ifndef CONFIG_CPU_DCACHE_DISABLE
 197         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 198 #endif
 199 #ifndef CONFIG_CPU_ICACHE_DISABLE
 200         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 201 #endif
 202         add     r0, r0, #CACHE_DLINESIZE
 203         cmp     r0, r1
 204         blo     1b
 205         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 206         mov     pc, lr
 207
 208 /*
 209  *      flush_kern_dcache_page(void *page)
 210  *
 211  *      Ensure no D cache aliasing occurs, either with itself or
 212  *      the I cache
 213  *
 214  *      - page  - page aligned address
 215  */
 216 ENTRY(arm1026_flush_kern_dcache_page)
 217         mov     ip, #0
 218 #ifndef CONFIG_CPU_DCACHE_DISABLE
 219         add     r1, r0, #PAGE_SZ
 220 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 221         add     r0, r0, #CACHE_DLINESIZE
 222         cmp     r0, r1
 223         blo     1b
 224 #endif
 225         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 226         mov     pc, lr
 227
 228 /*
 229  *      dma_inv_range(start, end)
 230  *
 231  *      Invalidate (discard) the specified virtual address range.
 232  *      May not write back any entries.  If 'start' or 'end'
 233  *      are not cache line aligned, those lines must be written
 234  *      back.
 235  *
 236  *      - start - virtual start address
 237  *      - end   - virtual end address
 238  *
 239  * (same as v4wb)
 240  */
 241 ENTRY(arm1026_dma_inv_range)
 242         mov     ip, #0
 243 #ifndef CONFIG_CPU_DCACHE_DISABLE
 244         tst     r0, #CACHE_DLINESIZE - 1
 245         bic     r0, r0, #CACHE_DLINESIZE - 1
 246         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 247         tst     r1, #CACHE_DLINESIZE - 1
 248         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 249 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 250         add     r0, r0, #CACHE_DLINESIZE
 251         cmp     r0, r1
 252         blo     1b
 253 #endif
 254         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 255         mov     pc, lr
 256
 257 /*
 258  *      dma_clean_range(start, end)
 259  *
 260  *      Clean the specified virtual address range.
 261  *
 262  *      - start - virtual start address
 263  *      - end   - virtual end address
 264  *
 265  * (same as v4wb)
 266  */
 267 ENTRY(arm1026_dma_clean_range)
 268         mov     ip, #0
 269 #ifndef CONFIG_CPU_DCACHE_DISABLE
 270         bic     r0, r0, #CACHE_DLINESIZE - 1
 271 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 272         add     r0, r0, #CACHE_DLINESIZE
 273         cmp     r0, r1
 274         blo     1b
 275 #endif
 276         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 277         mov     pc, lr
 278
 279 /*
 280  *      dma_flush_range(start, end)
 281  *
 282  *      Clean and invalidate the specified virtual address range.
 283  *
 284  *      - start - virtual start address
 285  *      - end   - virtual end address
 286  */
 287 ENTRY(arm1026_dma_flush_range)
 288         mov     ip, #0
 289 #ifndef CONFIG_CPU_DCACHE_DISABLE
 290         bic     r0, r0, #CACHE_DLINESIZE - 1
 291 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 292         add     r0, r0, #CACHE_DLINESIZE
 293         cmp     r0, r1
 294         blo     1b
 295 #endif
 296         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 297         mov     pc, lr
 298
 299 ENTRY(arm1026_cache_fns)
 300         .long   arm1026_flush_kern_cache_all
 301         .long   arm1026_flush_user_cache_all
 302         .long   arm1026_flush_user_cache_range
 303         .long   arm1026_coherent_kern_range
 304         .long   arm1026_coherent_user_range
 305         .long   arm1026_flush_kern_dcache_page
 306         .long   arm1026_dma_inv_range
 307         .long   arm1026_dma_clean_range
 308         .long   arm1026_dma_flush_range
 309
 310         .align  5
 311 ENTRY(cpu_arm1026_dcache_clean_area)
 312 #ifndef CONFIG_CPU_DCACHE_DISABLE
 313         mov     ip, #0
 314 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 315         add     r0, r0, #CACHE_DLINESIZE
 316         subs    r1, r1, #CACHE_DLINESIZE
 317         bhi     1b
 318 #endif
 319         mov     pc, lr
 320
 321 /* =============================== PageTable ============================== */
 322
 323 /*
 324  * cpu_arm1026_switch_mm(pgd)
 325  *
 326  * Set the translation base pointer to be as described by pgd.
 327  *
 328  * pgd: new page tables
 329  */
 330         .align  5
 331 ENTRY(cpu_arm1026_switch_mm)
 332 #ifdef CONFIG_MMU
 333         mov     r1, #0
 334 #ifndef CONFIG_CPU_DCACHE_DISABLE
 335 1:      mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
 336         bne     1b
 337 #endif
 338 #ifndef CONFIG_CPU_ICACHE_DISABLE
 339         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 340 #endif
 341         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 342         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 343         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 344 #endif
 345         mov     pc, lr
 346
 347 /*
 348  * cpu_arm1026_set_pte(ptep, pte)
 349  *
 350  * Set a PTE and flush it out
 351  */
 352         .align  5
 353 ENTRY(cpu_arm1026_set_pte)
 354 #ifdef CONFIG_MMU
 355         str     r1, [r0], #-2048                @ linux version
 356
 357         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 358
 359         bic     r2, r1, #PTE_SMALL_AP_MASK
 360         bic     r2, r2, #PTE_TYPE_MASK
 361         orr     r2, r2, #PTE_TYPE_SMALL
 362
 363         tst     r1, #L_PTE_USER                 @ User?
 364         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 365
 366         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 367         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 368
 369         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 370         movne   r2, #0
 371
 372 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 373         eor     r3, r1, #0x0a                   @ C & small page?
 374         tst     r3, #0x0b
 375         biceq   r2, r2, #4
 376 #endif
 377         str     r2, [r0]                        @ hardware version
 378         mov     r0, r0
 379 #ifndef CONFIG_CPU_DCACHE_DISABLE
 380         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 381 #endif
 382 #endif /* CONFIG_MMU */
 383         mov     pc, lr
 384
 385
 386         __INIT
 387
 388         .type   __arm1026_setup, #function
 389 __arm1026_setup:
 390         mov     r0, #0
 391         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 392         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 393 #ifdef CONFIG_MMU
 394         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 395         mcr     p15, 0, r4, c2, c0              @ load page table pointer
 396 #endif
 397 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 398         mov     r0, #4                          @ explicitly disable writeback
 399         mcr     p15, 7, r0, c15, c0, 0
 400 #endif
 401         adr     r5, arm1026_crval
 402         ldmia   r5, {r5, r6}
 403         mrc     p15, 0, r0, c1, c0              @ get control register v4
 404         bic     r0, r0, r5
 405         orr     r0, r0, r6
 406 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 407         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 408 #endif
 409         mov     pc, lr
 410         .size   __arm1026_setup, . - __arm1026_setup
 411
 412         /*
 413          *  R
 414          * .RVI ZFRS BLDP WCAM
 415          * .011 1001 ..11 0101
 416          *
 417          */
 418         .type   arm1026_crval, #object
 419 arm1026_crval:
 420         crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 421
 422         __INITDATA
 423
 424 /*
 425  * Purpose : Function pointers used to access above functions - all calls
 426  *           come through these
 427  */
 428         .type   arm1026_processor_functions, #object
 429 arm1026_processor_functions:
 430         .word   v5t_early_abort
 431         .word   cpu_arm1026_proc_init
 432         .word   cpu_arm1026_proc_fin
 433         .word   cpu_arm1026_reset
 434         .word   cpu_arm1026_do_idle
 435         .word   cpu_arm1026_dcache_clean_area
 436         .word   cpu_arm1026_switch_mm
 437         .word   cpu_arm1026_set_pte
 438         .size   arm1026_processor_functions, . - arm1026_processor_functions
 439
 440         .section .rodata
 441
 442         .type   cpu_arch_name, #object
 443 cpu_arch_name:
 444         .asciz  "armv5tej"
 445         .size   cpu_arch_name, . - cpu_arch_name
 446
 447         .type   cpu_elf_name, #object
 448 cpu_elf_name:
 449         .asciz  "v5"
 450         .size   cpu_elf_name, . - cpu_elf_name
 451         .align
 452
 453         .type   cpu_arm1026_name, #object
 454 cpu_arm1026_name:
 455         .asciz  "ARM1026EJ-S"
 456         .size   cpu_arm1026_name, . - cpu_arm1026_name
 457
 458         .align
 459
 460         .section ".proc.info.init", #alloc, #execinstr
 461
 462         .type   __arm1026_proc_info,#object
 463 __arm1026_proc_info:
 464         .long   0x4106a260                      @ ARM 1026EJ-S (v5TEJ)
 465         .long   0xff0ffff0
 466         .long   PMD_TYPE_SECT | \
 467                 PMD_BIT4 | \
 468                 PMD_SECT_AP_WRITE | \
 469                 PMD_SECT_AP_READ
 470         .long   PMD_TYPE_SECT | \
 471                 PMD_BIT4 | \
 472                 PMD_SECT_AP_WRITE | \
 473                 PMD_SECT_AP_READ
 474         b       __arm1026_setup
 475         .long   cpu_arch_name
 476         .long   cpu_elf_name
 477         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
 478         .long   cpu_arm1026_name
 479         .long   arm1026_processor_functions
 480         .long   v4wbi_tlb_fns
 481         .long   v4wb_user_fns
 482         .long   arm1026_cache_fns
 483         .size   __arm1026_proc_info, . - __arm1026_proc_info