arch/arm/mm/proc-arm920.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
   3  *
   4  *  Copyright (C) 1999,2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  *
  22  * These are the low level assembler for performing cache and TLB
  23  * functions on the arm920.
  24  *
  25  *  CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
  26  */
  27 #include <linux/linkage.h>
  28 #include <linux/config.h>
  29 #include <linux/init.h>
  30 #include <asm/assembler.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/procinfo.h>
  33 #include <asm/page.h>
  34 #include <asm/ptrace.h>
  35 #include "proc-macros.S"
  36
  37 /*
  38  * The size of one data cache line.
  39  */
  40 #define CACHE_DLINESIZE 32
  41
  42 /*
  43  * The number of data cache segments.
  44  */
  45 #define CACHE_DSEGMENTS 8
  46
  47 /*
  48  * The number of lines in a cache segment.
  49  */
  50 #define CACHE_DENTRIES  64
  51
  52 /*
  53  * This is the size at which it becomes more efficient to
  54  * clean the whole cache, rather than using the individual
  55  * cache line maintainence instructions.
  56  */
  57 #define CACHE_DLIMIT    65536
  58
  59
  60         .text
  61 /*
  62  * cpu_arm920_proc_init()
  63  */
  64 ENTRY(cpu_arm920_proc_init)
  65         mov     pc, lr
  66
  67 /*
  68  * cpu_arm920_proc_fin()
  69  */
  70 ENTRY(cpu_arm920_proc_fin)
  71         stmfd   sp!, {lr}
  72         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  73         msr     cpsr_c, ip
  74 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  75         bl      arm920_flush_kern_cache_all
  76 #else
  77         bl      v4wt_flush_kern_cache_all
  78 #endif
  79         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  80         bic     r0, r0, #0x1000                 @ ...i............
  81         bic     r0, r0, #0x000e                 @ ............wca.
  82         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  83         ldmfd   sp!, {pc}
  84
  85 /*
  86  * cpu_arm920_reset(loc)
  87  *
  88  * Perform a soft reset of the system.  Put the CPU into the
  89  * same state as it would be if it had been reset, and branch
  90  * to what would be the reset vector.
  91  *
  92  * loc: location to jump to for soft reset
  93  */
  94         .align  5
  95 ENTRY(cpu_arm920_reset)
  96         mov     ip, #0
  97         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  98         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  99         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 100         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
 101         bic     ip, ip, #0x000f                 @ ............wcam
 102         bic     ip, ip, #0x1100                 @ ...i...s........
 103         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 104         mov     pc, r0
 105
 106 /*
 107  * cpu_arm920_do_idle()
 108  */
 109         .align  5
 110 ENTRY(cpu_arm920_do_idle)
 111         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 112         mov     pc, lr
 113
 114
 115 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 116
 117 /*
 118  *      flush_user_cache_all()
 119  *
 120  *      Invalidate all cache entries in a particular address
 121  *      space.
 122  */
 123 ENTRY(arm920_flush_user_cache_all)
 124         /* FALLTHROUGH */
 125
 126 /*
 127  *      flush_kern_cache_all()
 128  *
 129  *      Clean and invalidate the entire cache.
 130  */
 131 ENTRY(arm920_flush_kern_cache_all)
 132         mov     r2, #VM_EXEC
 133         mov     ip, #0
 134 __flush_whole_cache:
 135         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
 136 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 137 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 138         subs    r3, r3, #1 << 26
 139         bcs     2b                              @ entries 63 to 0
 140         subs    r1, r1, #1 << 5
 141         bcs     1b                              @ segments 7 to 0
 142         tst     r2, #VM_EXEC
 143         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 144         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 145         mov     pc, lr
 146
 147 /*
 148  *      flush_user_cache_range(start, end, flags)
 149  *
 150  *      Invalidate a range of cache entries in the specified
 151  *      address space.
 152  *
 153  *      - start - start address (inclusive)
 154  *      - end   - end address (exclusive)
 155  *      - flags - vm_flags for address space
 156  */
 157 ENTRY(arm920_flush_user_cache_range)
 158         mov     ip, #0
 159         sub     r3, r1, r0                      @ calculate total size
 160         cmp     r3, #CACHE_DLIMIT
 161         bhs     __flush_whole_cache
 162
 163 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 164         tst     r2, #VM_EXEC
 165         mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
 166         add     r0, r0, #CACHE_DLINESIZE
 167         cmp     r0, r1
 168         blo     1b
 169         tst     r2, #VM_EXEC
 170         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 171         mov     pc, lr
 172
 173 /*
 174  *      coherent_kern_range(start, end)
 175  *
 176  *      Ensure coherency between the Icache and the Dcache in the
 177  *      region described by start, end.  If you have non-snooping
 178  *      Harvard caches, you need to implement this function.
 179  *
 180  *      - start - virtual start address
 181  *      - end   - virtual end address
 182  */
 183 ENTRY(arm920_coherent_kern_range)
 184         /* FALLTHROUGH */
 185
 186 /*
 187  *      coherent_user_range(start, end)
 188  *
 189  *      Ensure coherency between the Icache and the Dcache in the
 190  *      region described by start, end.  If you have non-snooping
 191  *      Harvard caches, you need to implement this function.
 192  *
 193  *      - start - virtual start address
 194  *      - end   - virtual end address
 195  */
 196 ENTRY(arm920_coherent_user_range)
 197         bic     r0, r0, #CACHE_DLINESIZE - 1
 198 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 199         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 200         add     r0, r0, #CACHE_DLINESIZE
 201         cmp     r0, r1
 202         blo     1b
 203         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 204         mov     pc, lr
 205
 206 /*
 207  *      flush_kern_dcache_page(void *page)
 208  *
 209  *      Ensure no D cache aliasing occurs, either with itself or
 210  *      the I cache
 211  *
 212  *      - addr  - page aligned address
 213  */
 214 ENTRY(arm920_flush_kern_dcache_page)
 215         add     r1, r0, #PAGE_SZ
 216 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 217         add     r0, r0, #CACHE_DLINESIZE
 218         cmp     r0, r1
 219         blo     1b
 220         mov     r0, #0
 221         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 222         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 223         mov     pc, lr
 224
 225 /*
 226  *      dma_inv_range(start, end)
 227  *
 228  *      Invalidate (discard) the specified virtual address range.
 229  *      May not write back any entries.  If 'start' or 'end'
 230  *      are not cache line aligned, those lines must be written
 231  *      back.
 232  *
 233  *      - start - virtual start address
 234  *      - end   - virtual end address
 235  *
 236  * (same as v4wb)
 237  */
 238 ENTRY(arm920_dma_inv_range)
 239         tst     r0, #CACHE_DLINESIZE - 1
 240         bic     r0, r0, #CACHE_DLINESIZE - 1
 241         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 242         tst     r1, #CACHE_DLINESIZE - 1
 243         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 244 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 245         add     r0, r0, #CACHE_DLINESIZE
 246         cmp     r0, r1
 247         blo     1b
 248         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 249         mov     pc, lr
 250
 251 /*
 252  *      dma_clean_range(start, end)
 253  *
 254  *      Clean the specified virtual address range.
 255  *
 256  *      - start - virtual start address
 257  *      - end   - virtual end address
 258  *
 259  * (same as v4wb)
 260  */
 261 ENTRY(arm920_dma_clean_range)
 262         bic     r0, r0, #CACHE_DLINESIZE - 1
 263 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 264         add     r0, r0, #CACHE_DLINESIZE
 265         cmp     r0, r1
 266         blo     1b
 267         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 268         mov     pc, lr
 269
 270 /*
 271  *      dma_flush_range(start, end)
 272  *
 273  *      Clean and invalidate the specified virtual address range.
 274  *
 275  *      - start - virtual start address
 276  *      - end   - virtual end address
 277  */
 278 ENTRY(arm920_dma_flush_range)
 279         bic     r0, r0, #CACHE_DLINESIZE - 1
 280 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 281         add     r0, r0, #CACHE_DLINESIZE
 282         cmp     r0, r1
 283         blo     1b
 284         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 285         mov     pc, lr
 286
 287 ENTRY(arm920_cache_fns)
 288         .long   arm920_flush_kern_cache_all
 289         .long   arm920_flush_user_cache_all
 290         .long   arm920_flush_user_cache_range
 291         .long   arm920_coherent_kern_range
 292         .long   arm920_coherent_user_range
 293         .long   arm920_flush_kern_dcache_page
 294         .long   arm920_dma_inv_range
 295         .long   arm920_dma_clean_range
 296         .long   arm920_dma_flush_range
 297
 298 #endif
 299
 300
 301 ENTRY(cpu_arm920_dcache_clean_area)
 302 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 303         add     r0, r0, #CACHE_DLINESIZE
 304         subs    r1, r1, #CACHE_DLINESIZE
 305         bhi     1b
 306         mov     pc, lr
 307
 308 /* =============================== PageTable ============================== */
 309
 310 /*
 311  * cpu_arm920_switch_mm(pgd)
 312  *
 313  * Set the translation base pointer to be as described by pgd.
 314  *
 315  * pgd: new page tables
 316  */
 317         .align  5
 318 ENTRY(cpu_arm920_switch_mm)
 319         mov     ip, #0
 320 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 321         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 322 #else
 323 @ && 'Clean & Invalidate whole DCache'
 324 @ && Re-written to use Index Ops.
 325 @ && Uses registers r1, r3 and ip
 326
 327         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
 328 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 329 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean & invalidate D index
 330         subs    r3, r3, #1 << 26
 331         bcs     2b                              @ entries 63 to 0
 332         subs    r1, r1, #1 << 5
 333         bcs     1b                              @ segments 7 to 0
 334 #endif
 335         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 336         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 337         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 338         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 339         mov     pc, lr
 340
 341 /*
 342  * cpu_arm920_set_pte(ptep, pte)
 343  *
 344  * Set a PTE and flush it out
 345  */
 346         .align  5
 347 ENTRY(cpu_arm920_set_pte)
 348         str     r1, [r0], #-2048                @ linux version
 349
 350         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 351
 352         bic     r2, r1, #PTE_SMALL_AP_MASK
 353         bic     r2, r2, #PTE_TYPE_MASK
 354         orr     r2, r2, #PTE_TYPE_SMALL
 355
 356         tst     r1, #L_PTE_USER                 @ User?
 357         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 358
 359         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 360         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 361
 362         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 363         movne   r2, #0
 364
 365 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 366         eor     r3, r2, #0x0a                   @ C & small page?
 367         tst     r3, #0x0b
 368         biceq   r2, r2, #4
 369 #endif
 370         str     r2, [r0]                        @ hardware version
 371         mov     r0, r0
 372         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 373         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 374         mov     pc, lr
 375
 376         __INIT
 377
 378         .type   __arm920_setup, #function
 379 __arm920_setup:
 380         mov     r0, #0
 381         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 382         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 383         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 384         mrc     p15, 0, r0, c1, c0              @ get control register v4
 385         ldr     r5, arm920_cr1_clear
 386         bic     r0, r0, r5
 387         ldr     r5, arm920_cr1_set
 388         orr     r0, r0, r5
 389         mov     pc, lr
 390         .size   __arm920_setup, . - __arm920_setup
 391
 392         /*
 393          *  R
 394          * .RVI ZFRS BLDP WCAM
 395          * ..11 0001 ..11 0101
 396          *
 397          */
 398         .type   arm920_cr1_clear, #object
 399         .type   arm920_cr1_set, #object
 400 arm920_cr1_clear:
 401         .word   0x3f3f
 402 arm920_cr1_set:
 403         .word   0x3135
 404
 405         __INITDATA
 406
 407 /*
 408  * Purpose : Function pointers used to access above functions - all calls
 409  *           come through these
 410  */
 411         .type   arm920_processor_functions, #object
 412 arm920_processor_functions:
 413         .word   v4t_early_abort
 414         .word   cpu_arm920_proc_init
 415         .word   cpu_arm920_proc_fin
 416         .word   cpu_arm920_reset
 417         .word   cpu_arm920_do_idle
 418         .word   cpu_arm920_dcache_clean_area
 419         .word   cpu_arm920_switch_mm
 420         .word   cpu_arm920_set_pte
 421         .size   arm920_processor_functions, . - arm920_processor_functions
 422
 423         .section ".rodata"
 424
 425         .type   cpu_arch_name, #object
 426 cpu_arch_name:
 427         .asciz  "armv4t"
 428         .size   cpu_arch_name, . - cpu_arch_name
 429
 430         .type   cpu_elf_name, #object
 431 cpu_elf_name:
 432         .asciz  "v4"
 433         .size   cpu_elf_name, . - cpu_elf_name
 434
 435         .type   cpu_arm920_name, #object
 436 cpu_arm920_name:
 437         .ascii  "ARM920T"
 438 #ifndef CONFIG_CPU_ICACHE_DISABLE
 439         .ascii  "i"
 440 #endif
 441 #ifndef CONFIG_CPU_DCACHE_DISABLE
 442         .ascii  "d"
 443 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 444         .ascii  "(wt)"
 445 #else
 446         .ascii  "(wb)"
 447 #endif
 448 #endif
 449         .ascii  "\0"
 450         .size   cpu_arm920_name, . - cpu_arm920_name
 451
 452         .align
 453
 454         .section ".proc.info.init", #alloc, #execinstr
 455
 456         .type   __arm920_proc_info,#object
 457 __arm920_proc_info:
 458         .long   0x41009200
 459         .long   0xff00fff0
 460         .long   PMD_TYPE_SECT | \
 461                 PMD_SECT_BUFFERABLE | \
 462                 PMD_SECT_CACHEABLE | \
 463                 PMD_BIT4 | \
 464                 PMD_SECT_AP_WRITE | \
 465                 PMD_SECT_AP_READ
 466         b       __arm920_setup
 467         .long   cpu_arch_name
 468         .long   cpu_elf_name
 469         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
 470         .long   cpu_arm920_name
 471         .long   arm920_processor_functions
 472         .long   v4wbi_tlb_fns
 473         .long   v4wb_user_fns
 474 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 475         .long   arm920_cache_fns
 476 #else
 477         .long   v4wt_cache_fns
 478 #endif
 479         .size   __arm920_proc_info, . - __arm920_proc_info