arch/arm/mm/proc-arm920.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
   3  *
   4  *  Copyright (C) 1999,2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22  *
  23  * These are the low level assembler for performing cache and TLB
  24  * functions on the arm920.
  25  *
  26  *  CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
  27  */
  28 #include <linux/linkage.h>
  29 #include <linux/config.h>
  30 #include <linux/init.h>
  31 #include <asm/assembler.h>
  32 #include <asm/pgtable-hwdef.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/procinfo.h>
  35 #include <asm/page.h>
  36 #include <asm/ptrace.h>
  37 #include "proc-macros.S"
  38
  39 /*
  40  * The size of one data cache line.
  41  */
  42 #define CACHE_DLINESIZE 32
  43
  44 /*
  45  * The number of data cache segments.
  46  */
  47 #define CACHE_DSEGMENTS 8
  48
  49 /*
  50  * The number of lines in a cache segment.
  51  */
  52 #define CACHE_DENTRIES  64
  53
  54 /*
  55  * This is the size at which it becomes more efficient to
  56  * clean the whole cache, rather than using the individual
  57  * cache line maintainence instructions.
  58  */
  59 #define CACHE_DLIMIT    65536
  60
  61
  62         .text
  63 /*
  64  * cpu_arm920_proc_init()
  65  */
  66 ENTRY(cpu_arm920_proc_init)
  67         mov     pc, lr
  68
  69 /*
  70  * cpu_arm920_proc_fin()
  71  */
  72 ENTRY(cpu_arm920_proc_fin)
  73         stmfd   sp!, {lr}
  74         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  75         msr     cpsr_c, ip
  76 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  77         bl      arm920_flush_kern_cache_all
  78 #else
  79         bl      v4wt_flush_kern_cache_all
  80 #endif
  81         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  82         bic     r0, r0, #0x1000                 @ ...i............
  83         bic     r0, r0, #0x000e                 @ ............wca.
  84         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  85         ldmfd   sp!, {pc}
  86
  87 /*
  88  * cpu_arm920_reset(loc)
  89  *
  90  * Perform a soft reset of the system.  Put the CPU into the
  91  * same state as it would be if it had been reset, and branch
  92  * to what would be the reset vector.
  93  *
  94  * loc: location to jump to for soft reset
  95  */
  96         .align  5
  97 ENTRY(cpu_arm920_reset)
  98         mov     ip, #0
  99         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
 100         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 101 #ifdef CONFIG_MMU
 102         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 103 #endif
 104         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
 105         bic     ip, ip, #0x000f                 @ ............wcam
 106         bic     ip, ip, #0x1100                 @ ...i...s........
 107         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 108         mov     pc, r0
 109
 110 /*
 111  * cpu_arm920_do_idle()
 112  */
 113         .align  5
 114 ENTRY(cpu_arm920_do_idle)
 115         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 116         mov     pc, lr
 117
 118
 119 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 120
 121 /*
 122  *      flush_user_cache_all()
 123  *
 124  *      Invalidate all cache entries in a particular address
 125  *      space.
 126  */
 127 ENTRY(arm920_flush_user_cache_all)
 128         /* FALLTHROUGH */
 129
 130 /*
 131  *      flush_kern_cache_all()
 132  *
 133  *      Clean and invalidate the entire cache.
 134  */
 135 ENTRY(arm920_flush_kern_cache_all)
 136         mov     r2, #VM_EXEC
 137         mov     ip, #0
 138 __flush_whole_cache:
 139         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
 140 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 141 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 142         subs    r3, r3, #1 << 26
 143         bcs     2b                              @ entries 63 to 0
 144         subs    r1, r1, #1 << 5
 145         bcs     1b                              @ segments 7 to 0
 146         tst     r2, #VM_EXEC
 147         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 148         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 149         mov     pc, lr
 150
 151 /*
 152  *      flush_user_cache_range(start, end, flags)
 153  *
 154  *      Invalidate a range of cache entries in the specified
 155  *      address space.
 156  *
 157  *      - start - start address (inclusive)
 158  *      - end   - end address (exclusive)
 159  *      - flags - vm_flags for address space
 160  */
 161 ENTRY(arm920_flush_user_cache_range)
 162         mov     ip, #0
 163         sub     r3, r1, r0                      @ calculate total size
 164         cmp     r3, #CACHE_DLIMIT
 165         bhs     __flush_whole_cache
 166
 167 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 168         tst     r2, #VM_EXEC
 169         mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
 170         add     r0, r0, #CACHE_DLINESIZE
 171         cmp     r0, r1
 172         blo     1b
 173         tst     r2, #VM_EXEC
 174         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 175         mov     pc, lr
 176
 177 /*
 178  *      coherent_kern_range(start, end)
 179  *
 180  *      Ensure coherency between the Icache and the Dcache in the
 181  *      region described by start, end.  If you have non-snooping
 182  *      Harvard caches, you need to implement this function.
 183  *
 184  *      - start - virtual start address
 185  *      - end   - virtual end address
 186  */
 187 ENTRY(arm920_coherent_kern_range)
 188         /* FALLTHROUGH */
 189
 190 /*
 191  *      coherent_user_range(start, end)
 192  *
 193  *      Ensure coherency between the Icache and the Dcache in the
 194  *      region described by start, end.  If you have non-snooping
 195  *      Harvard caches, you need to implement this function.
 196  *
 197  *      - start - virtual start address
 198  *      - end   - virtual end address
 199  */
 200 ENTRY(arm920_coherent_user_range)
 201         bic     r0, r0, #CACHE_DLINESIZE - 1
 202 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 203         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 204         add     r0, r0, #CACHE_DLINESIZE
 205         cmp     r0, r1
 206         blo     1b
 207         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 208         mov     pc, lr
 209
 210 /*
 211  *      flush_kern_dcache_page(void *page)
 212  *
 213  *      Ensure no D cache aliasing occurs, either with itself or
 214  *      the I cache
 215  *
 216  *      - addr  - page aligned address
 217  */
 218 ENTRY(arm920_flush_kern_dcache_page)
 219         add     r1, r0, #PAGE_SZ
 220 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 221         add     r0, r0, #CACHE_DLINESIZE
 222         cmp     r0, r1
 223         blo     1b
 224         mov     r0, #0
 225         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 226         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 227         mov     pc, lr
 228
 229 /*
 230  *      dma_inv_range(start, end)
 231  *
 232  *      Invalidate (discard) the specified virtual address range.
 233  *      May not write back any entries.  If 'start' or 'end'
 234  *      are not cache line aligned, those lines must be written
 235  *      back.
 236  *
 237  *      - start - virtual start address
 238  *      - end   - virtual end address
 239  *
 240  * (same as v4wb)
 241  */
 242 ENTRY(arm920_dma_inv_range)
 243         tst     r0, #CACHE_DLINESIZE - 1
 244         bic     r0, r0, #CACHE_DLINESIZE - 1
 245         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 246         tst     r1, #CACHE_DLINESIZE - 1
 247         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 248 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 249         add     r0, r0, #CACHE_DLINESIZE
 250         cmp     r0, r1
 251         blo     1b
 252         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 253         mov     pc, lr
 254
 255 /*
 256  *      dma_clean_range(start, end)
 257  *
 258  *      Clean the specified virtual address range.
 259  *
 260  *      - start - virtual start address
 261  *      - end   - virtual end address
 262  *
 263  * (same as v4wb)
 264  */
 265 ENTRY(arm920_dma_clean_range)
 266         bic     r0, r0, #CACHE_DLINESIZE - 1
 267 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 268         add     r0, r0, #CACHE_DLINESIZE
 269         cmp     r0, r1
 270         blo     1b
 271         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 272         mov     pc, lr
 273
 274 /*
 275  *      dma_flush_range(start, end)
 276  *
 277  *      Clean and invalidate the specified virtual address range.
 278  *
 279  *      - start - virtual start address
 280  *      - end   - virtual end address
 281  */
 282 ENTRY(arm920_dma_flush_range)
 283         bic     r0, r0, #CACHE_DLINESIZE - 1
 284 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 285         add     r0, r0, #CACHE_DLINESIZE
 286         cmp     r0, r1
 287         blo     1b
 288         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 289         mov     pc, lr
 290
 291 ENTRY(arm920_cache_fns)
 292         .long   arm920_flush_kern_cache_all
 293         .long   arm920_flush_user_cache_all
 294         .long   arm920_flush_user_cache_range
 295         .long   arm920_coherent_kern_range
 296         .long   arm920_coherent_user_range
 297         .long   arm920_flush_kern_dcache_page
 298         .long   arm920_dma_inv_range
 299         .long   arm920_dma_clean_range
 300         .long   arm920_dma_flush_range
 301
 302 #endif
 303
 304
 305 ENTRY(cpu_arm920_dcache_clean_area)
 306 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 307         add     r0, r0, #CACHE_DLINESIZE
 308         subs    r1, r1, #CACHE_DLINESIZE
 309         bhi     1b
 310         mov     pc, lr
 311
 312 /* =============================== PageTable ============================== */
 313
 314 /*
 315  * cpu_arm920_switch_mm(pgd)
 316  *
 317  * Set the translation base pointer to be as described by pgd.
 318  *
 319  * pgd: new page tables
 320  */
 321         .align  5
 322 ENTRY(cpu_arm920_switch_mm)
 323 #ifdef CONFIG_MMU
 324         mov     ip, #0
 325 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 326         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 327 #else
 328 @ && 'Clean & Invalidate whole DCache'
 329 @ && Re-written to use Index Ops.
 330 @ && Uses registers r1, r3 and ip
 331
 332         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
 333 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 334 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean & invalidate D index
 335         subs    r3, r3, #1 << 26
 336         bcs     2b                              @ entries 63 to 0
 337         subs    r1, r1, #1 << 5
 338         bcs     1b                              @ segments 7 to 0
 339 #endif
 340         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 341         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 342         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 343         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 344 #endif
 345         mov     pc, lr
 346
 347 /*
 348  * cpu_arm920_set_pte(ptep, pte)
 349  *
 350  * Set a PTE and flush it out
 351  */
 352         .align  5
 353 ENTRY(cpu_arm920_set_pte)
 354 #ifdef CONFIG_MMU
 355         str     r1, [r0], #-2048                @ linux version
 356
 357         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 358
 359         bic     r2, r1, #PTE_SMALL_AP_MASK
 360         bic     r2, r2, #PTE_TYPE_MASK
 361         orr     r2, r2, #PTE_TYPE_SMALL
 362
 363         tst     r1, #L_PTE_USER                 @ User?
 364         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 365
 366         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 367         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 368
 369         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 370         movne   r2, #0
 371
 372 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 373         eor     r3, r2, #0x0a                   @ C & small page?
 374         tst     r3, #0x0b
 375         biceq   r2, r2, #4
 376 #endif
 377         str     r2, [r0]                        @ hardware version
 378         mov     r0, r0
 379         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 380         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 381 #endif /* CONFIG_MMU */
 382         mov     pc, lr
 383
 384         __INIT
 385
 386         .type   __arm920_setup, #function
 387 __arm920_setup:
 388         mov     r0, #0
 389         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 390         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 391 #ifdef CONFIG_MMU
 392         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 393 #endif
 394         mrc     p15, 0, r0, c1, c0              @ get control register v4
 395         ldr     r5, arm920_cr1_clear
 396         bic     r0, r0, r5
 397         ldr     r5, arm920_cr1_set
 398         orr     r0, r0, r5
 399         mov     pc, lr
 400         .size   __arm920_setup, . - __arm920_setup
 401
 402         /*
 403          *  R
 404          * .RVI ZFRS BLDP WCAM
 405          * ..11 0001 ..11 0101
 406          *
 407          */
 408         .type   arm920_cr1_clear, #object
 409         .type   arm920_cr1_set, #object
 410 arm920_cr1_clear:
 411         .word   0x3f3f
 412 arm920_cr1_set:
 413         .word   0x3135
 414
 415         __INITDATA
 416
 417 /*
 418  * Purpose : Function pointers used to access above functions - all calls
 419  *           come through these
 420  */
 421         .type   arm920_processor_functions, #object
 422 arm920_processor_functions:
 423         .word   v4t_early_abort
 424         .word   cpu_arm920_proc_init
 425         .word   cpu_arm920_proc_fin
 426         .word   cpu_arm920_reset
 427         .word   cpu_arm920_do_idle
 428         .word   cpu_arm920_dcache_clean_area
 429         .word   cpu_arm920_switch_mm
 430         .word   cpu_arm920_set_pte
 431         .size   arm920_processor_functions, . - arm920_processor_functions
 432
 433         .section ".rodata"
 434
 435         .type   cpu_arch_name, #object
 436 cpu_arch_name:
 437         .asciz  "armv4t"
 438         .size   cpu_arch_name, . - cpu_arch_name
 439
 440         .type   cpu_elf_name, #object
 441 cpu_elf_name:
 442         .asciz  "v4"
 443         .size   cpu_elf_name, . - cpu_elf_name
 444
 445         .type   cpu_arm920_name, #object
 446 cpu_arm920_name:
 447         .ascii  "ARM920T"
 448 #ifndef CONFIG_CPU_ICACHE_DISABLE
 449         .ascii  "i"
 450 #endif
 451 #ifndef CONFIG_CPU_DCACHE_DISABLE
 452         .ascii  "d"
 453 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 454         .ascii  "(wt)"
 455 #else
 456         .ascii  "(wb)"
 457 #endif
 458 #endif
 459         .ascii  "\0"
 460         .size   cpu_arm920_name, . - cpu_arm920_name
 461
 462         .align
 463
 464         .section ".proc.info.init", #alloc, #execinstr
 465
 466         .type   __arm920_proc_info,#object
 467 __arm920_proc_info:
 468         .long   0x41009200
 469         .long   0xff00fff0
 470         .long   PMD_TYPE_SECT | \
 471                 PMD_SECT_BUFFERABLE | \
 472                 PMD_SECT_CACHEABLE | \
 473                 PMD_BIT4 | \
 474                 PMD_SECT_AP_WRITE | \
 475                 PMD_SECT_AP_READ
 476         b       __arm920_setup
 477         .long   cpu_arch_name
 478         .long   cpu_elf_name
 479         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
 480         .long   cpu_arm920_name
 481         .long   arm920_processor_functions
 482         .long   v4wbi_tlb_fns
 483         .long   v4wb_user_fns
 484 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 485         .long   arm920_cache_fns
 486 #else
 487         .long   v4wt_cache_fns
 488 #endif
 489         .size   __arm920_proc_info, . - __arm920_proc_info