arch/arm/mm/proc-fa526.S

   1 /*
   2  *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
   3  *
   4  *  Written by : Luke Lee
   5  *  Copyright (C) 2005 Faraday Corp.
   6  *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  *
  14  * These are the low level assembler for performing cache and TLB
  15  * functions on the fa526.
  16  */
  17 #include <linux/linkage.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/hwcap.h>
  21 #include <asm/pgtable-hwdef.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/page.h>
  24 #include <asm/ptrace.h>
  25
  26 #include "proc-macros.S"
  27
  28 #define CACHE_DLINESIZE 16
  29
  30         .text
  31 /*
  32  * cpu_fa526_proc_init()
  33  */
  34 ENTRY(cpu_fa526_proc_init)
  35         mov     pc, lr
  36
  37 /*
  38  * cpu_fa526_proc_fin()
  39  */
  40 ENTRY(cpu_fa526_proc_fin)
  41         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  42         bic     r0, r0, #0x1000                 @ ...i............
  43         bic     r0, r0, #0x000e                 @ ............wca.
  44         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  45         nop
  46         nop
  47         mov     pc, lr
  48
  49 /*
  50  * cpu_fa526_reset(loc)
  51  *
  52  * Perform a soft reset of the system.  Put the CPU into the
  53  * same state as it would be if it had been reset, and branch
  54  * to what would be the reset vector.
  55  *
  56  * loc: location to jump to for soft reset
  57  */
  58         .align  4
  59         .pushsection    .idmap.text, "ax"
  60 ENTRY(cpu_fa526_reset)
  61 /* TODO: Use CP8 if possible... */
  62         mov     ip, #0
  63         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  64         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  65 #ifdef CONFIG_MMU
  66         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  67 #endif
  68         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  69         bic     ip, ip, #0x000f                 @ ............wcam
  70         bic     ip, ip, #0x1100                 @ ...i...s........
  71         bic     ip, ip, #0x0800                 @ BTB off
  72         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  73         nop
  74         nop
  75         mov     pc, r0
  76 ENDPROC(cpu_fa526_reset)
  77         .popsection
  78
  79 /*
  80  * cpu_fa526_do_idle()
  81  */
  82         .align  4
  83 ENTRY(cpu_fa526_do_idle)
  84         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
  85         mov     pc, lr
  86
  87
  88 ENTRY(cpu_fa526_dcache_clean_area)
  89 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  90         add     r0, r0, #CACHE_DLINESIZE
  91         subs    r1, r1, #CACHE_DLINESIZE
  92         bhi     1b
  93         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
  94         mov     pc, lr
  95
  96 /* =============================== PageTable ============================== */
  97
  98 /*
  99  * cpu_fa526_switch_mm(pgd)
 100  *
 101  * Set the translation base pointer to be as described by pgd.
 102  *
 103  * pgd: new page tables
 104  */
 105         .align  4
 106 ENTRY(cpu_fa526_switch_mm)
 107 #ifdef CONFIG_MMU
 108         mov     ip, #0
 109 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 110         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 111 #else
 112         mcr     p15, 0, ip, c7, c14, 0          @ clean and invalidate whole D cache
 113 #endif
 114         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 115         mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB since mm changed
 116         mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
 117         mcr     p15, 0, ip, c7, c5, 4           @ prefetch flush
 118         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 119         mcr     p15, 0, ip, c8, c7, 0           @ invalidate UTLB
 120 #endif
 121         mov     pc, lr
 122
 123 /*
 124  * cpu_fa526_set_pte_ext(ptep, pte, ext)
 125  *
 126  * Set a PTE and flush it out
 127  */
 128         .align  4
 129 ENTRY(cpu_fa526_set_pte_ext)
 130 #ifdef CONFIG_MMU
 131         armv3_set_pte_ext
 132         mov     r0, r0
 133         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 134         mov     r0, #0
 135         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 136 #endif
 137         mov     pc, lr
 138
 139         __CPUINIT
 140
 141         .type   __fa526_setup, #function
 142 __fa526_setup:
 143         /* On return of this routine, r0 must carry correct flags for CFG register */
 144         mov     r0, #0
 145         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 146         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 147 #ifdef CONFIG_MMU
 148         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 149 #endif
 150         mcr     p15, 0, r0, c7, c5, 5           @ invalidate IScratchpad RAM
 151
 152         mov     r0, #1
 153         mcr     p15, 0, r0, c1, c1, 0           @ turn-on ECR
 154
 155         mov     r0, #0
 156         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB All
 157         mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
 158         mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
 159
 160         mov     r0, #0x1f                       @ Domains 0, 1 = manager, 2 = client
 161         mcr     p15, 0, r0, c3, c0              @ load domain access register
 162
 163         mrc     p15, 0, r0, c1, c0              @ get control register v4
 164         ldr     r5, fa526_cr1_clear
 165         bic     r0, r0, r5
 166         ldr     r5, fa526_cr1_set
 167         orr     r0, r0, r5
 168         mov     pc, lr
 169         .size   __fa526_setup, . - __fa526_setup
 170
 171         /*
 172          * .RVI ZFRS BLDP WCAM
 173          * ..11 1001 .111 1101
 174          *
 175          */
 176         .type   fa526_cr1_clear, #object
 177         .type   fa526_cr1_set, #object
 178 fa526_cr1_clear:
 179         .word   0x3f3f
 180 fa526_cr1_set:
 181         .word   0x397D
 182
 183         __INITDATA
 184
 185         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 186         define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
 187
 188         .section ".rodata"
 189
 190         string  cpu_arch_name, "armv4"
 191         string  cpu_elf_name, "v4"
 192         string  cpu_fa526_name, "FA526"
 193
 194         .align
 195
 196         .section ".proc.info.init", #alloc, #execinstr
 197
 198         .type   __fa526_proc_info,#object
 199 __fa526_proc_info:
 200         .long   0x66015261
 201         .long   0xff01fff1
 202         .long   PMD_TYPE_SECT | \
 203                 PMD_SECT_BUFFERABLE | \
 204                 PMD_SECT_CACHEABLE | \
 205                 PMD_BIT4 | \
 206                 PMD_SECT_AP_WRITE | \
 207                 PMD_SECT_AP_READ
 208         .long   PMD_TYPE_SECT | \
 209                 PMD_BIT4 | \
 210                 PMD_SECT_AP_WRITE | \
 211                 PMD_SECT_AP_READ
 212         b       __fa526_setup
 213         .long   cpu_arch_name
 214         .long   cpu_elf_name
 215         .long   HWCAP_SWP | HWCAP_HALF
 216         .long   cpu_fa526_name
 217         .long   fa526_processor_functions
 218         .long   fa_tlb_fns
 219         .long   fa_user_fns
 220         .long   fa_cache_fns
 221         .size   __fa526_proc_info, . - __fa526_proc_info