arch/arm/mm/proc-macros.S

   1 /*
   2  * We need constants.h for:
   3  *  VMA_VM_MM
   4  *  VMA_VM_FLAGS
   5  *  VM_EXEC
   6  */
   7 #include <asm/asm-offsets.h>
   8 #include <asm/thread_info.h>
   9
  10 /*
  11  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
  12  */
  13         .macro  vma_vm_mm, rd, rn
  14         ldr     \rd, [\rn, #VMA_VM_MM]
  15         .endm
  16
  17 /*
  18  * vma_vm_flags - get vma->vm_flags
  19  */
  20         .macro  vma_vm_flags, rd, rn
  21         ldr     \rd, [\rn, #VMA_VM_FLAGS]
  22         .endm
  23
  24         .macro  tsk_mm, rd, rn
  25         ldr     \rd, [\rn, #TI_TASK]
  26         ldr     \rd, [\rd, #TSK_ACTIVE_MM]
  27         .endm
  28
  29 /*
  30  * act_mm - get current->active_mm
  31  */
  32         .macro  act_mm, rd
  33         bic     \rd, sp, #8128
  34         bic     \rd, \rd, #63
  35         ldr     \rd, [\rd, #TI_TASK]
  36         ldr     \rd, [\rd, #TSK_ACTIVE_MM]
  37         .endm
  38
  39 /*
  40  * mmid - get context id from mm pointer (mm->context.id)
  41  */
  42         .macro  mmid, rd, rn
  43         ldr     \rd, [\rn, #MM_CONTEXT_ID]
  44         .endm
  45
  46 /*
  47  * mask_asid - mask the ASID from the context ID
  48  */
  49         .macro  asid, rd, rn
  50         and     \rd, \rn, #255
  51         .endm
  52
  53         .macro  crval, clear, mmuset, ucset
  54 #ifdef CONFIG_MMU
  55         .word   \clear
  56         .word   \mmuset
  57 #else
  58         .word   \clear
  59         .word   \ucset
  60 #endif
  61         .endm
  62
  63 /*
  64  * dcache_line_size - get the minimum D-cache line size from the CTR register
  65  * on ARMv7.
  66  */
  67         .macro  dcache_line_size, reg, tmp
  68         mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
  69         lsr     \tmp, \tmp, #16
  70         and     \tmp, \tmp, #0xf                @ cache line size encoding
  71         mov     \reg, #4                        @ bytes per word
  72         mov     \reg, \reg, lsl \tmp            @ actual cache line size
  73         .endm
  74
  75 /*
  76  * icache_line_size - get the minimum I-cache line size from the CTR register
  77  * on ARMv7.
  78  */
  79         .macro  icache_line_size, reg, tmp
  80         mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
  81         and     \tmp, \tmp, #0xf                @ cache line size encoding
  82         mov     \reg, #4                        @ bytes per word
  83         mov     \reg, \reg, lsl \tmp            @ actual cache line size
  84         .endm
  85
  86 /*
  87  * Sanity check the PTE configuration for the code below - which makes
  88  * certain assumptions about how these bits are laid out.
  89  */
  90 #ifdef CONFIG_MMU
  91 #if L_PTE_SHARED != PTE_EXT_SHARED
  92 #error PTE shared bit mismatch
  93 #endif
  94 #if !defined (CONFIG_ARM_LPAE) && \
  95         (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
  96          L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
  97 #error Invalid Linux PTE bit settings
  98 #endif
  99 #endif  /* CONFIG_MMU */
 100
 101 /*
 102  * The ARMv6 and ARMv7 set_pte_ext translation function.
 103  *
 104  * Permission translation:
 105  *  YUWD  APX AP1 AP0   SVC     User
 106  *  0xxx   0   0   0    no acc  no acc
 107  *  100x   1   0   1    r/o     no acc
 108  *  10x0   1   0   1    r/o     no acc
 109  *  1011   0   0   1    r/w     no acc
 110  *  110x   0   1   0    r/w     r/o
 111  *  11x0   0   1   0    r/w     r/o
 112  *  1111   0   1   1    r/w     r/w
 113  *
 114  * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
 115  *  110x   1   1   1    r/o     r/o
 116  *  11x0   1   1   1    r/o     r/o
 117  */
 118         .macro  armv6_mt_table pfx
 119 \pfx\()_mt_table:
 120         .long   0x00                                            @ L_PTE_MT_UNCACHED
 121         .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
 122         .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
 123         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
 124         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_SHARED
 125         .long   0x00                                            @ unused
 126         .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
 127         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
 128         .long   0x00                                            @ unused
 129         .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_DEV_WC
 130         .long   0x00                                            @ unused
 131         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
 132         .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
 133         .long   0x00                                            @ unused
 134         .long   0x00                                            @ unused
 135         .long   0x00                                            @ unused
 136         .endm
 137
 138         .macro  armv6_set_pte_ext pfx
 139         str     r1, [r0], #2048                 @ linux version
 140
 141         bic     r3, r1, #0x000003fc
 142         bic     r3, r3, #PTE_TYPE_MASK
 143         orr     r3, r3, r2
 144         orr     r3, r3, #PTE_EXT_AP0 | 2
 145
 146         adr     ip, \pfx\()_mt_table
 147         and     r2, r1, #L_PTE_MT_MASK
 148         ldr     r2, [ip, r2]
 149
 150         eor     r1, r1, #L_PTE_DIRTY
 151         tst     r1, #L_PTE_DIRTY|L_PTE_RDONLY
 152         orrne   r3, r3, #PTE_EXT_APX
 153
 154         tst     r1, #L_PTE_USER
 155         orrne   r3, r3, #PTE_EXT_AP1
 156 #ifdef CONFIG_CPU_USE_DOMAINS
 157         @ allow kernel read/write access to read-only user pages
 158         tstne   r3, #PTE_EXT_APX
 159         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 160 #endif
 161
 162         tst     r1, #L_PTE_XN
 163         orrne   r3, r3, #PTE_EXT_XN
 164
 165         orr     r3, r3, r2
 166
 167         tst     r1, #L_PTE_YOUNG
 168         tstne   r1, #L_PTE_PRESENT
 169         moveq   r3, #0
 170
 171         str     r3, [r0]
 172         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 173         .endm
 174
 175
 176 /*
 177  * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
 178  * covering most CPUs except Xscale and Xscale 3.
 179  *
 180  * Permission translation:
 181  *  YUWD   AP   SVC     User
 182  *  0xxx  0x00  no acc  no acc
 183  *  100x  0x00  r/o     no acc
 184  *  10x0  0x00  r/o     no acc
 185  *  1011  0x55  r/w     no acc
 186  *  110x  0xaa  r/w     r/o
 187  *  11x0  0xaa  r/w     r/o
 188  *  1111  0xff  r/w     r/w
 189  */
 190         .macro  armv3_set_pte_ext wc_disable=1
 191         str     r1, [r0], #2048                 @ linux version
 192
 193         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 194
 195         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
 196         bic     r2, r2, #PTE_TYPE_MASK
 197         orr     r2, r2, #PTE_TYPE_SMALL
 198
 199         tst     r3, #L_PTE_USER                 @ user?
 200         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 201
 202         tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
 203         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 204
 205         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
 206         movne   r2, #0
 207
 208         .if     \wc_disable
 209 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 210         tst     r2, #PTE_CACHEABLE
 211         bicne   r2, r2, #PTE_BUFFERABLE
 212 #endif
 213         .endif
 214         str     r2, [r0]                @ hardware version
 215         .endm
 216
 217
 218 /*
 219  * Xscale set_pte_ext translation, split into two halves to cope
 220  * with work-arounds.  r3 must be preserved by code between these
 221  * two macros.
 222  *
 223  * Permission translation:
 224  *  YUWD  AP    SVC     User
 225  *  0xxx  00    no acc  no acc
 226  *  100x  00    r/o     no acc
 227  *  10x0  00    r/o     no acc
 228  *  1011  01    r/w     no acc
 229  *  110x  10    r/w     r/o
 230  *  11x0  10    r/w     r/o
 231  *  1111  11    r/w     r/w
 232  */
 233         .macro  xscale_set_pte_ext_prologue
 234         str     r1, [r0]                        @ linux version
 235
 236         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 237
 238         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
 239         orr     r2, r2, #PTE_TYPE_EXT           @ extended page
 240
 241         tst     r3, #L_PTE_USER                 @ user?
 242         orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
 243
 244         tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
 245         orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
 246                                                 @ combined with user -> user r/w
 247         .endm
 248
 249         .macro  xscale_set_pte_ext_epilogue
 250         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
 251         movne   r2, #0                          @ no -> fault
 252
 253         str     r2, [r0, #2048]!                @ hardware version
 254         mov     ip, #0
 255         mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
 256         mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
 257         .endm
 258
 259 .macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
 260         .type   \name\()_processor_functions, #object
 261         .align 2
 262 ENTRY(\name\()_processor_functions)
 263         .word   \dabort
 264         .word   \pabort
 265         .word   cpu_\name\()_proc_init
 266         .word   cpu_\name\()_proc_fin
 267         .word   cpu_\name\()_reset
 268         .word   cpu_\name\()_do_idle
 269         .word   cpu_\name\()_dcache_clean_area
 270         .word   cpu_\name\()_switch_mm
 271
 272         .if \nommu
 273         .word   0
 274         .else
 275         .word   cpu_\name\()_set_pte_ext
 276         .endif
 277
 278         .if \suspend
 279         .word   cpu_\name\()_suspend_size
 280 #ifdef CONFIG_PM_SLEEP
 281         .word   cpu_\name\()_do_suspend
 282         .word   cpu_\name\()_do_resume
 283 #else
 284         .word   0
 285         .word   0
 286 #endif
 287         .else
 288         .word   0
 289         .word   0
 290         .word   0
 291         .endif
 292
 293         .size   \name\()_processor_functions, . - \name\()_processor_functions
 294 .endm
 295
 296 .macro define_cache_functions name:req
 297         .align 2
 298         .type   \name\()_cache_fns, #object
 299 ENTRY(\name\()_cache_fns)
 300         .long   \name\()_flush_icache_all
 301         .long   \name\()_flush_kern_cache_all
 302         .long   \name\()_flush_user_cache_all
 303         .long   \name\()_flush_user_cache_range
 304         .long   \name\()_coherent_kern_range
 305         .long   \name\()_coherent_user_range
 306         .long   \name\()_flush_kern_dcache_area
 307         .long   \name\()_dma_map_area
 308         .long   \name\()_dma_unmap_area
 309         .long   \name\()_dma_flush_range
 310         .size   \name\()_cache_fns, . - \name\()_cache_fns
 311 .endm
 312
 313 .macro define_tlb_functions name:req, flags_up:req, flags_smp
 314         .type   \name\()_tlb_fns, #object
 315 ENTRY(\name\()_tlb_fns)
 316         .long   \name\()_flush_user_tlb_range
 317         .long   \name\()_flush_kern_tlb_range
 318         .ifnb \flags_smp
 319                 ALT_SMP(.long   \flags_smp )
 320                 ALT_UP(.long    \flags_up )
 321         .else
 322                 .long   \flags_up
 323         .endif
 324         .size   \name\()_tlb_fns, . - \name\()_tlb_fns
 325 .endm