arch/arm/mm/proc-v6.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *  Modified by Catalin Marinas for noMMU support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv6 processor support.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/linkage.h>
  15 #include <asm/assembler.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/hwcap.h>
  18 #include <asm/pgtable-hwdef.h>
  19 #include <asm/pgtable.h>
  20
  21 #include "proc-macros.S"
  22
  23 #define D_CACHE_LINE_SIZE       32
  24
  25 #define TTB_C           (1 << 0)
  26 #define TTB_S           (1 << 1)
  27 #define TTB_IMP         (1 << 2)
  28 #define TTB_RGN_NC      (0 << 3)
  29 #define TTB_RGN_WBWA    (1 << 3)
  30 #define TTB_RGN_WT      (2 << 3)
  31 #define TTB_RGN_WB      (3 << 3)
  32
  33 #define TTB_FLAGS_UP    TTB_RGN_WBWA
  34 #define PMD_FLAGS_UP    PMD_SECT_WB
  35 #define TTB_FLAGS_SMP   TTB_RGN_WBWA|TTB_S
  36 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
  37
  38 ENTRY(cpu_v6_proc_init)
  39         mov     pc, lr
  40
  41 ENTRY(cpu_v6_proc_fin)
  42         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  43         bic     r0, r0, #0x1000                 @ ...i............
  44         bic     r0, r0, #0x0006                 @ .............ca.
  45         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  46         mov     pc, lr
  47
  48 /*
  49  *      cpu_v6_reset(loc)
  50  *
  51  *      Perform a soft reset of the system.  Put the CPU into the
  52  *      same state as it would be if it had been reset, and branch
  53  *      to what would be the reset vector.
  54  *
  55  *      - loc   - location to jump to for soft reset
  56  */
  57         .align  5
  58         .pushsection    .idmap.text, "ax"
  59 ENTRY(cpu_v6_reset)
  60         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  61         bic     r1, r1, #0x1                    @ ...............m
  62         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  63         mov     r1, #0
  64         mcr     p15, 0, r1, c7, c5, 4           @ ISB
  65         mov     pc, r0
  66 ENDPROC(cpu_v6_reset)
  67         .popsection
  68
  69 /*
  70  *      cpu_v6_do_idle()
  71  *
  72  *      Idle the processor (eg, wait for interrupt).
  73  *
  74  *      IRQs are already disabled.
  75  */
  76 ENTRY(cpu_v6_do_idle)
  77         mov     r1, #0
  78         mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
  79         mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
  80         mov     pc, lr
  81
  82 ENTRY(cpu_v6_dcache_clean_area)
  83 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  84         add     r0, r0, #D_CACHE_LINE_SIZE
  85         subs    r1, r1, #D_CACHE_LINE_SIZE
  86         bhi     1b
  87         mov     pc, lr
  88
  89 /*
  90  *      cpu_v6_switch_mm(pgd_phys, tsk)
  91  *
  92  *      Set the translation table base pointer to be pgd_phys
  93  *
  94  *      - pgd_phys - physical address of new TTB
  95  *
  96  *      It is assumed that:
  97  *      - we are not using split page tables
  98  */
  99 ENTRY(cpu_v6_switch_mm)
 100 #ifdef CONFIG_MMU
 101         mov     r2, #0
 102         mmid    r1, r1                          @ get mm->context.id
 103         ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
 104         ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 105         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 106         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
 107         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 108 #ifdef CONFIG_PID_IN_CONTEXTIDR
 109         mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
 110         bic     r2, r2, #0xff                   @ extract the PID
 111         and     r1, r1, #0xff
 112         orr     r1, r1, r2                      @ insert into new context ID
 113 #endif
 114         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 115 #endif
 116         mov     pc, lr
 117
 118 /*
 119  *      cpu_v6_set_pte_ext(ptep, pte, ext)
 120  *
 121  *      Set a level 2 translation table entry.
 122  *
 123  *      - ptep  - pointer to level 2 translation table entry
 124  *                (hardware version is stored at -1024 bytes)
 125  *      - pte   - PTE value to store
 126  *      - ext   - value for extended PTE bits
 127  */
 128         armv6_mt_table cpu_v6
 129
 130 ENTRY(cpu_v6_set_pte_ext)
 131 #ifdef CONFIG_MMU
 132         armv6_set_pte_ext cpu_v6
 133 #endif
 134         mov     pc, lr
 135
 136 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 137 .globl  cpu_v6_suspend_size
 138 .equ    cpu_v6_suspend_size, 4 * 6
 139 #ifdef CONFIG_ARM_CPU_SUSPEND
 140 ENTRY(cpu_v6_do_suspend)
 141         stmfd   sp!, {r4 - r9, lr}
 142         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 143 #ifdef CONFIG_MMU
 144         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
 145         mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
 146 #endif
 147         mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
 148         mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
 149         mrc     p15, 0, r9, c1, c0, 0   @ control register
 150         stmia   r0, {r4 - r9}
 151         ldmfd   sp!, {r4- r9, pc}
 152 ENDPROC(cpu_v6_do_suspend)
 153
 154 ENTRY(cpu_v6_do_resume)
 155         mov     ip, #0
 156         mcr     p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
 157         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 158         mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
 159         mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
 160         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 161         ldmia   r0, {r4 - r9}
 162         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 163 #ifdef CONFIG_MMU
 164         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
 165         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 166         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 167         mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
 168         mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
 169         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
 170 #endif
 171         mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
 172         mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
 173         mcr     p15, 0, ip, c7, c5, 4   @ ISB
 174         mov     r0, r9                  @ control register
 175         b       cpu_resume_mmu
 176 ENDPROC(cpu_v6_do_resume)
 177 #endif
 178
 179         string  cpu_v6_name, "ARMv6-compatible processor"
 180
 181         .align
 182
 183         __CPUINIT
 184
 185 /*
 186  *      __v6_setup
 187  *
 188  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 189  *      on.  Return in r0 the new CP15 C1 control register setting.
 190  *
 191  *      We automatically detect if we have a Harvard cache, and use the
 192  *      Harvard cache control instructions insead of the unified cache
 193  *      control instructions.
 194  *
 195  *      This should be able to cover all ARMv6 cores.
 196  *
 197  *      It is assumed that:
 198  *      - cache type register is implemented
 199  */
 200 __v6_setup:
 201 #ifdef CONFIG_SMP
 202         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)  @ Enable SMP/nAMP mode
 203         ALT_UP(nop)
 204         orr     r0, r0, #0x20
 205         ALT_SMP(mcr     p15, 0, r0, c1, c0, 1)
 206         ALT_UP(nop)
 207 #endif
 208
 209         mov     r0, #0
 210         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
 211         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 212         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
 213         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 214 #ifdef CONFIG_MMU
 215         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
 216         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
 217         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
 218         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
 219         ALT_SMP(orr     r8, r8, #TTB_FLAGS_SMP)
 220         ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
 221         mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
 222 #endif /* CONFIG_MMU */
 223         adr     r5, v6_crval
 224         ldmia   r5, {r5, r6}
 225 #ifdef CONFIG_CPU_ENDIAN_BE8
 226         orr     r6, r6, #1 << 25                @ big-endian page tables
 227 #endif
 228         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 229         bic     r0, r0, r5                      @ clear bits them
 230         orr     r0, r0, r6                      @ set them
 231 #ifdef CONFIG_ARM_ERRATA_364296
 232         /*
 233          * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
 234          * corruption with hit-under-miss enabled). The conditional code below
 235          * (setting the undocumented bit 31 in the auxiliary control register
 236          * and the FI bit in the control register) disables hit-under-miss
 237          * without putting the processor into full low interrupt latency mode.
 238          */
 239         ldr     r6, =0x4107b362                 @ id for ARM1136 r0p2
 240         mrc     p15, 0, r5, c0, c0, 0           @ get processor id
 241         teq     r5, r6                          @ check for the faulty core
 242         mrceq   p15, 0, r5, c1, c0, 1           @ load aux control reg
 243         orreq   r5, r5, #(1 << 31)              @ set the undocumented bit 31
 244         mcreq   p15, 0, r5, c1, c0, 1           @ write aux control reg
 245         orreq   r0, r0, #(1 << 21)              @ low interrupt latency configuration
 246 #endif
 247         mov     pc, lr                          @ return to head.S:__ret
 248
 249         /*
 250          *         V X F   I D LR
 251          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 252          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 253          *         0 110       0011 1.00 .111 1101 < we want
 254          */
 255         .type   v6_crval, #object
 256 v6_crval:
 257         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 258
 259         __INITDATA
 260
 261         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 262         define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
 263
 264         .section ".rodata"
 265
 266         string  cpu_arch_name, "armv6"
 267         string  cpu_elf_name, "v6"
 268         .align
 269
 270         .section ".proc.info.init", #alloc, #execinstr
 271
 272         /*
 273          * Match any ARMv6 processor core.
 274          */
 275         .type   __v6_proc_info, #object
 276 __v6_proc_info:
 277         .long   0x0007b000
 278         .long   0x0007f000
 279         ALT_SMP(.long \
 280                 PMD_TYPE_SECT | \
 281                 PMD_SECT_AP_WRITE | \
 282                 PMD_SECT_AP_READ | \
 283                 PMD_FLAGS_SMP)
 284         ALT_UP(.long \
 285                 PMD_TYPE_SECT | \
 286                 PMD_SECT_AP_WRITE | \
 287                 PMD_SECT_AP_READ | \
 288                 PMD_FLAGS_UP)
 289         .long   PMD_TYPE_SECT | \
 290                 PMD_SECT_XN | \
 291                 PMD_SECT_AP_WRITE | \
 292                 PMD_SECT_AP_READ
 293         b       __v6_setup
 294         .long   cpu_arch_name
 295         .long   cpu_elf_name
 296         /* See also feat_v6_fixup() for HWCAP_TLS */
 297         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
 298         .long   cpu_v6_name
 299         .long   v6_processor_functions
 300         .long   v6wbi_tlb_fns
 301         .long   v6_user_fns
 302         .long   v6_cache_fns
 303         .size   __v6_proc_info, . - __v6_proc_info