arch/arm/mm/proc-v6.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v6.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *  Modified by Catalin Marinas for noMMU support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv6 processor support.
  12  */
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/elf.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19
  20 #include "proc-macros.S"
  21
  22 #define D_CACHE_LINE_SIZE       32
  23
  24 #define TTB_C           (1 << 0)
  25 #define TTB_S           (1 << 1)
  26 #define TTB_IMP         (1 << 2)
  27 #define TTB_RGN_NC      (0 << 3)
  28 #define TTB_RGN_WBWA    (1 << 3)
  29 #define TTB_RGN_WT      (2 << 3)
  30 #define TTB_RGN_WB      (3 << 3)
  31
  32 #ifndef CONFIG_SMP
  33 #define TTB_FLAGS       TTB_RGN_WBWA
  34 #else
  35 #define TTB_FLAGS       TTB_RGN_WBWA|TTB_S
  36 #endif
  37
  38 ENTRY(cpu_v6_proc_init)
  39         mov     pc, lr
  40
  41 ENTRY(cpu_v6_proc_fin)
  42         stmfd   sp!, {lr}
  43         cpsid   if                              @ disable interrupts
  44         bl      v6_flush_kern_cache_all
  45         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  46         bic     r0, r0, #0x1000                 @ ...i............
  47         bic     r0, r0, #0x0006                 @ .............ca.
  48         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  49         ldmfd   sp!, {pc}
  50
  51 /*
  52  *      cpu_v6_reset(loc)
  53  *
  54  *      Perform a soft reset of the system.  Put the CPU into the
  55  *      same state as it would be if it had been reset, and branch
  56  *      to what would be the reset vector.
  57  *
  58  *      - loc   - location to jump to for soft reset
  59  *
  60  *      It is assumed that:
  61  */
  62         .align  5
  63 ENTRY(cpu_v6_reset)
  64         mov     pc, r0
  65
  66 /*
  67  *      cpu_v6_do_idle()
  68  *
  69  *      Idle the processor (eg, wait for interrupt).
  70  *
  71  *      IRQs are already disabled.
  72  */
  73 ENTRY(cpu_v6_do_idle)
  74         mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
  75         mov     pc, lr
  76
  77 ENTRY(cpu_v6_dcache_clean_area)
  78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
  79 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  80         add     r0, r0, #D_CACHE_LINE_SIZE
  81         subs    r1, r1, #D_CACHE_LINE_SIZE
  82         bhi     1b
  83 #endif
  84         mov     pc, lr
  85
  86 /*
  87  *      cpu_arm926_switch_mm(pgd_phys, tsk)
  88  *
  89  *      Set the translation table base pointer to be pgd_phys
  90  *
  91  *      - pgd_phys - physical address of new TTB
  92  *
  93  *      It is assumed that:
  94  *      - we are not using split page tables
  95  */
  96 ENTRY(cpu_v6_switch_mm)
  97 #ifdef CONFIG_MMU
  98         mov     r2, #0
  99         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
 100         orr     r0, r0, #TTB_FLAGS
 101         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 102         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
 103         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 104         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 105 #endif
 106         mov     pc, lr
 107
 108 /*
 109  *      cpu_v6_set_pte_ext(ptep, pte, ext)
 110  *
 111  *      Set a level 2 translation table entry.
 112  *
 113  *      - ptep  - pointer to level 2 translation table entry
 114  *                (hardware version is stored at -1024 bytes)
 115  *      - pte   - PTE value to store
 116  *      - ext   - value for extended PTE bits
 117  *
 118  *      Permissions:
 119  *        YUWD  APX AP1 AP0     SVC     User
 120  *        0xxx   0   0   0      no acc  no acc
 121  *        100x   1   0   1      r/o     no acc
 122  *        10x0   1   0   1      r/o     no acc
 123  *        1011   0   0   1      r/w     no acc
 124  *        110x   0   1   0      r/w     r/o
 125  *        11x0   0   1   0      r/w     r/o
 126  *        1111   0   1   1      r/w     r/w
 127  */
 128 ENTRY(cpu_v6_set_pte_ext)
 129 #ifdef CONFIG_MMU
 130         str     r1, [r0], #-2048                @ linux version
 131
 132         bic     r3, r1, #0x000003f0
 133         bic     r3, r3, #0x00000003
 134         orr     r3, r3, r2
 135         orr     r3, r3, #PTE_EXT_AP0 | 2
 136
 137         tst     r1, #L_PTE_WRITE
 138         tstne   r1, #L_PTE_DIRTY
 139         orreq   r3, r3, #PTE_EXT_APX
 140
 141         tst     r1, #L_PTE_USER
 142         orrne   r3, r3, #PTE_EXT_AP1
 143         tstne   r3, #PTE_EXT_APX
 144         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 145
 146         tst     r1, #L_PTE_YOUNG
 147         biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
 148
 149         tst     r1, #L_PTE_EXEC
 150         orreq   r3, r3, #PTE_EXT_XN
 151
 152         tst     r1, #L_PTE_PRESENT
 153         moveq   r3, #0
 154
 155         str     r3, [r0]
 156         mcr     p15, 0, r0, c7, c10, 1 @ flush_pte
 157 #endif
 158         mov     pc, lr
 159
 160
 161
 162
 163 cpu_v6_name:
 164         .asciz  "ARMv6-compatible processor"
 165         .align
 166
 167         .section ".text.init", #alloc, #execinstr
 168
 169 /*
 170  *      __v6_setup
 171  *
 172  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 173  *      on.  Return in r0 the new CP15 C1 control register setting.
 174  *
 175  *      We automatically detect if we have a Harvard cache, and use the
 176  *      Harvard cache control instructions insead of the unified cache
 177  *      control instructions.
 178  *
 179  *      This should be able to cover all ARMv6 cores.
 180  *
 181  *      It is assumed that:
 182  *      - cache type register is implemented
 183  */
 184 __v6_setup:
 185 #ifdef CONFIG_SMP
 186         mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
 187         orr     r0, r0, #0x20
 188         mcr     p15, 0, r0, c1, c0, 1
 189 #endif
 190
 191         mov     r0, #0
 192         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
 193         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 194         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
 195         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 196 #ifdef CONFIG_MMU
 197         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
 198         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
 199         orr     r4, r4, #TTB_FLAGS
 200         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 201 #endif /* CONFIG_MMU */
 202         adr     r5, v6_crval
 203         ldmia   r5, {r5, r6}
 204         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 205         bic     r0, r0, r5                      @ clear bits them
 206         orr     r0, r0, r6                      @ set them
 207         mov     pc, lr                          @ return to head.S:__ret
 208
 209         /*
 210          *         V X F   I D LR
 211          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 212          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 213          *         0 110       0011 1.00 .111 1101 < we want
 214          */
 215         .type   v6_crval, #object
 216 v6_crval:
 217         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 218
 219         .type   v6_processor_functions, #object
 220 ENTRY(v6_processor_functions)
 221         .word   v6_early_abort
 222         .word   pabort_noifar
 223         .word   cpu_v6_proc_init
 224         .word   cpu_v6_proc_fin
 225         .word   cpu_v6_reset
 226         .word   cpu_v6_do_idle
 227         .word   cpu_v6_dcache_clean_area
 228         .word   cpu_v6_switch_mm
 229         .word   cpu_v6_set_pte_ext
 230         .size   v6_processor_functions, . - v6_processor_functions
 231
 232         .type   cpu_arch_name, #object
 233 cpu_arch_name:
 234         .asciz  "armv6"
 235         .size   cpu_arch_name, . - cpu_arch_name
 236
 237         .type   cpu_elf_name, #object
 238 cpu_elf_name:
 239         .asciz  "v6"
 240         .size   cpu_elf_name, . - cpu_elf_name
 241         .align
 242
 243         .section ".proc.info.init", #alloc, #execinstr
 244
 245         /*
 246          * Match any ARMv6 processor core.
 247          */
 248         .type   __v6_proc_info, #object
 249 __v6_proc_info:
 250         .long   0x0007b000
 251         .long   0x0007f000
 252         .long   PMD_TYPE_SECT | \
 253                 PMD_SECT_BUFFERABLE | \
 254                 PMD_SECT_CACHEABLE | \
 255                 PMD_SECT_AP_WRITE | \
 256                 PMD_SECT_AP_READ
 257         .long   PMD_TYPE_SECT | \
 258                 PMD_SECT_XN | \
 259                 PMD_SECT_AP_WRITE | \
 260                 PMD_SECT_AP_READ
 261         b       __v6_setup
 262         .long   cpu_arch_name
 263         .long   cpu_elf_name
 264         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
 265         .long   cpu_v6_name
 266         .long   v6_processor_functions
 267         .long   v6wbi_tlb_fns
 268         .long   v6_user_fns
 269         .long   v6_cache_fns
 270         .size   __v6_proc_info, . - __v6_proc_info