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[deliverable/linux.git] / arch / arm / mm / proc-v7.S
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
19
20 #include "proc-macros.S"
21
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
24 #else
25 #include "proc-v7-2level.S"
26 #endif
27
28 ENTRY(cpu_v7_proc_init)
29 ret lr
30 ENDPROC(cpu_v7_proc_init)
31
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
37 ret lr
38 ENDPROC(cpu_v7_proc_fin)
39
40 /*
41 * cpu_v7_reset(loc)
42 *
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
46 *
47 * - loc - location to jump to for soft reset
48 *
49 * This code must be executed using a flat identity mapping with
50 * caches disabled.
51 */
52 .align 5
53 .pushsection .idmap.text, "ax"
54 ENTRY(cpu_v7_reset)
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
59 isb
60 bx r0
61 ENDPROC(cpu_v7_reset)
62 .popsection
63
64 /*
65 * cpu_v7_do_idle()
66 *
67 * Idle the processor (eg, wait for interrupt).
68 *
69 * IRQs are already disabled.
70 */
71 ENTRY(cpu_v7_do_idle)
72 dsb @ WFI may enter a low-power mode
73 wfi
74 ret lr
75 ENDPROC(cpu_v7_do_idle)
76
77 ENTRY(cpu_v7_dcache_clean_area)
78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
79 ALT_UP_B(1f)
80 ret lr
81 1: dcache_line_size r2, r3
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, r2
84 subs r1, r1, r2
85 bhi 2b
86 dsb ishst
87 ret lr
88 ENDPROC(cpu_v7_dcache_clean_area)
89
90 string cpu_v7_name, "ARMv7 Processor"
91 .align
92
93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94 .globl cpu_v7_suspend_size
95 .equ cpu_v7_suspend_size, 4 * 9
96 #ifdef CONFIG_ARM_CPU_SUSPEND
97 ENTRY(cpu_v7_do_suspend)
98 stmfd sp!, {r4 - r10, lr}
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 stmia r0!, {r4 - r5}
102 #ifdef CONFIG_MMU
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
104 #ifdef CONFIG_ARM_LPAE
105 mrrc p15, 1, r5, r7, c2 @ TTB 1
106 #else
107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
108 #endif
109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
110 #endif
111 mrc p15, 0, r8, c1, c0, 0 @ Control register
112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
114 stmia r0, {r5 - r11}
115 ldmfd sp!, {r4 - r10, pc}
116 ENDPROC(cpu_v7_do_suspend)
117
118 ENTRY(cpu_v7_do_resume)
119 mov ip, #0
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
122 ldmia r0!, {r4 - r5}
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
125 ldmia r0, {r5 - r11}
126 #ifdef CONFIG_MMU
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
129 #ifdef CONFIG_ARM_LPAE
130 mcrr p15, 0, r1, ip, c2 @ TTB 0
131 mcrr p15, 1, r5, r7, c2 @ TTB 1
132 #else
133 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
134 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
137 #endif
138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
139 ldr r4, =PRRR @ PRRR
140 ldr r5, =NMRR @ NMRR
141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
143 #endif /* CONFIG_MMU */
144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
145 teq r4, r9 @ Is it already set?
146 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
148 isb
149 dsb
150 mov r0, r8 @ control register
151 b cpu_resume_mmu
152 ENDPROC(cpu_v7_do_resume)
153 #endif
154
155 /*
156 * Cortex-A8
157 */
158 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
159 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
160 globl_equ cpu_ca8_reset, cpu_v7_reset
161 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
162 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
163 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
164 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
165 #ifdef CONFIG_ARM_CPU_SUSPEND
166 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
167 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
168 #endif
169
170 /*
171 * Cortex-A9 processor functions
172 */
173 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
174 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
175 globl_equ cpu_ca9mp_reset, cpu_v7_reset
176 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
177 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
178 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
179 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
180 .globl cpu_ca9mp_suspend_size
181 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
182 #ifdef CONFIG_ARM_CPU_SUSPEND
183 ENTRY(cpu_ca9mp_do_suspend)
184 stmfd sp!, {r4 - r5}
185 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
186 mrc p15, 0, r5, c15, c0, 0 @ Power register
187 stmia r0!, {r4 - r5}
188 ldmfd sp!, {r4 - r5}
189 b cpu_v7_do_suspend
190 ENDPROC(cpu_ca9mp_do_suspend)
191
192 ENTRY(cpu_ca9mp_do_resume)
193 ldmia r0!, {r4 - r5}
194 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
195 teq r4, r10 @ Already restored?
196 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
197 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
198 teq r5, r10 @ Already restored?
199 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
200 b cpu_v7_do_resume
201 ENDPROC(cpu_ca9mp_do_resume)
202 #endif
203
204 #ifdef CONFIG_CPU_PJ4B
205 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
206 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
207 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
208 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
209 globl_equ cpu_pj4b_reset, cpu_v7_reset
210 #ifdef CONFIG_PJ4B_ERRATA_4742
211 ENTRY(cpu_pj4b_do_idle)
212 dsb @ WFI may enter a low-power mode
213 wfi
214 dsb @barrier
215 ret lr
216 ENDPROC(cpu_pj4b_do_idle)
217 #else
218 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
219 #endif
220 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
221 #ifdef CONFIG_ARM_CPU_SUSPEND
222 ENTRY(cpu_pj4b_do_suspend)
223 stmfd sp!, {r6 - r10}
224 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
225 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
226 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
227 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
228 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
229 stmia r0!, {r6 - r10}
230 ldmfd sp!, {r6 - r10}
231 b cpu_v7_do_suspend
232 ENDPROC(cpu_pj4b_do_suspend)
233
234 ENTRY(cpu_pj4b_do_resume)
235 ldmia r0!, {r6 - r10}
236 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
237 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
238 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
239 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
241 b cpu_v7_do_resume
242 ENDPROC(cpu_pj4b_do_resume)
243 #endif
244 .globl cpu_pj4b_suspend_size
245 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
246
247 #endif
248
249 /*
250 * __v7_setup
251 *
252 * Initialise TLB, Caches, and MMU state ready to switch the MMU
253 * on. Return in r0 the new CP15 C1 control register setting.
254 *
255 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
256 * r4: TTBR0 (low word)
257 * r5: TTBR0 (high word if LPAE)
258 * r8: TTBR1
259 * r9: Main ID register
260 *
261 * This should be able to cover all ARMv7 cores.
262 *
263 * It is assumed that:
264 * - cache type register is implemented
265 */
266 __v7_ca5mp_setup:
267 __v7_ca9mp_setup:
268 __v7_cr7mp_setup:
269 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
270 b 1f
271 __v7_ca7mp_setup:
272 __v7_ca12mp_setup:
273 __v7_ca15mp_setup:
274 __v7_b15mp_setup:
275 __v7_ca17mp_setup:
276 mov r10, #0
277 1: adr r12, __v7_setup_stack @ the local stack
278 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
279 bl v7_invalidate_l1
280 ldmia r12, {r0-r5, lr}
281 #ifdef CONFIG_SMP
282 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
283 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
284 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
285 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
286 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
287 mcreq p15, 0, r0, c1, c0, 1
288 #endif
289 b __v7_setup_cont
290
291 /*
292 * Errata:
293 * r0, r10 available for use
294 * r1, r2, r4, r5, r9, r13: must be preserved
295 * r3: contains MIDR rX number in bits 23-20
296 * r6: contains MIDR rXpY as 8-bit XY number
297 * r9: MIDR
298 */
299 __ca8_errata:
300 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
301 teq r3, #0x00100000 @ only present in r1p*
302 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
303 orreq r0, r0, #(1 << 6) @ set IBE to 1
304 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
305 #endif
306 #ifdef CONFIG_ARM_ERRATA_458693
307 teq r6, #0x20 @ only present in r2p0
308 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
309 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
310 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
311 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
312 #endif
313 #ifdef CONFIG_ARM_ERRATA_460075
314 teq r6, #0x20 @ only present in r2p0
315 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
316 tsteq r0, #1 << 22
317 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
318 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
319 #endif
320 b __errata_finish
321
322 __ca9_errata:
323 #ifdef CONFIG_ARM_ERRATA_742230
324 cmp r6, #0x22 @ only present up to r2p2
325 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
326 orrle r0, r0, #1 << 4 @ set bit #4
327 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
328 #endif
329 #ifdef CONFIG_ARM_ERRATA_742231
330 teq r6, #0x20 @ present in r2p0
331 teqne r6, #0x21 @ present in r2p1
332 teqne r6, #0x22 @ present in r2p2
333 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
334 orreq r0, r0, #1 << 12 @ set bit #12
335 orreq r0, r0, #1 << 22 @ set bit #22
336 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
337 #endif
338 #ifdef CONFIG_ARM_ERRATA_743622
339 teq r3, #0x00200000 @ only present in r2p*
340 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
341 orreq r0, r0, #1 << 6 @ set bit #6
342 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
343 #endif
344 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
345 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
346 ALT_UP_B(1f)
347 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
348 orrlt r0, r0, #1 << 11 @ set bit #11
349 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
350 1:
351 #endif
352 b __errata_finish
353
354 __ca15_errata:
355 #ifdef CONFIG_ARM_ERRATA_773022
356 cmp r6, #0x4 @ only present up to r0p4
357 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
358 orrle r0, r0, #1 << 1 @ disable loop buffer
359 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
360 #endif
361 b __errata_finish
362
363 __v7_pj4b_setup:
364 #ifdef CONFIG_CPU_PJ4B
365
366 /* Auxiliary Debug Modes Control 1 Register */
367 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
368 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
369 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
370
371 /* Auxiliary Debug Modes Control 2 Register */
372 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
373 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
374 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
375 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
376 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
377 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
378 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
379
380 /* Auxiliary Functional Modes Control Register 0 */
381 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
382 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
383 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
384
385 /* Auxiliary Debug Modes Control 0 Register */
386 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
387
388 /* Auxiliary Debug Modes Control 1 Register */
389 mrc p15, 1, r0, c15, c1, 1
390 orr r0, r0, #PJ4B_CLEAN_LINE
391 orr r0, r0, #PJ4B_INTER_PARITY
392 bic r0, r0, #PJ4B_STATIC_BP
393 mcr p15, 1, r0, c15, c1, 1
394
395 /* Auxiliary Debug Modes Control 2 Register */
396 mrc p15, 1, r0, c15, c1, 2
397 bic r0, r0, #PJ4B_FAST_LDR
398 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
399 mcr p15, 1, r0, c15, c1, 2
400
401 /* Auxiliary Functional Modes Control Register 0 */
402 mrc p15, 1, r0, c15, c2, 0
403 #ifdef CONFIG_SMP
404 orr r0, r0, #PJ4B_SMP_CFB
405 #endif
406 orr r0, r0, #PJ4B_L1_PAR_CHK
407 orr r0, r0, #PJ4B_BROADCAST_CACHE
408 mcr p15, 1, r0, c15, c2, 0
409
410 /* Auxiliary Debug Modes Control 0 Register */
411 mrc p15, 1, r0, c15, c1, 0
412 orr r0, r0, #PJ4B_WFI_WFE
413 mcr p15, 1, r0, c15, c1, 0
414
415 #endif /* CONFIG_CPU_PJ4B */
416
417 __v7_setup:
418 adr r12, __v7_setup_stack @ the local stack
419 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
420 bl v7_invalidate_l1
421 ldmia r12, {r0-r5, lr}
422
423 __v7_setup_cont:
424 and r0, r9, #0xff000000 @ ARM?
425 teq r0, #0x41000000
426 bne __errata_finish
427 and r3, r9, #0x00f00000 @ variant
428 and r6, r9, #0x0000000f @ revision
429 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
430 ubfx r0, r9, #4, #12 @ primary part number
431
432 /* Cortex-A8 Errata */
433 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
434 teq r0, r10
435 beq __ca8_errata
436
437 /* Cortex-A9 Errata */
438 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
439 teq r0, r10
440 beq __ca9_errata
441
442 /* Cortex-A15 Errata */
443 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
444 teq r0, r10
445 beq __ca15_errata
446
447 __errata_finish:
448 mov r10, #0
449 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
450 #ifdef CONFIG_MMU
451 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
452 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
453 ldr r3, =PRRR @ PRRR
454 ldr r6, =NMRR @ NMRR
455 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
456 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
457 #endif
458 dsb @ Complete invalidations
459 #ifndef CONFIG_ARM_THUMBEE
460 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
461 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
462 teq r0, #(1 << 12) @ check if ThumbEE is present
463 bne 1f
464 mov r3, #0
465 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
466 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
467 orr r0, r0, #1 @ set the 1st bit in order to
468 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
469 1:
470 #endif
471 adr r3, v7_crval
472 ldmia r3, {r3, r6}
473 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
474 #ifdef CONFIG_SWP_EMULATE
475 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
476 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
477 #endif
478 mrc p15, 0, r0, c1, c0, 0 @ read control register
479 bic r0, r0, r3 @ clear bits them
480 orr r0, r0, r6 @ set them
481 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
482 ret lr @ return to head.S:__ret
483 ENDPROC(__v7_setup)
484
485 .align 2
486 __v7_setup_stack:
487 .space 4 * 7 @ 12 registers
488
489 __INITDATA
490
491 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
492 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
493 #ifndef CONFIG_ARM_LPAE
494 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
495 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
496 #endif
497 #ifdef CONFIG_CPU_PJ4B
498 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
499 #endif
500
501 .section ".rodata"
502
503 string cpu_arch_name, "armv7"
504 string cpu_elf_name, "v7"
505 .align
506
507 .section ".proc.info.init", #alloc
508
509 /*
510 * Standard v7 proc info content
511 */
512 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
513 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
514 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
515 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
516 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
517 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
518 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
519 initfn \initfunc, \name
520 .long cpu_arch_name
521 .long cpu_elf_name
522 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
523 HWCAP_EDSP | HWCAP_TLS | \hwcaps
524 .long cpu_v7_name
525 .long \proc_fns
526 .long v7wbi_tlb_fns
527 .long v6_user_fns
528 .long v7_cache_fns
529 .endm
530
531 #ifndef CONFIG_ARM_LPAE
532 /*
533 * ARM Ltd. Cortex A5 processor.
534 */
535 .type __v7_ca5mp_proc_info, #object
536 __v7_ca5mp_proc_info:
537 .long 0x410fc050
538 .long 0xff0ffff0
539 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
540 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
541
542 /*
543 * ARM Ltd. Cortex A9 processor.
544 */
545 .type __v7_ca9mp_proc_info, #object
546 __v7_ca9mp_proc_info:
547 .long 0x410fc090
548 .long 0xff0ffff0
549 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
550 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
551
552 /*
553 * ARM Ltd. Cortex A8 processor.
554 */
555 .type __v7_ca8_proc_info, #object
556 __v7_ca8_proc_info:
557 .long 0x410fc080
558 .long 0xff0ffff0
559 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
560 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
561
562 #endif /* CONFIG_ARM_LPAE */
563
564 /*
565 * Marvell PJ4B processor.
566 */
567 #ifdef CONFIG_CPU_PJ4B
568 .type __v7_pj4b_proc_info, #object
569 __v7_pj4b_proc_info:
570 .long 0x560f5800
571 .long 0xff0fff00
572 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
573 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
574 #endif
575
576 /*
577 * ARM Ltd. Cortex R7 processor.
578 */
579 .type __v7_cr7mp_proc_info, #object
580 __v7_cr7mp_proc_info:
581 .long 0x410fc170
582 .long 0xff0ffff0
583 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
584 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
585
586 /*
587 * ARM Ltd. Cortex A7 processor.
588 */
589 .type __v7_ca7mp_proc_info, #object
590 __v7_ca7mp_proc_info:
591 .long 0x410fc070
592 .long 0xff0ffff0
593 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
594 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
595
596 /*
597 * ARM Ltd. Cortex A12 processor.
598 */
599 .type __v7_ca12mp_proc_info, #object
600 __v7_ca12mp_proc_info:
601 .long 0x410fc0d0
602 .long 0xff0ffff0
603 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
604 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
605
606 /*
607 * ARM Ltd. Cortex A15 processor.
608 */
609 .type __v7_ca15mp_proc_info, #object
610 __v7_ca15mp_proc_info:
611 .long 0x410fc0f0
612 .long 0xff0ffff0
613 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
614 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
615
616 /*
617 * Broadcom Corporation Brahma-B15 processor.
618 */
619 .type __v7_b15mp_proc_info, #object
620 __v7_b15mp_proc_info:
621 .long 0x420f00f0
622 .long 0xff0ffff0
623 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup
624 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
625
626 /*
627 * ARM Ltd. Cortex A17 processor.
628 */
629 .type __v7_ca17mp_proc_info, #object
630 __v7_ca17mp_proc_info:
631 .long 0x410fc0e0
632 .long 0xff0ffff0
633 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
634 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
635
636 /*
637 * Qualcomm Inc. Krait processors.
638 */
639 .type __krait_proc_info, #object
640 __krait_proc_info:
641 .long 0x510f0400 @ Required ID value
642 .long 0xff0ffc00 @ Mask for ID
643 /*
644 * Some Krait processors don't indicate support for SDIV and UDIV
645 * instructions in the ARM instruction set, even though they actually
646 * do support them. They also don't indicate support for fused multiply
647 * instructions even though they actually do support them.
648 */
649 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
650 .size __krait_proc_info, . - __krait_proc_info
651
652 /*
653 * Match any ARMv7 processor core.
654 */
655 .type __v7_proc_info, #object
656 __v7_proc_info:
657 .long 0x000f0000 @ Required ID value
658 .long 0x000f0000 @ Mask for ID
659 __v7_proc __v7_proc_info, __v7_setup
660 .size __v7_proc_info, . - __v7_proc_info
Linux kernel - Deliverables
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