arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/linkage.h>
  13 #include <asm/assembler.h>
  14 #include <asm/asm-offsets.h>
  15 #include <asm/hwcap.h>
  16 #include <asm/pgtable-hwdef.h>
  17 #include <asm/pgtable.h>
  18
  19 #include "proc-macros.S"
  20
  21 #define TTB_C           (1 << 0)
  22 #define TTB_S           (1 << 1)
  23 #define TTB_RGN_NC      (0 << 3)
  24 #define TTB_RGN_OC_WBWA (1 << 3)
  25 #define TTB_RGN_OC_WT   (2 << 3)
  26 #define TTB_RGN_OC_WB   (3 << 3)
  27
  28 #ifndef CONFIG_SMP
  29 #define TTB_FLAGS       TTB_C|TTB_RGN_OC_WB             @ mark PTWs cacheable, outer WB
  30 #else
  31 #define TTB_FLAGS       TTB_C|TTB_S|TTB_RGN_OC_WBWA     @ mark PTWs cacheable and shared, outer WBWA
  32 #endif
  33
  34 ENTRY(cpu_v7_proc_init)
  35         mov     pc, lr
  36 ENDPROC(cpu_v7_proc_init)
  37
  38 ENTRY(cpu_v7_proc_fin)
  39         mov     pc, lr
  40 ENDPROC(cpu_v7_proc_fin)
  41
  42 /*
  43  *      cpu_v7_reset(loc)
  44  *
  45  *      Perform a soft reset of the system.  Put the CPU into the
  46  *      same state as it would be if it had been reset, and branch
  47  *      to what would be the reset vector.
  48  *
  49  *      - loc   - location to jump to for soft reset
  50  *
  51  *      It is assumed that:
  52  */
  53         .align  5
  54 ENTRY(cpu_v7_reset)
  55         mov     pc, r0
  56 ENDPROC(cpu_v7_reset)
  57
  58 /*
  59  *      cpu_v7_do_idle()
  60  *
  61  *      Idle the processor (eg, wait for interrupt).
  62  *
  63  *      IRQs are already disabled.
  64  */
  65 ENTRY(cpu_v7_do_idle)
  66         dsb                                     @ WFI may enter a low-power mode
  67         wfi
  68         mov     pc, lr
  69 ENDPROC(cpu_v7_do_idle)
  70
  71 ENTRY(cpu_v7_dcache_clean_area)
  72 #ifndef TLB_CAN_READ_FROM_L1_CACHE
  73         dcache_line_size r2, r3
  74 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  75         add     r0, r0, r2
  76         subs    r1, r1, r2
  77         bhi     1b
  78         dsb
  79 #endif
  80         mov     pc, lr
  81 ENDPROC(cpu_v7_dcache_clean_area)
  82
  83 /*
  84  *      cpu_v7_switch_mm(pgd_phys, tsk)
  85  *
  86  *      Set the translation table base pointer to be pgd_phys
  87  *
  88  *      - pgd_phys - physical address of new TTB
  89  *
  90  *      It is assumed that:
  91  *      - we are not using split page tables
  92  */
  93 ENTRY(cpu_v7_switch_mm)
  94 #ifdef CONFIG_MMU
  95         mov     r2, #0
  96         ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
  97         orr     r0, r0, #TTB_FLAGS
  98 #ifdef CONFIG_ARM_ERRATA_430973
  99         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 100 #endif
 101         mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
 102         isb
 103 1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 104         isb
 105         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 106         isb
 107 #endif
 108         mov     pc, lr
 109 ENDPROC(cpu_v7_switch_mm)
 110
 111 /*
 112  *      cpu_v7_set_pte_ext(ptep, pte)
 113  *
 114  *      Set a level 2 translation table entry.
 115  *
 116  *      - ptep  - pointer to level 2 translation table entry
 117  *                (hardware version is stored at -1024 bytes)
 118  *      - pte   - PTE value to store
 119  *      - ext   - value for extended PTE bits
 120  */
 121 ENTRY(cpu_v7_set_pte_ext)
 122 #ifdef CONFIG_MMU
 123         str     r1, [r0], #-2048                @ linux version
 124
 125         bic     r3, r1, #0x000003f0
 126         bic     r3, r3, #PTE_TYPE_MASK
 127         orr     r3, r3, r2
 128         orr     r3, r3, #PTE_EXT_AP0 | 2
 129
 130         tst     r1, #1 << 4
 131         orrne   r3, r3, #PTE_EXT_TEX(1)
 132
 133         tst     r1, #L_PTE_WRITE
 134         tstne   r1, #L_PTE_DIRTY
 135         orreq   r3, r3, #PTE_EXT_APX
 136
 137         tst     r1, #L_PTE_USER
 138         orrne   r3, r3, #PTE_EXT_AP1
 139         tstne   r3, #PTE_EXT_APX
 140         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 141
 142         tst     r1, #L_PTE_EXEC
 143         orreq   r3, r3, #PTE_EXT_XN
 144
 145         tst     r1, #L_PTE_YOUNG
 146         tstne   r1, #L_PTE_PRESENT
 147         moveq   r3, #0
 148
 149         str     r3, [r0]
 150         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 151 #endif
 152         mov     pc, lr
 153 ENDPROC(cpu_v7_set_pte_ext)
 154
 155 cpu_v7_name:
 156         .ascii  "ARMv7 Processor"
 157         .align
 158
 159         .section ".text.init", #alloc, #execinstr
 160
 161 /*
 162  *      __v7_setup
 163  *
 164  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 165  *      on.  Return in r0 the new CP15 C1 control register setting.
 166  *
 167  *      We automatically detect if we have a Harvard cache, and use the
 168  *      Harvard cache control instructions insead of the unified cache
 169  *      control instructions.
 170  *
 171  *      This should be able to cover all ARMv7 cores.
 172  *
 173  *      It is assumed that:
 174  *      - cache type register is implemented
 175  */
 176 __v7_setup:
 177 #ifdef CONFIG_SMP
 178         mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
 179         orr     r0, r0, #(0x1 << 6)
 180         mcr     p15, 0, r0, c1, c0, 1
 181 #endif
 182         adr     r12, __v7_setup_stack           @ the local stack
 183         stmia   r12, {r0-r5, r7, r9, r11, lr}
 184         bl      v7_flush_dcache_all
 185         ldmia   r12, {r0-r5, r7, r9, r11, lr}
 186 #ifdef CONFIG_ARM_ERRATA_430973
 187         mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
 188         orr     r10, r10, #(1 << 6)             @ set IBE to 1
 189         mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
 190 #endif
 191 #ifdef CONFIG_ARM_ERRATA_458693
 192         mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
 193         orr     r10, r10, #(1 << 5)             @ set L1NEON to 1
 194         orr     r10, r10, #(1 << 9)             @ set PLDNOP to 1
 195         mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
 196 #endif
 197 #ifdef CONFIG_ARM_ERRATA_460075
 198         mrc     p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
 199         orr     r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
 200         mcr     p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 201 #endif
 202         mov     r10, #0
 203 #ifdef HARVARD_CACHE
 204         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 205 #endif
 206         dsb
 207 #ifdef CONFIG_MMU
 208         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 209         mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
 210         orr     r4, r4, #TTB_FLAGS
 211         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
 212         mov     r10, #0x1f                      @ domains 0, 1 = manager
 213         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 214 #endif
 215         ldr     r5, =0xff0aa1a8
 216         ldr     r6, =0x40e040e0
 217         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
 218         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 219         adr     r5, v7_crval
 220         ldmia   r5, {r5, r6}
 221         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 222         bic     r0, r0, r5                      @ clear bits them
 223         orr     r0, r0, r6                      @ set them
 224         mov     pc, lr                          @ return to head.S:__ret
 225 ENDPROC(__v7_setup)
 226
 227         /*   AT
 228          *  TFR   EV X F   I D LR
 229          * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
 230          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
 231          *    1    0 110       0011 1.00 .111 1101 < we want
 232          */
 233         .type   v7_crval, #object
 234 v7_crval:
 235         crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
 236
 237 __v7_setup_stack:
 238         .space  4 * 11                          @ 11 registers
 239
 240         .type   v7_processor_functions, #object
 241 ENTRY(v7_processor_functions)
 242         .word   v7_early_abort
 243         .word   pabort_ifar
 244         .word   cpu_v7_proc_init
 245         .word   cpu_v7_proc_fin
 246         .word   cpu_v7_reset
 247         .word   cpu_v7_do_idle
 248         .word   cpu_v7_dcache_clean_area
 249         .word   cpu_v7_switch_mm
 250         .word   cpu_v7_set_pte_ext
 251         .size   v7_processor_functions, . - v7_processor_functions
 252
 253         .type   cpu_arch_name, #object
 254 cpu_arch_name:
 255         .asciz  "armv7"
 256         .size   cpu_arch_name, . - cpu_arch_name
 257
 258         .type   cpu_elf_name, #object
 259 cpu_elf_name:
 260         .asciz  "v7"
 261         .size   cpu_elf_name, . - cpu_elf_name
 262         .align
 263
 264         .section ".proc.info.init", #alloc, #execinstr
 265
 266         /*
 267          * Match any ARMv7 processor core.
 268          */
 269         .type   __v7_proc_info, #object
 270 __v7_proc_info:
 271         .long   0x000f0000              @ Required ID value
 272         .long   0x000f0000              @ Mask for ID
 273         .long   PMD_TYPE_SECT | \
 274                 PMD_SECT_BUFFERABLE | \
 275                 PMD_SECT_CACHEABLE | \
 276                 PMD_SECT_AP_WRITE | \
 277                 PMD_SECT_AP_READ
 278         .long   PMD_TYPE_SECT | \
 279                 PMD_SECT_XN | \
 280                 PMD_SECT_AP_WRITE | \
 281                 PMD_SECT_AP_READ
 282         b       __v7_setup
 283         .long   cpu_arch_name
 284         .long   cpu_elf_name
 285         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 286         .long   cpu_v7_name
 287         .long   v7_processor_functions
 288         .long   v7wbi_tlb_fns
 289         .long   v6_user_fns
 290         .long   v7_cache_fns
 291         .size   __v7_proc_info, . - __v7_proc_info