arch/arm/oprofile/op_model_xscale.c

   1 /**
   2  * @file op_model_xscale.c
   3  * XScale Performance Monitor Driver
   4  *
   5  * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
   6  * @remark Copyright 2000-2004 MontaVista Software Inc
   7  * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
   8  * @remark Copyright 2004 Intel Corporation
   9  * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
  10  * @remark Copyright 2004 OProfile Authors
  11  *
  12  * @remark Read the file COPYING
  13  *
  14  * @author Zwane Mwaikambo
  15  */
  16
  17 /* #define DEBUG */
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/sched.h>
  21 #include <linux/oprofile.h>
  22 #include <linux/interrupt.h>
  23 #include <asm/irq.h>
  24 #include <asm/system.h>
  25
  26 #include "op_counter.h"
  27 #include "op_arm_model.h"
  28
  29 #define PMU_ENABLE      0x001   /* Enable counters */
  30 #define PMN_RESET       0x002   /* Reset event counters */
  31 #define CCNT_RESET      0x004   /* Reset clock counter */
  32 #define PMU_RESET       (CCNT_RESET | PMN_RESET)
  33 #define PMU_CNT64       0x008   /* Make CCNT count every 64th cycle */
  34
  35 /* TODO do runtime detection */
  36 #ifdef CONFIG_ARCH_IOP32X
  37 #define XSCALE_PMU_IRQ  IRQ_IOP32X_CORE_PMU
  38 #endif
  39 #ifdef CONFIG_ARCH_IOP33X
  40 #define XSCALE_PMU_IRQ  IRQ_IOP33X_CORE_PMU
  41 #endif
  42 #ifdef CONFIG_ARCH_PXA
  43 #define XSCALE_PMU_IRQ  IRQ_PMU
  44 #endif
  45
  46 /*
  47  * Different types of events that can be counted by the XScale PMU
  48  * as used by Oprofile userspace. Here primarily for documentation
  49  * purposes.
  50  */
  51
  52 #define EVT_ICACHE_MISS                 0x00
  53 #define EVT_ICACHE_NO_DELIVER           0x01
  54 #define EVT_DATA_STALL                  0x02
  55 #define EVT_ITLB_MISS                   0x03
  56 #define EVT_DTLB_MISS                   0x04
  57 #define EVT_BRANCH                      0x05
  58 #define EVT_BRANCH_MISS                 0x06
  59 #define EVT_INSTRUCTION                 0x07
  60 #define EVT_DCACHE_FULL_STALL           0x08
  61 #define EVT_DCACHE_FULL_STALL_CONTIG    0x09
  62 #define EVT_DCACHE_ACCESS               0x0A
  63 #define EVT_DCACHE_MISS                 0x0B
  64 #define EVT_DCACE_WRITE_BACK            0x0C
  65 #define EVT_PC_CHANGED                  0x0D
  66 #define EVT_BCU_REQUEST                 0x10
  67 #define EVT_BCU_FULL                    0x11
  68 #define EVT_BCU_DRAIN                   0x12
  69 #define EVT_BCU_ECC_NO_ELOG             0x14
  70 #define EVT_BCU_1_BIT_ERR               0x15
  71 #define EVT_RMW                         0x16
  72 /* EVT_CCNT is not hardware defined */
  73 #define EVT_CCNT                        0xFE
  74 #define EVT_UNUSED                      0xFF
  75
  76 struct pmu_counter {
  77         volatile unsigned long ovf;
  78         unsigned long reset_counter;
  79 };
  80
  81 enum { CCNT, PMN0, PMN1, PMN2, PMN3, MAX_COUNTERS };
  82
  83 static struct pmu_counter results[MAX_COUNTERS];
  84
  85 /*
  86  * There are two versions of the PMU in current XScale processors
  87  * with differing register layouts and number of performance counters.
  88  * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
  89  * We detect which register layout to use in xscale_detect_pmu()
  90  */
  91 enum { PMU_XSC1, PMU_XSC2 };
  92
  93 struct pmu_type {
  94         int id;
  95         char *name;
  96         int num_counters;
  97         unsigned int int_enable;
  98         unsigned int cnt_ovf[MAX_COUNTERS];
  99         unsigned int int_mask[MAX_COUNTERS];
 100 };
 101
 102 static struct pmu_type pmu_parms[] = {
 103         {
 104                 .id             = PMU_XSC1,
 105                 .name           = "arm/xscale1",
 106                 .num_counters   = 3,
 107                 .int_mask       = { [PMN0] = 0x10, [PMN1] = 0x20,
 108                                     [CCNT] = 0x40 },
 109                 .cnt_ovf        = { [CCNT] = 0x400, [PMN0] = 0x100,
 110                                     [PMN1] = 0x200},
 111         },
 112         {
 113                 .id             = PMU_XSC2,
 114                 .name           = "arm/xscale2",
 115                 .num_counters   = 5,
 116                 .int_mask       = { [CCNT] = 0x01, [PMN0] = 0x02,
 117                                     [PMN1] = 0x04, [PMN2] = 0x08,
 118                                     [PMN3] = 0x10 },
 119                 .cnt_ovf        = { [CCNT] = 0x01, [PMN0] = 0x02,
 120                                     [PMN1] = 0x04, [PMN2] = 0x08,
 121                                     [PMN3] = 0x10 },
 122         },
 123 };
 124
 125 static struct pmu_type *pmu;
 126
 127 static void write_pmnc(u32 val)
 128 {
 129         if (pmu->id == PMU_XSC1) {
 130                 /* upper 4bits and 7, 11 are write-as-0 */
 131                 val &= 0xffff77f;
 132                 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
 133         } else {
 134                 /* bits 4-23 are write-as-0, 24-31 are write ignored */
 135                 val &= 0xf;
 136                 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
 137         }
 138 }
 139
 140 static u32 read_pmnc(void)
 141 {
 142         u32 val;
 143
 144         if (pmu->id == PMU_XSC1)
 145                 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
 146         else {
 147                 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
 148                 /* bits 1-2 and 4-23 are read-unpredictable */
 149                 val &= 0xff000009;
 150         }
 151
 152         return val;
 153 }
 154
 155 static u32 __xsc1_read_counter(int counter)
 156 {
 157         u32 val = 0;
 158
 159         switch (counter) {
 160         case CCNT:
 161                 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
 162                 break;
 163         case PMN0:
 164                 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
 165                 break;
 166         case PMN1:
 167                 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
 168                 break;
 169         }
 170         return val;
 171 }
 172
 173 static u32 __xsc2_read_counter(int counter)
 174 {
 175         u32 val = 0;
 176
 177         switch (counter) {
 178         case CCNT:
 179                 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
 180                 break;
 181         case PMN0:
 182                 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
 183                 break;
 184         case PMN1:
 185                 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
 186                 break;
 187         case PMN2:
 188                 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
 189                 break;
 190         case PMN3:
 191                 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
 192                 break;
 193         }
 194         return val;
 195 }
 196
 197 static u32 read_counter(int counter)
 198 {
 199         u32 val;
 200
 201         if (pmu->id == PMU_XSC1)
 202                 val = __xsc1_read_counter(counter);
 203         else
 204                 val = __xsc2_read_counter(counter);
 205
 206         return val;
 207 }
 208
 209 static void __xsc1_write_counter(int counter, u32 val)
 210 {
 211         switch (counter) {
 212         case CCNT:
 213                 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
 214                 break;
 215         case PMN0:
 216                 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
 217                 break;
 218         case PMN1:
 219                 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
 220                 break;
 221         }
 222 }
 223
 224 static void __xsc2_write_counter(int counter, u32 val)
 225 {
 226         switch (counter) {
 227         case CCNT:
 228                 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
 229                 break;
 230         case PMN0:
 231                 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
 232                 break;
 233         case PMN1:
 234                 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
 235                 break;
 236         case PMN2:
 237                 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
 238                 break;
 239         case PMN3:
 240                 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
 241                 break;
 242         }
 243 }
 244
 245 static void write_counter(int counter, u32 val)
 246 {
 247         if (pmu->id == PMU_XSC1)
 248                 __xsc1_write_counter(counter, val);
 249         else
 250                 __xsc2_write_counter(counter, val);
 251 }
 252
 253 static int xscale_setup_ctrs(void)
 254 {
 255         u32 evtsel, pmnc;
 256         int i;
 257
 258         for (i = CCNT; i < MAX_COUNTERS; i++) {
 259                 if (counter_config[i].enabled)
 260                         continue;
 261
 262                 counter_config[i].event = EVT_UNUSED;
 263         }
 264
 265         switch (pmu->id) {
 266         case PMU_XSC1:
 267                 pmnc = (counter_config[PMN1].event << 20) | (counter_config[PMN0].event << 12);
 268                 pr_debug("xscale_setup_ctrs: pmnc: %#08x\n", pmnc);
 269                 write_pmnc(pmnc);
 270                 break;
 271
 272         case PMU_XSC2:
 273                 evtsel = counter_config[PMN0].event | (counter_config[PMN1].event << 8) |
 274                         (counter_config[PMN2].event << 16) | (counter_config[PMN3].event << 24);
 275
 276                 pr_debug("xscale_setup_ctrs: evtsel %#08x\n", evtsel);
 277                 __asm__ __volatile__ ("mcr p14, 0, %0, c8, c1, 0" : : "r" (evtsel));
 278                 break;
 279         }
 280
 281         for (i = CCNT; i < MAX_COUNTERS; i++) {
 282                 if (counter_config[i].event == EVT_UNUSED) {
 283                         counter_config[i].event = 0;
 284                         pmu->int_enable &= ~pmu->int_mask[i];
 285                         continue;
 286                 }
 287
 288                 results[i].reset_counter = counter_config[i].count;
 289                 write_counter(i, -(u32)counter_config[i].count);
 290                 pmu->int_enable |= pmu->int_mask[i];
 291                 pr_debug("xscale_setup_ctrs: counter%d %#08x from %#08lx\n", i,
 292                         read_counter(i), counter_config[i].count);
 293         }
 294
 295         return 0;
 296 }
 297
 298 static void inline __xsc1_check_ctrs(void)
 299 {
 300         int i;
 301         u32 pmnc = read_pmnc();
 302
 303         /* NOTE: there's an A stepping errata that states if an overflow */
 304         /*       bit already exists and another occurs, the previous     */
 305         /*       Overflow bit gets cleared. There's no workaround.       */
 306         /*       Fixed in B stepping or later                            */
 307
 308         /* Write the value back to clear the overflow flags. Overflow */
 309         /* flags remain in pmnc for use below */
 310         write_pmnc(pmnc & ~PMU_ENABLE);
 311
 312         for (i = CCNT; i <= PMN1; i++) {
 313                 if (!(pmu->int_mask[i] & pmu->int_enable))
 314                         continue;
 315
 316                 if (pmnc & pmu->cnt_ovf[i])
 317                         results[i].ovf++;
 318         }
 319 }
 320
 321 static void inline __xsc2_check_ctrs(void)
 322 {
 323         int i;
 324         u32 flag = 0, pmnc = read_pmnc();
 325
 326         pmnc &= ~PMU_ENABLE;
 327         write_pmnc(pmnc);
 328
 329         /* read overflow flag register */
 330         __asm__ __volatile__ ("mrc p14, 0, %0, c5, c1, 0" : "=r" (flag));
 331
 332         for (i = CCNT; i <= PMN3; i++) {
 333                 if (!(pmu->int_mask[i] & pmu->int_enable))
 334                         continue;
 335
 336                 if (flag & pmu->cnt_ovf[i])
 337                         results[i].ovf++;
 338         }
 339
 340         /* writeback clears overflow bits */
 341         __asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag));
 342 }
 343
 344 static irqreturn_t xscale_pmu_interrupt(int irq, void *arg)
 345 {
 346         int i;
 347         u32 pmnc;
 348
 349         if (pmu->id == PMU_XSC1)
 350                 __xsc1_check_ctrs();
 351         else
 352                 __xsc2_check_ctrs();
 353
 354         for (i = CCNT; i < MAX_COUNTERS; i++) {
 355                 if (!results[i].ovf)
 356                         continue;
 357
 358                 write_counter(i, -(u32)results[i].reset_counter);
 359                 oprofile_add_sample(get_irq_regs(), i);
 360                 results[i].ovf--;
 361         }
 362
 363         pmnc = read_pmnc() | PMU_ENABLE;
 364         write_pmnc(pmnc);
 365
 366         return IRQ_HANDLED;
 367 }
 368
 369 static void xscale_pmu_stop(void)
 370 {
 371         u32 pmnc = read_pmnc();
 372
 373         pmnc &= ~PMU_ENABLE;
 374         write_pmnc(pmnc);
 375
 376         free_irq(XSCALE_PMU_IRQ, results);
 377 }
 378
 379 static int xscale_pmu_start(void)
 380 {
 381         int ret;
 382         u32 pmnc = read_pmnc();
 383
 384         ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED,
 385                         "XScale PMU", (void *)results);
 386
 387         if (ret < 0) {
 388                 printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
 389                         XSCALE_PMU_IRQ);
 390                 return ret;
 391         }
 392
 393         if (pmu->id == PMU_XSC1)
 394                 pmnc |= pmu->int_enable;
 395         else {
 396                 __asm__ __volatile__ ("mcr p14, 0, %0, c4, c1, 0" : : "r" (pmu->int_enable));
 397                 pmnc &= ~PMU_CNT64;
 398         }
 399
 400         pmnc |= PMU_ENABLE;
 401         write_pmnc(pmnc);
 402         pr_debug("xscale_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, pmu->int_enable);
 403         return 0;
 404 }
 405
 406 static int xscale_detect_pmu(void)
 407 {
 408         int ret = 0;
 409         u32 id;
 410
 411         id = (read_cpuid(CPUID_ID) >> 13) & 0x7;
 412
 413         switch (id) {
 414         case 1:
 415                 pmu = &pmu_parms[PMU_XSC1];
 416                 break;
 417         case 2:
 418                 pmu = &pmu_parms[PMU_XSC2];
 419                 break;
 420         default:
 421                 ret = -ENODEV;
 422                 break;
 423         }
 424
 425         if (!ret) {
 426                 op_xscale_spec.name = pmu->name;
 427                 op_xscale_spec.num_counters = pmu->num_counters;
 428                 pr_debug("xscale_detect_pmu: detected %s PMU\n", pmu->name);
 429         }
 430
 431         return ret;
 432 }
 433
 434 struct op_arm_model_spec op_xscale_spec = {
 435         .init           = xscale_detect_pmu,
 436         .setup_ctrs     = xscale_setup_ctrs,
 437         .start          = xscale_pmu_start,
 438         .stop           = xscale_pmu_stop,
 439 };
 440