arch/arm/plat-mxc/avic.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqdomain.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <mach/common.h>
  26 #include <asm/mach/irq.h>
  27 #include <asm/exception.h>
  28 #include <mach/hardware.h>
  29 #include <mach/irqs.h>
  30
  31 #include "irq-common.h"
  32
  33 #define AVIC_INTCNTL            0x00    /* int control reg */
  34 #define AVIC_NIMASK             0x04    /* int mask reg */
  35 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  36 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  37 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  38 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  39 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  40 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  41 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  42 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  43 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  44 #define AVIC_INTSRCH            0x48    /* int source reg high */
  45 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  46 #define AVIC_INTFRCH            0x50    /* int force reg high */
  47 #define AVIC_INTFRCL            0x54    /* int force reg low */
  48 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  49 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  50 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  51 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  52
  53 #define AVIC_NUM_IRQS 64
  54
  55 void __iomem *avic_base;
  56 static struct irq_domain *domain;
  57
  58 static u32 avic_saved_mask_reg[2];
  59
  60 #ifdef CONFIG_MXC_IRQ_PRIOR
  61 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
  62 {
  63         struct irq_data *d = irq_get_irq_data(irq);
  64         unsigned int temp;
  65         unsigned int mask = 0x0F << irq % 8 * 4;
  66
  67         irq = d->hwirq;
  68
  69         if (irq >= AVIC_NUM_IRQS)
  70                 return -EINVAL;
  71
  72         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
  73         temp &= ~mask;
  74         temp |= prio & mask;
  75
  76         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
  77
  78         return 0;
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_FIQ
  83 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
  84 {
  85         struct irq_data *d = irq_get_irq_data(irq);
  86         unsigned int irqt;
  87
  88         irq = d->hwirq;
  89
  90         if (irq >= AVIC_NUM_IRQS)
  91                 return -EINVAL;
  92
  93         if (irq < AVIC_NUM_IRQS / 2) {
  94                 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
  95                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
  96         } else {
  97                 irq -= AVIC_NUM_IRQS / 2;
  98                 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
  99                 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
 100         }
 101
 102         return 0;
 103 }
 104 #endif /* CONFIG_FIQ */
 105
 106
 107 static struct mxc_extra_irq avic_extra_irq = {
 108 #ifdef CONFIG_MXC_IRQ_PRIOR
 109         .set_priority = avic_irq_set_priority,
 110 #endif
 111 #ifdef CONFIG_FIQ
 112         .set_irq_fiq = avic_set_irq_fiq,
 113 #endif
 114 };
 115
 116 #ifdef CONFIG_PM
 117 static void avic_irq_suspend(struct irq_data *d)
 118 {
 119         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 120         struct irq_chip_type *ct = gc->chip_types;
 121         int idx = d->hwirq >> 5;
 122
 123         avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
 124         __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
 125 }
 126
 127 static void avic_irq_resume(struct irq_data *d)
 128 {
 129         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 130         struct irq_chip_type *ct = gc->chip_types;
 131         int idx = d->hwirq >> 5;
 132
 133         __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 134 }
 135
 136 #else
 137 #define avic_irq_suspend NULL
 138 #define avic_irq_resume NULL
 139 #endif
 140
 141 static __init void avic_init_gc(int idx, unsigned int irq_start)
 142 {
 143         struct irq_chip_generic *gc;
 144         struct irq_chip_type *ct;
 145
 146         gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
 147                                     handle_level_irq);
 148         gc->private = &avic_extra_irq;
 149         gc->wake_enabled = IRQ_MSK(32);
 150
 151         ct = gc->chip_types;
 152         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 153         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 154         ct->chip.irq_ack = irq_gc_mask_clr_bit;
 155         ct->chip.irq_set_wake = irq_gc_set_wake;
 156         ct->chip.irq_suspend = avic_irq_suspend;
 157         ct->chip.irq_resume = avic_irq_resume;
 158         ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
 159         ct->regs.ack = ct->regs.mask;
 160
 161         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 162 }
 163
 164 asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
 165 {
 166         u32 nivector;
 167
 168         do {
 169                 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
 170                 if (nivector == 0xffff)
 171                         break;
 172
 173                 handle_IRQ(irq_find_mapping(domain, nivector), regs);
 174         } while (1);
 175 }
 176
 177 /*
 178  * This function initializes the AVIC hardware and disables all the
 179  * interrupts. It registers the interrupt enable and disable functions
 180  * to the kernel for each interrupt source.
 181  */
 182 void __init mxc_init_irq(void __iomem *irqbase)
 183 {
 184         struct device_node *np;
 185         int irq_base;
 186         int i;
 187
 188         avic_base = irqbase;
 189
 190         /* put the AVIC into the reset value with
 191          * all interrupts disabled
 192          */
 193         __raw_writel(0, avic_base + AVIC_INTCNTL);
 194         __raw_writel(0x1f, avic_base + AVIC_NIMASK);
 195
 196         /* disable all interrupts */
 197         __raw_writel(0, avic_base + AVIC_INTENABLEH);
 198         __raw_writel(0, avic_base + AVIC_INTENABLEL);
 199
 200         /* all IRQ no FIQ */
 201         __raw_writel(0, avic_base + AVIC_INTTYPEH);
 202         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 203
 204         irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
 205         WARN_ON(irq_base < 0);
 206
 207         np = of_find_compatible_node(NULL, NULL, "fsl,avic");
 208         domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
 209                                        &irq_domain_simple_ops, NULL);
 210         WARN_ON(!domain);
 211
 212         for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
 213                 avic_init_gc(i, irq_base);
 214
 215         /* Set default priority value (0) for all IRQ's */
 216         for (i = 0; i < 8; i++)
 217                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 218
 219 #ifdef CONFIG_FIQ
 220         /* Initialize FIQ */
 221         init_FIQ(FIQ_START);
 222 #endif
 223
 224         printk(KERN_INFO "MXC IRQ initialized\n");
 225 }