arch/arm/plat-mxc/dma-mx1-mx2.c

   1 /*
   2  *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
   3  *
   4  *  i.MX DMA registration and IRQ dispatching
   5  *
   6  * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
   7  * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
   8  * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301, USA.
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/errno.h>
  30 #include <linux/clk.h>
  31 #include <linux/scatterlist.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/system.h>
  35 #include <asm/irq.h>
  36 #include <mach/hardware.h>
  37 #include <mach/dma-mx1-mx2.h>
  38
  39 #define DMA_DCR     0x00                /* Control Register */
  40 #define DMA_DISR    0x04                /* Interrupt status Register */
  41 #define DMA_DIMR    0x08                /* Interrupt mask Register */
  42 #define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
  43 #define DMA_DRTOSR  0x10                /* Request timeout Register */
  44 #define DMA_DSESR   0x14                /* Transfer Error Status Register */
  45 #define DMA_DBOSR   0x18                /* Buffer overflow status Register */
  46 #define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
  47 #define DMA_WSRA    0x40                /* W-Size Register A */
  48 #define DMA_XSRA    0x44                /* X-Size Register A */
  49 #define DMA_YSRA    0x48                /* Y-Size Register A */
  50 #define DMA_WSRB    0x4c                /* W-Size Register B */
  51 #define DMA_XSRB    0x50                /* X-Size Register B */
  52 #define DMA_YSRB    0x54                /* Y-Size Register B */
  53 #define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
  54 #define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
  55 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
  56 #define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
  57 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
  58 #define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
  59 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
  60 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
  61 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
  62
  63 #define DCR_DRST           (1<<1)
  64 #define DCR_DEN            (1<<0)
  65 #define DBTOCR_EN          (1<<15)
  66 #define DBTOCR_CNT(x)      ((x) & 0x7fff)
  67 #define CNTR_CNT(x)        ((x) & 0xffffff)
  68 #define CCR_ACRPT          (1<<14)
  69 #define CCR_DMOD_LINEAR    (0x0 << 12)
  70 #define CCR_DMOD_2D        (0x1 << 12)
  71 #define CCR_DMOD_FIFO      (0x2 << 12)
  72 #define CCR_DMOD_EOBFIFO   (0x3 << 12)
  73 #define CCR_SMOD_LINEAR    (0x0 << 10)
  74 #define CCR_SMOD_2D        (0x1 << 10)
  75 #define CCR_SMOD_FIFO      (0x2 << 10)
  76 #define CCR_SMOD_EOBFIFO   (0x3 << 10)
  77 #define CCR_MDIR_DEC       (1<<9)
  78 #define CCR_MSEL_B         (1<<8)
  79 #define CCR_DSIZ_32        (0x0 << 6)
  80 #define CCR_DSIZ_8         (0x1 << 6)
  81 #define CCR_DSIZ_16        (0x2 << 6)
  82 #define CCR_SSIZ_32        (0x0 << 4)
  83 #define CCR_SSIZ_8         (0x1 << 4)
  84 #define CCR_SSIZ_16        (0x2 << 4)
  85 #define CCR_REN            (1<<3)
  86 #define CCR_RPT            (1<<2)
  87 #define CCR_FRC            (1<<1)
  88 #define CCR_CEN            (1<<0)
  89 #define RTOR_EN            (1<<15)
  90 #define RTOR_CLK           (1<<14)
  91 #define RTOR_PSC           (1<<13)
  92
  93 /*
  94  * struct imx_dma_channel - i.MX specific DMA extension
  95  * @name: name specified by DMA client
  96  * @irq_handler: client callback for end of transfer
  97  * @err_handler: client callback for error condition
  98  * @data: clients context data for callbacks
  99  * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
 100  * @sg: pointer to the actual read/written chunk for scatter-gather emulation
 101  * @resbytes: total residual number of bytes to transfer
 102  *            (it can be lower or same as sum of SG mapped chunk sizes)
 103  * @sgcount: number of chunks to be read/written
 104  *
 105  * Structure is used for IMX DMA processing. It would be probably good
 106  * @struct dma_struct in the future for external interfacing and use
 107  * @struct imx_dma_channel only as extension to it.
 108  */
 109
 110 struct imx_dma_channel {
 111         const char *name;
 112         void (*irq_handler) (int, void *);
 113         void (*err_handler) (int, void *, int errcode);
 114         void (*prog_handler) (int, void *, struct scatterlist *);
 115         void *data;
 116         unsigned int dma_mode;
 117         struct scatterlist *sg;
 118         unsigned int resbytes;
 119         int dma_num;
 120
 121         int in_use;
 122
 123         u32 ccr_from_device;
 124         u32 ccr_to_device;
 125
 126         struct timer_list watchdog;
 127
 128         int hw_chaining;
 129 };
 130
 131 static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
 132
 133 static struct clk *dma_clk;
 134
 135 static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
 136 {
 137         if (cpu_is_mx27())
 138                 return imxdma->hw_chaining;
 139         else
 140                 return 0;
 141 }
 142
 143
 144 /*
 145  * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
 146  */
 147 static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
 148 {
 149         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 150         unsigned long now;
 151
 152         if (!imxdma->name) {
 153                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 154                        __func__, channel);
 155                 return 0;
 156         }
 157
 158         now = min(imxdma->resbytes, sg->length);
 159         imxdma->resbytes -= now;
 160
 161         if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
 162                 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
 163         else
 164                 __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel));
 165
 166         __raw_writel(now, DMA_BASE + DMA_CNTR(channel));
 167
 168         pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
 169                 "size 0x%08x\n", channel,
 170                  __raw_readl(DMA_BASE + DMA_DAR(channel)),
 171                  __raw_readl(DMA_BASE + DMA_SAR(channel)),
 172                  __raw_readl(DMA_BASE + DMA_CNTR(channel)));
 173
 174         return now;
 175 }
 176
 177 /**
 178  * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
 179  * device transfer
 180  *
 181  * @channel: i.MX DMA channel number
 182  * @dma_address: the DMA/physical memory address of the linear data block
 183  *              to transfer
 184  * @dma_length: length of the data block in bytes
 185  * @dev_addr: physical device port address
 186  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 187  *           or %DMA_MODE_WRITE from memory to the device
 188  *
 189  * Return value: if incorrect parameters are provided -%EINVAL.
 190  *              Zero indicates success.
 191  */
 192 int
 193 imx_dma_setup_single(int channel, dma_addr_t dma_address,
 194                      unsigned int dma_length, unsigned int dev_addr,
 195                      unsigned int dmamode)
 196 {
 197         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 198
 199         imxdma->sg = NULL;
 200         imxdma->dma_mode = dmamode;
 201
 202         if (!dma_address) {
 203                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
 204                        channel);
 205                 return -EINVAL;
 206         }
 207
 208         if (!dma_length) {
 209                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
 210                        channel);
 211                 return -EINVAL;
 212         }
 213
 214         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 215                 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
 216                         "dev_addr=0x%08x for read\n",
 217                         channel, __func__, (unsigned int)dma_address,
 218                         dma_length, dev_addr);
 219
 220                 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
 221                 __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel));
 222                 __raw_writel(imxdma->ccr_from_device,
 223                                 DMA_BASE + DMA_CCR(channel));
 224         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 225                 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
 226                         "dev_addr=0x%08x for write\n",
 227                         channel, __func__, (unsigned int)dma_address,
 228                         dma_length, dev_addr);
 229
 230                 __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel));
 231                 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
 232                 __raw_writel(imxdma->ccr_to_device,
 233                                 DMA_BASE + DMA_CCR(channel));
 234         } else {
 235                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
 236                        channel);
 237                 return -EINVAL;
 238         }
 239
 240         __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel));
 241
 242         return 0;
 243 }
 244 EXPORT_SYMBOL(imx_dma_setup_single);
 245
 246 /**
 247  * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
 248  * @channel: i.MX DMA channel number
 249  * @sg: pointer to the scatter-gather list/vector
 250  * @sgcount: scatter-gather list hungs count
 251  * @dma_length: total length of the transfer request in bytes
 252  * @dev_addr: physical device port address
 253  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 254  *           or %DMA_MODE_WRITE from memory to the device
 255  *
 256  * The function sets up DMA channel state and registers to be ready for
 257  * transfer specified by provided parameters. The scatter-gather emulation
 258  * is set up according to the parameters.
 259  *
 260  * The full preparation of the transfer requires setup of more register
 261  * by the caller before imx_dma_enable() can be called.
 262  *
 263  * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
 264  *
 265  * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
 266  *
 267  * %CCR(channel) has to specify transfer parameters, the next settings is
 268  * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
 269  * specified
 270  *
 271  * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
 272  *
 273  * The typical setup for %DMA_MODE_WRITE is specified by next options
 274  * combination
 275  *
 276  * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
 277  *
 278  * Be careful here and do not mistakenly mix source and target device
 279  * port sizes constants, they are really different:
 280  * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
 281  * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
 282  *
 283  * Return value: if incorrect parameters are provided -%EINVAL.
 284  * Zero indicates success.
 285  */
 286 int
 287 imx_dma_setup_sg(int channel,
 288                  struct scatterlist *sg, unsigned int sgcount,
 289                  unsigned int dma_length, unsigned int dev_addr,
 290                  unsigned int dmamode)
 291 {
 292         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 293
 294         if (imxdma->in_use)
 295                 return -EBUSY;
 296
 297         imxdma->sg = sg;
 298         imxdma->dma_mode = dmamode;
 299         imxdma->resbytes = dma_length;
 300
 301         if (!sg || !sgcount) {
 302                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
 303                        channel);
 304                 return -EINVAL;
 305         }
 306
 307         if (!sg->length) {
 308                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
 309                        channel);
 310                 return -EINVAL;
 311         }
 312
 313         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 314                 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 315                         "dev_addr=0x%08x for read\n",
 316                         channel, __func__, sg, sgcount, dma_length, dev_addr);
 317
 318                 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
 319                 __raw_writel(imxdma->ccr_from_device,
 320                                 DMA_BASE + DMA_CCR(channel));
 321         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 322                 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 323                         "dev_addr=0x%08x for write\n",
 324                         channel, __func__, sg, sgcount, dma_length, dev_addr);
 325
 326                 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
 327                 __raw_writel(imxdma->ccr_to_device,
 328                                 DMA_BASE + DMA_CCR(channel));
 329         } else {
 330                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
 331                        channel);
 332                 return -EINVAL;
 333         }
 334
 335         imx_dma_sg_next(channel, sg);
 336
 337         return 0;
 338 }
 339 EXPORT_SYMBOL(imx_dma_setup_sg);
 340
 341 int
 342 imx_dma_config_channel(int channel, unsigned int config_port,
 343         unsigned int config_mem, unsigned int dmareq, int hw_chaining)
 344 {
 345         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 346         u32 dreq = 0;
 347
 348         imxdma->hw_chaining = 0;
 349
 350         if (hw_chaining) {
 351                 imxdma->hw_chaining = 1;
 352                 if (!imx_dma_hw_chain(imxdma))
 353                         return -EINVAL;
 354         }
 355
 356         if (dmareq)
 357                 dreq = CCR_REN;
 358
 359         imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
 360         imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
 361
 362         __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel));
 363
 364         return 0;
 365 }
 366 EXPORT_SYMBOL(imx_dma_config_channel);
 367
 368 void imx_dma_config_burstlen(int channel, unsigned int burstlen)
 369 {
 370         __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel));
 371 }
 372 EXPORT_SYMBOL(imx_dma_config_burstlen);
 373
 374 /**
 375  * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
 376  * handlers
 377  * @channel: i.MX DMA channel number
 378  * @irq_handler: the pointer to the function called if the transfer
 379  *              ends successfully
 380  * @err_handler: the pointer to the function called if the premature
 381  *              end caused by error occurs
 382  * @data: user specified value to be passed to the handlers
 383  */
 384 int
 385 imx_dma_setup_handlers(int channel,
 386                        void (*irq_handler) (int, void *),
 387                        void (*err_handler) (int, void *, int),
 388                        void *data)
 389 {
 390         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 391         unsigned long flags;
 392
 393         if (!imxdma->name) {
 394                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 395                        __func__, channel);
 396                 return -ENODEV;
 397         }
 398
 399         local_irq_save(flags);
 400         __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
 401         imxdma->irq_handler = irq_handler;
 402         imxdma->err_handler = err_handler;
 403         imxdma->data = data;
 404         local_irq_restore(flags);
 405         return 0;
 406 }
 407 EXPORT_SYMBOL(imx_dma_setup_handlers);
 408
 409 /**
 410  * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
 411  * handlers
 412  * @channel: i.MX DMA channel number
 413  * @prog_handler: the pointer to the function called if the transfer progresses
 414  */
 415 int
 416 imx_dma_setup_progression_handler(int channel,
 417                         void (*prog_handler) (int, void*, struct scatterlist*))
 418 {
 419         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 420         unsigned long flags;
 421
 422         if (!imxdma->name) {
 423                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 424                        __func__, channel);
 425                 return -ENODEV;
 426         }
 427
 428         local_irq_save(flags);
 429         imxdma->prog_handler = prog_handler;
 430         local_irq_restore(flags);
 431         return 0;
 432 }
 433 EXPORT_SYMBOL(imx_dma_setup_progression_handler);
 434
 435 /**
 436  * imx_dma_enable - function to start i.MX DMA channel operation
 437  * @channel: i.MX DMA channel number
 438  *
 439  * The channel has to be allocated by driver through imx_dma_request()
 440  * or imx_dma_request_by_prio() function.
 441  * The transfer parameters has to be set to the channel registers through
 442  * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
 443  * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
 444  * be set prior this function call by the channel user.
 445  */
 446 void imx_dma_enable(int channel)
 447 {
 448         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 449         unsigned long flags;
 450
 451         pr_debug("imxdma%d: imx_dma_enable\n", channel);
 452
 453         if (!imxdma->name) {
 454                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 455                        __func__, channel);
 456                 return;
 457         }
 458
 459         if (imxdma->in_use)
 460                 return;
 461
 462         local_irq_save(flags);
 463
 464         __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
 465         __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel),
 466                 DMA_BASE + DMA_DIMR);
 467         __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN |
 468                 CCR_ACRPT,
 469                 DMA_BASE + DMA_CCR(channel));
 470
 471 #ifdef CONFIG_ARCH_MX2
 472         if (imxdma->sg && imx_dma_hw_chain(imxdma)) {
 473                 imxdma->sg = sg_next(imxdma->sg);
 474                 if (imxdma->sg) {
 475                         u32 tmp;
 476                         imx_dma_sg_next(channel, imxdma->sg);
 477                         tmp = __raw_readl(DMA_BASE + DMA_CCR(channel));
 478                         __raw_writel(tmp | CCR_RPT | CCR_ACRPT,
 479                                 DMA_BASE + DMA_CCR(channel));
 480                 }
 481         }
 482 #endif
 483         imxdma->in_use = 1;
 484
 485         local_irq_restore(flags);
 486 }
 487 EXPORT_SYMBOL(imx_dma_enable);
 488
 489 /**
 490  * imx_dma_disable - stop, finish i.MX DMA channel operatin
 491  * @channel: i.MX DMA channel number
 492  */
 493 void imx_dma_disable(int channel)
 494 {
 495         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 496         unsigned long flags;
 497
 498         pr_debug("imxdma%d: imx_dma_disable\n", channel);
 499
 500         if (imx_dma_hw_chain(imxdma))
 501                 del_timer(&imxdma->watchdog);
 502
 503         local_irq_save(flags);
 504         __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
 505                 DMA_BASE + DMA_DIMR);
 506         __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
 507                 DMA_BASE + DMA_CCR(channel));
 508         __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
 509         imxdma->in_use = 0;
 510         local_irq_restore(flags);
 511 }
 512 EXPORT_SYMBOL(imx_dma_disable);
 513
 514 #ifdef CONFIG_ARCH_MX2
 515 static void imx_dma_watchdog(unsigned long chno)
 516 {
 517         struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
 518
 519         __raw_writel(0, DMA_BASE + DMA_CCR(chno));
 520         imxdma->in_use = 0;
 521         imxdma->sg = NULL;
 522
 523         if (imxdma->err_handler)
 524                 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
 525 }
 526 #endif
 527
 528 static irqreturn_t dma_err_handler(int irq, void *dev_id)
 529 {
 530         int i, disr;
 531         struct imx_dma_channel *imxdma;
 532         unsigned int err_mask;
 533         int errcode;
 534
 535         disr = __raw_readl(DMA_BASE + DMA_DISR);
 536
 537         err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) |
 538                    __raw_readl(DMA_BASE + DMA_DRTOSR) |
 539                    __raw_readl(DMA_BASE + DMA_DSESR)  |
 540                    __raw_readl(DMA_BASE + DMA_DBOSR);
 541
 542         if (!err_mask)
 543                 return IRQ_HANDLED;
 544
 545         __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR);
 546
 547         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 548                 if (!(err_mask & (1 << i)))
 549                         continue;
 550                 imxdma = &imx_dma_channels[i];
 551                 errcode = 0;
 552
 553                 if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) {
 554                         __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR);
 555                         errcode |= IMX_DMA_ERR_BURST;
 556                 }
 557                 if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) {
 558                         __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR);
 559                         errcode |= IMX_DMA_ERR_REQUEST;
 560                 }
 561                 if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) {
 562                         __raw_writel(1 << i, DMA_BASE + DMA_DSESR);
 563                         errcode |= IMX_DMA_ERR_TRANSFER;
 564                 }
 565                 if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) {
 566                         __raw_writel(1 << i, DMA_BASE + DMA_DBOSR);
 567                         errcode |= IMX_DMA_ERR_BUFFER;
 568                 }
 569                 if (imxdma->name && imxdma->err_handler) {
 570                         imxdma->err_handler(i, imxdma->data, errcode);
 571                         continue;
 572                 }
 573
 574                 imx_dma_channels[i].sg = NULL;
 575
 576                 printk(KERN_WARNING
 577                        "DMA timeout on channel %d (%s) -%s%s%s%s\n",
 578                        i, imxdma->name,
 579                        errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
 580                        errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
 581                        errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
 582                        errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
 583         }
 584         return IRQ_HANDLED;
 585 }
 586
 587 static void dma_irq_handle_channel(int chno)
 588 {
 589         struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
 590
 591         if (!imxdma->name) {
 592                 /*
 593                  * IRQ for an unregistered DMA channel:
 594                  * let's clear the interrupts and disable it.
 595                  */
 596                 printk(KERN_WARNING
 597                        "spurious IRQ for DMA channel %d\n", chno);
 598                 return;
 599         }
 600
 601         if (imxdma->sg) {
 602                 u32 tmp;
 603                 struct scatterlist *current_sg = imxdma->sg;
 604                 imxdma->sg = sg_next(imxdma->sg);
 605
 606                 if (imxdma->sg) {
 607                         imx_dma_sg_next(chno, imxdma->sg);
 608
 609                         tmp = __raw_readl(DMA_BASE + DMA_CCR(chno));
 610
 611                         if (imx_dma_hw_chain(imxdma)) {
 612                                 /* FIXME: The timeout should probably be
 613                                  * configurable
 614                                  */
 615                                 mod_timer(&imxdma->watchdog,
 616                                         jiffies + msecs_to_jiffies(500));
 617
 618                                 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
 619                                 __raw_writel(tmp, DMA_BASE +
 620                                                 DMA_CCR(chno));
 621                         } else {
 622                                 __raw_writel(tmp & ~CCR_CEN, DMA_BASE +
 623                                                 DMA_CCR(chno));
 624                                 tmp |= CCR_CEN;
 625                         }
 626
 627                         __raw_writel(tmp, DMA_BASE + DMA_CCR(chno));
 628
 629                         if (imxdma->prog_handler)
 630                                 imxdma->prog_handler(chno, imxdma->data,
 631                                                 current_sg);
 632
 633                         return;
 634                 }
 635
 636                 if (imx_dma_hw_chain(imxdma)) {
 637                         del_timer(&imxdma->watchdog);
 638                         return;
 639                 }
 640         }
 641
 642         __raw_writel(0, DMA_BASE + DMA_CCR(chno));
 643         imxdma->in_use = 0;
 644         if (imxdma->irq_handler)
 645                 imxdma->irq_handler(chno, imxdma->data);
 646 }
 647
 648 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 649 {
 650         int i, disr;
 651
 652 #ifdef CONFIG_ARCH_MX2
 653         dma_err_handler(irq, dev_id);
 654 #endif
 655
 656         disr = __raw_readl(DMA_BASE + DMA_DISR);
 657
 658         pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 659                      disr);
 660
 661         __raw_writel(disr, DMA_BASE + DMA_DISR);
 662         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 663                 if (disr & (1 << i))
 664                         dma_irq_handle_channel(i);
 665         }
 666
 667         return IRQ_HANDLED;
 668 }
 669
 670 /**
 671  * imx_dma_request - request/allocate specified channel number
 672  * @channel: i.MX DMA channel number
 673  * @name: the driver/caller own non-%NULL identification
 674  */
 675 int imx_dma_request(int channel, const char *name)
 676 {
 677         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 678         unsigned long flags;
 679         int ret = 0;
 680
 681         /* basic sanity checks */
 682         if (!name)
 683                 return -EINVAL;
 684
 685         if (channel >= IMX_DMA_CHANNELS) {
 686                 printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
 687                        __func__, channel);
 688                 return -EINVAL;
 689         }
 690
 691         local_irq_save(flags);
 692         if (imxdma->name) {
 693                 local_irq_restore(flags);
 694                 return -EBUSY;
 695         }
 696         memset(imxdma, 0, sizeof(imxdma));
 697         imxdma->name = name;
 698         local_irq_restore(flags); /* request_irq() can block */
 699
 700 #ifdef CONFIG_ARCH_MX2
 701         ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
 702                         NULL);
 703         if (ret) {
 704                 imxdma->name = NULL;
 705                 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
 706                                 MXC_INT_DMACH0 + channel, channel);
 707                 return ret;
 708         }
 709         init_timer(&imxdma->watchdog);
 710         imxdma->watchdog.function = &imx_dma_watchdog;
 711         imxdma->watchdog.data = channel;
 712 #endif
 713
 714         return ret;
 715 }
 716 EXPORT_SYMBOL(imx_dma_request);
 717
 718 /**
 719  * imx_dma_free - release previously acquired channel
 720  * @channel: i.MX DMA channel number
 721  */
 722 void imx_dma_free(int channel)
 723 {
 724         unsigned long flags;
 725         struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
 726
 727         if (!imxdma->name) {
 728                 printk(KERN_CRIT
 729                        "%s: trying to free free channel %d\n",
 730                        __func__, channel);
 731                 return;
 732         }
 733
 734         local_irq_save(flags);
 735         /* Disable interrupts */
 736         imx_dma_disable(channel);
 737         imxdma->name = NULL;
 738
 739 #ifdef CONFIG_ARCH_MX2
 740         free_irq(MXC_INT_DMACH0 + channel, NULL);
 741 #endif
 742
 743         local_irq_restore(flags);
 744 }
 745 EXPORT_SYMBOL(imx_dma_free);
 746
 747 /**
 748  * imx_dma_request_by_prio - find and request some of free channels best
 749  * suiting requested priority
 750  * @channel: i.MX DMA channel number
 751  * @name: the driver/caller own non-%NULL identification
 752  *
 753  * This function tries to find a free channel in the specified priority group
 754  * This function tries to find a free channel in the specified priority group
 755  * if the priority cannot be achieved it tries to look for free channel
 756  * in the higher and then even lower priority groups.
 757  *
 758  * Return value: If there is no free channel to allocate, -%ENODEV is returned.
 759  *               On successful allocation channel is returned.
 760  */
 761 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
 762 {
 763         int i;
 764         int best;
 765
 766         switch (prio) {
 767         case (DMA_PRIO_HIGH):
 768                 best = 8;
 769                 break;
 770         case (DMA_PRIO_MEDIUM):
 771                 best = 4;
 772                 break;
 773         case (DMA_PRIO_LOW):
 774         default:
 775                 best = 0;
 776                 break;
 777         }
 778
 779         for (i = best; i < IMX_DMA_CHANNELS; i++)
 780                 if (!imx_dma_request(i, name))
 781                         return i;
 782
 783         for (i = best - 1; i >= 0; i--)
 784                 if (!imx_dma_request(i, name))
 785                         return i;
 786
 787         printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
 788
 789         return -ENODEV;
 790 }
 791 EXPORT_SYMBOL(imx_dma_request_by_prio);
 792
 793 static int __init imx_dma_init(void)
 794 {
 795         int ret = 0;
 796         int i;
 797
 798         dma_clk = clk_get(NULL, "dma");
 799         clk_enable(dma_clk);
 800
 801         /* reset DMA module */
 802         __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR);
 803
 804 #ifdef CONFIG_ARCH_MX1
 805         ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
 806         if (ret) {
 807                 printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
 808                 return ret;
 809         }
 810
 811         ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
 812         if (ret) {
 813                 printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
 814                 free_irq(DMA_INT, NULL);
 815                 return ret;
 816         }
 817 #endif
 818         /* enable DMA module */
 819         __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR);
 820
 821         /* clear all interrupts */
 822         __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR);
 823
 824         /* disable interrupts */
 825         __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR);
 826
 827         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 828                 imx_dma_channels[i].sg = NULL;
 829                 imx_dma_channels[i].dma_num = i;
 830         }
 831
 832         return ret;
 833 }
 834
 835 arch_initcall(imx_dma_init);