arch/arm/plat-mxc/gpio.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/irq.h>
  25 #include <linux/gpio.h>
  26 #include <mach/hardware.h>
  27 #include <asm-generic/bug.h>
  28
  29 static struct mxc_gpio_port *mxc_gpio_ports;
  30 static int gpio_table_size;
  31
  32 #define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
  33
  34 #define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
  35 #define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
  36 #define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
  37 #define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
  38 #define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
  39 #define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
  40 #define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
  41
  42 #define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
  43 #define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
  44 #define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
  45 #define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
  46 #define GPIO_INT_NONE           0x4
  47
  48 /* Note: This driver assumes 32 GPIOs are handled in one register */
  49
  50 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
  51 {
  52         __raw_writel(1 << index, port->base + GPIO_ISR);
  53 }
  54
  55 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
  56                                 int enable)
  57 {
  58         u32 l;
  59
  60         l = __raw_readl(port->base + GPIO_IMR);
  61         l = (l & (~(1 << index))) | (!!enable << index);
  62         __raw_writel(l, port->base + GPIO_IMR);
  63 }
  64
  65 static void gpio_ack_irq(u32 irq)
  66 {
  67         u32 gpio = irq_to_gpio(irq);
  68         _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
  69 }
  70
  71 static void gpio_mask_irq(u32 irq)
  72 {
  73         u32 gpio = irq_to_gpio(irq);
  74         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
  75 }
  76
  77 static void gpio_unmask_irq(u32 irq)
  78 {
  79         u32 gpio = irq_to_gpio(irq);
  80         _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
  81 }
  82
  83 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
  84
  85 static int gpio_set_irq_type(u32 irq, u32 type)
  86 {
  87         u32 gpio = irq_to_gpio(irq);
  88         struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
  89         u32 bit, val;
  90         int edge;
  91         void __iomem *reg = port->base;
  92
  93         port->both_edges &= ~(1 << (gpio & 31));
  94         switch (type) {
  95         case IRQ_TYPE_EDGE_RISING:
  96                 edge = GPIO_INT_RISE_EDGE;
  97                 break;
  98         case IRQ_TYPE_EDGE_FALLING:
  99                 edge = GPIO_INT_FALL_EDGE;
 100                 break;
 101         case IRQ_TYPE_EDGE_BOTH:
 102                 val = mxc_gpio_get(&port->chip, gpio & 31);
 103                 if (val) {
 104                         edge = GPIO_INT_LOW_LEV;
 105                         pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 106                 } else {
 107                         edge = GPIO_INT_HIGH_LEV;
 108                         pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 109                 }
 110                 port->both_edges |= 1 << (gpio & 31);
 111                 break;
 112         case IRQ_TYPE_LEVEL_LOW:
 113                 edge = GPIO_INT_LOW_LEV;
 114                 break;
 115         case IRQ_TYPE_LEVEL_HIGH:
 116                 edge = GPIO_INT_HIGH_LEV;
 117                 break;
 118         default:
 119                 return -EINVAL;
 120         }
 121
 122         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 123         bit = gpio & 0xf;
 124         val = __raw_readl(reg) & ~(0x3 << (bit << 1));
 125         __raw_writel(val | (edge << (bit << 1)), reg);
 126         _clear_gpio_irqstatus(port, gpio & 0x1f);
 127
 128         return 0;
 129 }
 130
 131 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 132 {
 133         void __iomem *reg = port->base;
 134         u32 bit, val;
 135         int edge;
 136
 137         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 138         bit = gpio & 0xf;
 139         val = __raw_readl(reg);
 140         edge = (val >> (bit << 1)) & 3;
 141         val &= ~(0x3 << (bit << 1));
 142         if (edge == GPIO_INT_HIGH_LEV) {
 143                 edge = GPIO_INT_LOW_LEV;
 144                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 145         } else if (edge == GPIO_INT_LOW_LEV) {
 146                 edge = GPIO_INT_HIGH_LEV;
 147                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 148         } else {
 149                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 150                        gpio, edge);
 151                 return;
 152         }
 153         __raw_writel(val | (edge << (bit << 1)), reg);
 154 }
 155
 156 /* handle 32 interrupts in one status register */
 157 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 158 {
 159         u32 gpio_irq_no_base = port->virtual_irq_start;
 160
 161         while (irq_stat != 0) {
 162                 int irqoffset = fls(irq_stat) - 1;
 163
 164                 if (port->both_edges & (1 << irqoffset))
 165                         mxc_flip_edge(port, irqoffset);
 166
 167                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 168
 169                 irq_stat &= ~(1 << irqoffset);
 170         }
 171 }
 172
 173 /* MX1 and MX3 has one interrupt *per* gpio port */
 174 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 175 {
 176         u32 irq_stat;
 177         struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
 178
 179         irq_stat = __raw_readl(port->base + GPIO_ISR) &
 180                         __raw_readl(port->base + GPIO_IMR);
 181
 182         mxc_gpio_irq_handler(port, irq_stat);
 183 }
 184
 185 /* MX2 has one interrupt *for all* gpio ports */
 186 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 187 {
 188         int i;
 189         u32 irq_msk, irq_stat;
 190         struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
 191
 192         /* walk through all interrupt status registers */
 193         for (i = 0; i < gpio_table_size; i++) {
 194                 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
 195                 if (!irq_msk)
 196                         continue;
 197
 198                 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
 199                 if (irq_stat)
 200                         mxc_gpio_irq_handler(&port[i], irq_stat);
 201         }
 202 }
 203
 204 static struct irq_chip gpio_irq_chip = {
 205         .ack = gpio_ack_irq,
 206         .mask = gpio_mask_irq,
 207         .unmask = gpio_unmask_irq,
 208         .set_type = gpio_set_irq_type,
 209 };
 210
 211 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 212                                 int dir)
 213 {
 214         struct mxc_gpio_port *port =
 215                 container_of(chip, struct mxc_gpio_port, chip);
 216         u32 l;
 217
 218         l = __raw_readl(port->base + GPIO_GDIR);
 219         if (dir)
 220                 l |= 1 << offset;
 221         else
 222                 l &= ~(1 << offset);
 223         __raw_writel(l, port->base + GPIO_GDIR);
 224 }
 225
 226 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 227 {
 228         struct mxc_gpio_port *port =
 229                 container_of(chip, struct mxc_gpio_port, chip);
 230         void __iomem *reg = port->base + GPIO_DR;
 231         u32 l;
 232
 233         l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
 234         __raw_writel(l, reg);
 235 }
 236
 237 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
 238 {
 239         struct mxc_gpio_port *port =
 240                 container_of(chip, struct mxc_gpio_port, chip);
 241
 242         return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
 243 }
 244
 245 static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 246 {
 247         _set_gpio_direction(chip, offset, 0);
 248         return 0;
 249 }
 250
 251 static int mxc_gpio_direction_output(struct gpio_chip *chip,
 252                                      unsigned offset, int value)
 253 {
 254         mxc_gpio_set(chip, offset, value);
 255         _set_gpio_direction(chip, offset, 1);
 256         return 0;
 257 }
 258
 259 int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 260 {
 261         int i, j;
 262
 263         /* save for local usage */
 264         mxc_gpio_ports = port;
 265         gpio_table_size = cnt;
 266
 267         printk(KERN_INFO "MXC GPIO hardware\n");
 268
 269         for (i = 0; i < cnt; i++) {
 270                 /* disable the interrupt and clear the status */
 271                 __raw_writel(0, port[i].base + GPIO_IMR);
 272                 __raw_writel(~0, port[i].base + GPIO_ISR);
 273                 for (j = port[i].virtual_irq_start;
 274                         j < port[i].virtual_irq_start + 32; j++) {
 275                         set_irq_chip(j, &gpio_irq_chip);
 276                         set_irq_handler(j, handle_level_irq);
 277                         set_irq_flags(j, IRQF_VALID);
 278                 }
 279
 280                 /* register gpio chip */
 281                 port[i].chip.direction_input = mxc_gpio_direction_input;
 282                 port[i].chip.direction_output = mxc_gpio_direction_output;
 283                 port[i].chip.get = mxc_gpio_get;
 284                 port[i].chip.set = mxc_gpio_set;
 285                 port[i].chip.base = i * 32;
 286                 port[i].chip.ngpio = 32;
 287
 288                 /* its a serious configuration bug when it fails */
 289                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 290
 291                 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
 292                         /* setup one handler for each entry */
 293                         set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
 294                         set_irq_data(port[i].irq, &port[i]);
 295                 }
 296         }
 297
 298         if (cpu_is_mx2()) {
 299                 /* setup one handler for all GPIO interrupts */
 300                 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
 301                 set_irq_data(port[0].irq, port);
 302         }
 303
 304         return 0;
 305 }