arch/arm/plat-mxc/irq.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <mach/common.h>
  23
  24 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
  25 #define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
  26 #define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
  27 #define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
  28 #define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
  29 #define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
  30 #define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
  31 #define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
  32 #define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
  33 #define AVIC_NIPRIORITY(x)      (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
  34 #define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
  35 #define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
  36 #define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
  37 #define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
  38 #define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
  39 #define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
  40 #define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
  41 #define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
  42 #define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
  43 #define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
  44
  45 #define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
  46 #define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
  47 #define IIM_PROD_REV_SH         3
  48 #define IIM_PROD_REV_LEN        5
  49
  50 #ifdef CONFIG_MXC_IRQ_PRIOR
  51 void imx_irq_set_priority(unsigned char irq, unsigned char prio)
  52 {
  53         unsigned int temp;
  54         unsigned int mask = 0x0F << irq % 8 * 4;
  55
  56         if (irq > 63)
  57                 return;
  58
  59         temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
  60         temp &= ~mask;
  61         temp |= prio & mask;
  62
  63         __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
  64 }
  65 EXPORT_SYMBOL(imx_irq_set_priority);
  66 #endif
  67
  68 /* Disable interrupt number "irq" in the AVIC */
  69 static void mxc_mask_irq(unsigned int irq)
  70 {
  71         __raw_writel(irq, AVIC_INTDISNUM);
  72 }
  73
  74 /* Enable interrupt number "irq" in the AVIC */
  75 static void mxc_unmask_irq(unsigned int irq)
  76 {
  77         __raw_writel(irq, AVIC_INTENNUM);
  78 }
  79
  80 static struct irq_chip mxc_avic_chip = {
  81         .ack = mxc_mask_irq,
  82         .mask = mxc_mask_irq,
  83         .unmask = mxc_unmask_irq,
  84 };
  85
  86 /*
  87  * This function initializes the AVIC hardware and disables all the
  88  * interrupts. It registers the interrupt enable and disable functions
  89  * to the kernel for each interrupt source.
  90  */
  91 void __init mxc_init_irq(void)
  92 {
  93         int i;
  94         u32 reg;
  95
  96         /* put the AVIC into the reset value with
  97          * all interrupts disabled
  98          */
  99         __raw_writel(0, AVIC_INTCNTL);
 100         __raw_writel(0x1f, AVIC_NIMASK);
 101
 102         /* disable all interrupts */
 103         __raw_writel(0, AVIC_INTENABLEH);
 104         __raw_writel(0, AVIC_INTENABLEL);
 105
 106         /* all IRQ no FIQ */
 107         __raw_writel(0, AVIC_INTTYPEH);
 108         __raw_writel(0, AVIC_INTTYPEL);
 109         for (i = 0; i < MXC_MAX_INT_LINES; i++) {
 110                 set_irq_chip(i, &mxc_avic_chip);
 111                 set_irq_handler(i, handle_level_irq);
 112                 set_irq_flags(i, IRQF_VALID);
 113         }
 114
 115         /* Set default priority value (0) for all IRQ's */
 116         for (i = 0; i < 8; i++)
 117                 __raw_writel(0, AVIC_NIPRIORITY(i));
 118
 119         /* init architectures chained interrupt handler */
 120         mxc_register_gpios();
 121
 122         printk(KERN_INFO "MXC IRQ initialized\n");
 123 }